1 /*
2 * QEMU emulation of an RISC-V IOMMU
3 *
4 * Copyright (C) 2022-2023 Rivos Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include "qemu/osdep.h"
20 #include "exec/target_page.h"
21 #include "hw/pci/msi.h"
22 #include "hw/pci/msix.h"
23 #include "hw/pci/pci_bus.h"
24 #include "hw/qdev-properties.h"
25 #include "hw/riscv/riscv_hart.h"
26 #include "migration/vmstate.h"
27 #include "qapi/error.h"
28 #include "qemu/error-report.h"
29 #include "qemu/host-utils.h"
30 #include "qom/object.h"
31
32 #include "cpu_bits.h"
33 #include "riscv-iommu.h"
34 #include "riscv-iommu-bits.h"
35 #include "trace.h"
36
37 /* RISC-V IOMMU PCI Device Emulation */
38 #define RISCV_PCI_CLASS_SYSTEM_IOMMU 0x0806
39
40 /*
41 * 4 MSIx vectors for ICVEC, one for MRIF. The spec mentions in
42 * the "Placement and data flow" section that:
43 *
44 * "The interfaces related to recording an incoming MSI in a memory-resident
45 * interrupt file (MRIF) are implementation-specific. The partitioning of
46 * responsibility between the IOMMU and the IO bridge for recording the
47 * incoming MSI in an MRIF and generating the associated notice MSI are
48 * implementation-specific."
49 *
50 * We're making a design decision to create the MSIx for MRIF in the
51 * IOMMU MSIx emulation.
52 */
53 #define RISCV_IOMMU_PCI_MSIX_VECTORS 5
54
55 /*
56 * 4 vectors that can be used by civ, fiv, pmiv and piv. Number of
57 * vectors is represented by 2^N, where N = number of writable bits
58 * in each cause. For 4 vectors we'll write 0b11 (3) in each reg.
59 */
60 #define RISCV_IOMMU_PCI_ICVEC_VECTORS 0x3333
61
62 typedef struct RISCVIOMMUStatePci {
63 PCIDevice pci; /* Parent PCIe device state */
64 uint16_t vendor_id;
65 uint16_t device_id;
66 uint8_t revision;
67 MemoryRegion bar0; /* PCI BAR (including MSI-x config) */
68 RISCVIOMMUState iommu; /* common IOMMU state */
69 } RISCVIOMMUStatePci;
70
71 struct RISCVIOMMUPciClass {
72 /*< public >*/
73 DeviceRealize parent_realize;
74 ResettablePhases parent_phases;
75 };
76
77 /* interrupt delivery callback */
riscv_iommu_pci_notify(RISCVIOMMUState * iommu,unsigned vector)78 static void riscv_iommu_pci_notify(RISCVIOMMUState *iommu, unsigned vector)
79 {
80 RISCVIOMMUStatePci *s = container_of(iommu, RISCVIOMMUStatePci, iommu);
81
82 if (msix_enabled(&(s->pci))) {
83 msix_notify(&(s->pci), vector);
84 }
85 }
86
riscv_iommu_pci_realize(PCIDevice * dev,Error ** errp)87 static void riscv_iommu_pci_realize(PCIDevice *dev, Error **errp)
88 {
89 RISCVIOMMUStatePci *s = DO_UPCAST(RISCVIOMMUStatePci, pci, dev);
90 RISCVIOMMUState *iommu = &s->iommu;
91 uint8_t *pci_conf = dev->config;
92 Error *err = NULL;
93
94 pci_set_word(pci_conf + PCI_VENDOR_ID, s->vendor_id);
95 pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, s->vendor_id);
96 pci_set_word(pci_conf + PCI_DEVICE_ID, s->device_id);
97 pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, s->device_id);
98 pci_set_byte(pci_conf + PCI_REVISION_ID, s->revision);
99
100 /* Set device id for trace / debug */
101 DEVICE(iommu)->id = g_strdup_printf("%02x:%02x.%01x",
102 pci_dev_bus_num(dev), PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
103 qdev_realize(DEVICE(iommu), NULL, errp);
104
105 memory_region_init(&s->bar0, OBJECT(s), "riscv-iommu-bar0",
106 QEMU_ALIGN_UP(memory_region_size(&iommu->regs_mr), TARGET_PAGE_SIZE));
107 memory_region_add_subregion(&s->bar0, 0, &iommu->regs_mr);
108
109 pcie_endpoint_cap_init(dev, 0);
110
111 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
112 PCI_BASE_ADDRESS_MEM_TYPE_64, &s->bar0);
113
114 int ret = msix_init(dev, RISCV_IOMMU_PCI_MSIX_VECTORS,
115 &s->bar0, 0, RISCV_IOMMU_REG_MSI_CONFIG,
116 &s->bar0, 0, RISCV_IOMMU_REG_MSI_CONFIG + 256, 0, &err);
117
118 if (ret == -ENOTSUP) {
119 /*
120 * MSI-x is not supported by the platform.
121 * Driver should use timer/polling based notification handlers.
122 */
123 warn_report_err(err);
124 } else if (ret < 0) {
125 error_propagate(errp, err);
126 return;
127 } else {
128 /* Mark all ICVEC MSIx vectors as used */
129 for (int i = 0; i < RISCV_IOMMU_PCI_MSIX_VECTORS; i++) {
130 msix_vector_use(dev, i);
131 }
132
133 iommu->notify = riscv_iommu_pci_notify;
134 }
135
136 PCIBus *bus = pci_device_root_bus(dev);
137 if (!bus) {
138 error_setg(errp, "can't find PCIe root port for %02x:%02x.%x",
139 pci_bus_num(pci_get_bus(dev)), PCI_SLOT(dev->devfn),
140 PCI_FUNC(dev->devfn));
141 return;
142 }
143
144 riscv_iommu_pci_setup_iommu(iommu, bus, errp);
145 }
146
riscv_iommu_pci_exit(PCIDevice * pci_dev)147 static void riscv_iommu_pci_exit(PCIDevice *pci_dev)
148 {
149 pci_setup_iommu(pci_device_root_bus(pci_dev), NULL, NULL);
150 }
151
152 static const VMStateDescription riscv_iommu_vmstate = {
153 .name = "riscv-iommu",
154 .unmigratable = 1
155 };
156
riscv_iommu_pci_init(Object * obj)157 static void riscv_iommu_pci_init(Object *obj)
158 {
159 RISCVIOMMUStatePci *s = RISCV_IOMMU_PCI(obj);
160 RISCVIOMMUState *iommu = &s->iommu;
161
162 object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU);
163 qdev_alias_all_properties(DEVICE(iommu), obj);
164
165 iommu->icvec_avail_vectors = RISCV_IOMMU_PCI_ICVEC_VECTORS;
166 riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_MSI);
167 }
168
169 static const Property riscv_iommu_pci_properties[] = {
170 DEFINE_PROP_UINT16("vendor-id", RISCVIOMMUStatePci, vendor_id,
171 PCI_VENDOR_ID_REDHAT),
172 DEFINE_PROP_UINT16("device-id", RISCVIOMMUStatePci, device_id,
173 PCI_DEVICE_ID_REDHAT_RISCV_IOMMU),
174 DEFINE_PROP_UINT8("revision", RISCVIOMMUStatePci, revision, 0x01),
175 };
176
riscv_iommu_pci_reset_hold(Object * obj,ResetType type)177 static void riscv_iommu_pci_reset_hold(Object *obj, ResetType type)
178 {
179 RISCVIOMMUStatePci *pci = RISCV_IOMMU_PCI(obj);
180 RISCVIOMMUState *iommu = &pci->iommu;
181
182 riscv_iommu_reset(iommu);
183
184 trace_riscv_iommu_pci_reset_hold(type);
185 }
186
riscv_iommu_pci_class_init(ObjectClass * klass,const void * data)187 static void riscv_iommu_pci_class_init(ObjectClass *klass, const void *data)
188 {
189 DeviceClass *dc = DEVICE_CLASS(klass);
190 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
191 ResettableClass *rc = RESETTABLE_CLASS(klass);
192
193 rc->phases.hold = riscv_iommu_pci_reset_hold;
194
195 k->realize = riscv_iommu_pci_realize;
196 k->exit = riscv_iommu_pci_exit;
197 k->class_id = RISCV_PCI_CLASS_SYSTEM_IOMMU;
198 dc->desc = "RISCV-IOMMU DMA Remapping device";
199 dc->vmsd = &riscv_iommu_vmstate;
200 dc->hotpluggable = false;
201 dc->user_creatable = true;
202 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
203 device_class_set_props(dc, riscv_iommu_pci_properties);
204 }
205
206 static const TypeInfo riscv_iommu_pci = {
207 .name = TYPE_RISCV_IOMMU_PCI,
208 .parent = TYPE_PCI_DEVICE,
209 .class_init = riscv_iommu_pci_class_init,
210 .instance_init = riscv_iommu_pci_init,
211 .instance_size = sizeof(RISCVIOMMUStatePci),
212 .interfaces = (const InterfaceInfo[]) {
213 { INTERFACE_PCIE_DEVICE },
214 { },
215 },
216 };
217
riscv_iommu_register_pci_types(void)218 static void riscv_iommu_register_pci_types(void)
219 {
220 type_register_static(&riscv_iommu_pci);
221 }
222
223 type_init(riscv_iommu_register_pci_types);
224