1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2H(P) SoC 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g057-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a09g057"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_extal_clk: audio-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by the board */ 20 clock-frequency = <0>; 21 }; 22 23 /* 24 * The default cluster table is based on the assumption that the PLLCA55 clock 25 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to 26 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be 27 * clocked to 1.8GHz as well). The table below should be overridden in the board 28 * DTS based on the PLLCA55 clock frequency. 29 */ 30 cluster0_opp: opp-table-0 { 31 compatible = "operating-points-v2"; 32 33 opp-1700000000 { 34 opp-hz = /bits/ 64 <1700000000>; 35 opp-microvolt = <900000>; 36 clock-latency-ns = <300000>; 37 }; 38 opp-850000000 { 39 opp-hz = /bits/ 64 <850000000>; 40 opp-microvolt = <800000>; 41 clock-latency-ns = <300000>; 42 }; 43 opp-425000000 { 44 opp-hz = /bits/ 64 <425000000>; 45 opp-microvolt = <800000>; 46 clock-latency-ns = <300000>; 47 }; 48 opp-212500000 { 49 opp-hz = /bits/ 64 <212500000>; 50 opp-microvolt = <800000>; 51 clock-latency-ns = <300000>; 52 opp-suspend; 53 }; 54 }; 55 56 cpus { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 cpu0: cpu@0 { 61 compatible = "arm,cortex-a55"; 62 reg = <0>; 63 device_type = "cpu"; 64 next-level-cache = <&L3_CA55>; 65 enable-method = "psci"; 66 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>; 67 operating-points-v2 = <&cluster0_opp>; 68 }; 69 70 cpu1: cpu@100 { 71 compatible = "arm,cortex-a55"; 72 reg = <0x100>; 73 device_type = "cpu"; 74 next-level-cache = <&L3_CA55>; 75 enable-method = "psci"; 76 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>; 77 operating-points-v2 = <&cluster0_opp>; 78 }; 79 80 cpu2: cpu@200 { 81 compatible = "arm,cortex-a55"; 82 reg = <0x200>; 83 device_type = "cpu"; 84 next-level-cache = <&L3_CA55>; 85 enable-method = "psci"; 86 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>; 87 operating-points-v2 = <&cluster0_opp>; 88 }; 89 90 cpu3: cpu@300 { 91 compatible = "arm,cortex-a55"; 92 reg = <0x300>; 93 device_type = "cpu"; 94 next-level-cache = <&L3_CA55>; 95 enable-method = "psci"; 96 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>; 97 operating-points-v2 = <&cluster0_opp>; 98 }; 99 100 L3_CA55: cache-controller-0 { 101 compatible = "cache"; 102 cache-unified; 103 cache-size = <0x100000>; 104 cache-level = <3>; 105 }; 106 }; 107 108 gpu_opp_table: opp-table-1 { 109 compatible = "operating-points-v2"; 110 111 opp-630000000 { 112 opp-hz = /bits/ 64 <630000000>; 113 opp-microvolt = <800000>; 114 }; 115 116 opp-315000000 { 117 opp-hz = /bits/ 64 <315000000>; 118 opp-microvolt = <800000>; 119 }; 120 121 opp-157500000 { 122 opp-hz = /bits/ 64 <157500000>; 123 opp-microvolt = <800000>; 124 }; 125 126 opp-78750000 { 127 opp-hz = /bits/ 64 <78750000>; 128 opp-microvolt = <800000>; 129 }; 130 131 opp-19687500 { 132 opp-hz = /bits/ 64 <19687500>; 133 opp-microvolt = <800000>; 134 }; 135 }; 136 137 psci { 138 compatible = "arm,psci-1.0", "arm,psci-0.2"; 139 method = "smc"; 140 }; 141 142 qextal_clk: qextal-clk { 143 compatible = "fixed-clock"; 144 #clock-cells = <0>; 145 /* This value must be overridden by the board */ 146 clock-frequency = <0>; 147 }; 148 149 rtxin_clk: rtxin-clk { 150 compatible = "fixed-clock"; 151 #clock-cells = <0>; 152 /* This value must be overridden by the board */ 153 clock-frequency = <0>; 154 }; 155 156 soc: soc { 157 compatible = "simple-bus"; 158 interrupt-parent = <&gic>; 159 #address-cells = <2>; 160 #size-cells = <2>; 161 ranges; 162 163 icu: interrupt-controller@10400000 { 164 compatible = "renesas,r9a09g057-icu"; 165 reg = <0 0x10400000 0 0x10000>; 166 #interrupt-cells = <2>; 167 #address-cells = <0>; 168 interrupt-controller; 169 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, 219 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 220 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 221 <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 222 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; 227 interrupt-names = "nmi", 228 "port_irq0", "port_irq1", "port_irq2", 229 "port_irq3", "port_irq4", "port_irq5", 230 "port_irq6", "port_irq7", "port_irq8", 231 "port_irq9", "port_irq10", "port_irq11", 232 "port_irq12", "port_irq13", "port_irq14", 233 "port_irq15", 234 "tint0", "tint1", "tint2", "tint3", 235 "tint4", "tint5", "tint6", "tint7", 236 "tint8", "tint9", "tint10", "tint11", 237 "tint12", "tint13", "tint14", "tint15", 238 "tint16", "tint17", "tint18", "tint19", 239 "tint20", "tint21", "tint22", "tint23", 240 "tint24", "tint25", "tint26", "tint27", 241 "tint28", "tint29", "tint30", "tint31", 242 "int-ca55-0", "int-ca55-1", 243 "int-ca55-2", "int-ca55-3", 244 "icu-error-ca55", 245 "gpt-u0-gtciada", "gpt-u0-gtciadb", 246 "gpt-u1-gtciada", "gpt-u1-gtciadb"; 247 clocks = <&cpg CPG_MOD 0x5>; 248 power-domains = <&cpg>; 249 resets = <&cpg 0x36>; 250 }; 251 252 pinctrl: pinctrl@10410000 { 253 compatible = "renesas,r9a09g057-pinctrl"; 254 reg = <0 0x10410000 0 0x10000>; 255 clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>; 256 gpio-controller; 257 #gpio-cells = <2>; 258 gpio-ranges = <&pinctrl 0 0 96>; 259 #interrupt-cells = <2>; 260 interrupt-controller; 261 interrupt-parent = <&icu>; 262 power-domains = <&cpg>; 263 resets = <&cpg 0xa5>, <&cpg 0xa6>; 264 }; 265 266 cpg: clock-controller@10420000 { 267 compatible = "renesas,r9a09g057-cpg"; 268 reg = <0 0x10420000 0 0x10000>; 269 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 270 clock-names = "audio_extal", "rtxin", "qextal"; 271 #clock-cells = <2>; 272 #reset-cells = <1>; 273 #power-domain-cells = <0>; 274 }; 275 276 sys: system-controller@10430000 { 277 compatible = "renesas,r9a09g057-sys"; 278 reg = <0 0x10430000 0 0x10000>; 279 clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>; 280 resets = <&cpg 0x30>; 281 }; 282 283 ostm0: timer@11800000 { 284 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 285 reg = <0x0 0x11800000 0x0 0x1000>; 286 interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>; 287 clocks = <&cpg CPG_MOD 0x43>; 288 resets = <&cpg 0x6d>; 289 power-domains = <&cpg>; 290 status = "disabled"; 291 }; 292 293 ostm1: timer@11801000 { 294 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 295 reg = <0x0 0x11801000 0x0 0x1000>; 296 interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>; 297 clocks = <&cpg CPG_MOD 0x44>; 298 resets = <&cpg 0x6e>; 299 power-domains = <&cpg>; 300 status = "disabled"; 301 }; 302 303 ostm2: timer@14000000 { 304 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 305 reg = <0x0 0x14000000 0x0 0x1000>; 306 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; 307 clocks = <&cpg CPG_MOD 0x45>; 308 resets = <&cpg 0x6f>; 309 power-domains = <&cpg>; 310 status = "disabled"; 311 }; 312 313 ostm3: timer@14001000 { 314 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 315 reg = <0x0 0x14001000 0x0 0x1000>; 316 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>; 317 clocks = <&cpg CPG_MOD 0x46>; 318 resets = <&cpg 0x70>; 319 power-domains = <&cpg>; 320 status = "disabled"; 321 }; 322 323 ostm4: timer@12c00000 { 324 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 325 reg = <0x0 0x12c00000 0x0 0x1000>; 326 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 327 clocks = <&cpg CPG_MOD 0x47>; 328 resets = <&cpg 0x71>; 329 power-domains = <&cpg>; 330 status = "disabled"; 331 }; 332 333 ostm5: timer@12c01000 { 334 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 335 reg = <0x0 0x12c01000 0x0 0x1000>; 336 interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 337 clocks = <&cpg CPG_MOD 0x48>; 338 resets = <&cpg 0x72>; 339 power-domains = <&cpg>; 340 status = "disabled"; 341 }; 342 343 ostm6: timer@12c02000 { 344 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 345 reg = <0x0 0x12c02000 0x0 0x1000>; 346 interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; 347 clocks = <&cpg CPG_MOD 0x49>; 348 resets = <&cpg 0x73>; 349 power-domains = <&cpg>; 350 status = "disabled"; 351 }; 352 353 ostm7: timer@12c03000 { 354 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 355 reg = <0x0 0x12c03000 0x0 0x1000>; 356 interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; 357 clocks = <&cpg CPG_MOD 0x4a>; 358 resets = <&cpg 0x74>; 359 power-domains = <&cpg>; 360 status = "disabled"; 361 }; 362 363 wdt0: watchdog@11c00400 { 364 compatible = "renesas,r9a09g057-wdt"; 365 reg = <0 0x11c00400 0 0x400>; 366 clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>; 367 clock-names = "pclk", "oscclk"; 368 resets = <&cpg 0x75>; 369 power-domains = <&cpg>; 370 status = "disabled"; 371 }; 372 373 wdt1: watchdog@14400000 { 374 compatible = "renesas,r9a09g057-wdt"; 375 reg = <0 0x14400000 0 0x400>; 376 clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; 377 clock-names = "pclk", "oscclk"; 378 resets = <&cpg 0x76>; 379 power-domains = <&cpg>; 380 status = "disabled"; 381 }; 382 383 wdt2: watchdog@13000000 { 384 compatible = "renesas,r9a09g057-wdt"; 385 reg = <0 0x13000000 0 0x400>; 386 clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; 387 clock-names = "pclk", "oscclk"; 388 resets = <&cpg 0x77>; 389 power-domains = <&cpg>; 390 status = "disabled"; 391 }; 392 393 wdt3: watchdog@13000400 { 394 compatible = "renesas,r9a09g057-wdt"; 395 reg = <0 0x13000400 0 0x400>; 396 clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; 397 clock-names = "pclk", "oscclk"; 398 resets = <&cpg 0x78>; 399 power-domains = <&cpg>; 400 status = "disabled"; 401 }; 402 403 scif: serial@11c01400 { 404 compatible = "renesas,scif-r9a09g057"; 405 reg = <0 0x11c01400 0 0x400>; 406 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 414 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 415 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 416 "tei", "tei-dri", "rxi-edge", "txi-edge"; 417 clocks = <&cpg CPG_MOD 0x8f>; 418 clock-names = "fck"; 419 power-domains = <&cpg>; 420 resets = <&cpg 0x95>; 421 status = "disabled"; 422 }; 423 424 i2c0: i2c@14400400 { 425 compatible = "renesas,riic-r9a09g057"; 426 reg = <0 0x14400400 0 0x400>; 427 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 429 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 430 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 435 interrupt-names = "tei", "ri", "ti", "spi", "sti", 436 "naki", "ali", "tmoi"; 437 clocks = <&cpg CPG_MOD 0x94>; 438 resets = <&cpg 0x98>; 439 power-domains = <&cpg>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 status = "disabled"; 443 }; 444 445 i2c1: i2c@14400800 { 446 compatible = "renesas,riic-r9a09g057"; 447 reg = <0 0x14400800 0 0x400>; 448 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 450 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 451 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 456 interrupt-names = "tei", "ri", "ti", "spi", "sti", 457 "naki", "ali", "tmoi"; 458 clocks = <&cpg CPG_MOD 0x95>; 459 resets = <&cpg 0x99>; 460 power-domains = <&cpg>; 461 #address-cells = <1>; 462 #size-cells = <0>; 463 status = "disabled"; 464 }; 465 466 i2c2: i2c@14400c00 { 467 compatible = "renesas,riic-r9a09g057"; 468 reg = <0 0x14400c00 0 0x400>; 469 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 471 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 472 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 477 interrupt-names = "tei", "ri", "ti", "spi", "sti", 478 "naki", "ali", "tmoi"; 479 clocks = <&cpg CPG_MOD 0x96>; 480 resets = <&cpg 0x9a>; 481 power-domains = <&cpg>; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 status = "disabled"; 485 }; 486 487 i2c3: i2c@14401000 { 488 compatible = "renesas,riic-r9a09g057"; 489 reg = <0 0x14401000 0 0x400>; 490 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 492 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 493 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 498 interrupt-names = "tei", "ri", "ti", "spi", "sti", 499 "naki", "ali", "tmoi"; 500 clocks = <&cpg CPG_MOD 0x97>; 501 resets = <&cpg 0x9b>; 502 power-domains = <&cpg>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 status = "disabled"; 506 }; 507 508 i2c4: i2c@14401400 { 509 compatible = "renesas,riic-r9a09g057"; 510 reg = <0 0x14401400 0 0x400>; 511 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 513 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 514 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 519 interrupt-names = "tei", "ri", "ti", "spi", "sti", 520 "naki", "ali", "tmoi"; 521 clocks = <&cpg CPG_MOD 0x98>; 522 resets = <&cpg 0x9c>; 523 power-domains = <&cpg>; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 status = "disabled"; 527 }; 528 529 i2c5: i2c@14401800 { 530 compatible = "renesas,riic-r9a09g057"; 531 reg = <0 0x14401800 0 0x400>; 532 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 534 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 535 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 540 interrupt-names = "tei", "ri", "ti", "spi", "sti", 541 "naki", "ali", "tmoi"; 542 clocks = <&cpg CPG_MOD 0x99>; 543 resets = <&cpg 0x9d>; 544 power-domains = <&cpg>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 status = "disabled"; 548 }; 549 550 i2c6: i2c@14401c00 { 551 compatible = "renesas,riic-r9a09g057"; 552 reg = <0 0x14401c00 0 0x400>; 553 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 555 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 556 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 561 interrupt-names = "tei", "ri", "ti", "spi", "sti", 562 "naki", "ali", "tmoi"; 563 clocks = <&cpg CPG_MOD 0x9a>; 564 resets = <&cpg 0x9e>; 565 power-domains = <&cpg>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 status = "disabled"; 569 }; 570 571 i2c7: i2c@14402000 { 572 compatible = "renesas,riic-r9a09g057"; 573 reg = <0 0x14402000 0 0x400>; 574 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 576 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 577 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 582 interrupt-names = "tei", "ri", "ti", "spi", "sti", 583 "naki", "ali", "tmoi"; 584 clocks = <&cpg CPG_MOD 0x9b>; 585 resets = <&cpg 0x9f>; 586 power-domains = <&cpg>; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 status = "disabled"; 590 }; 591 592 i2c8: i2c@11c01000 { 593 compatible = "renesas,riic-r9a09g057"; 594 reg = <0 0x11c01000 0 0x400>; 595 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 597 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 598 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 603 interrupt-names = "tei", "ri", "ti", "spi", "sti", 604 "naki", "ali", "tmoi"; 605 clocks = <&cpg CPG_MOD 0x93>; 606 resets = <&cpg 0xa0>; 607 power-domains = <&cpg>; 608 #address-cells = <1>; 609 #size-cells = <0>; 610 status = "disabled"; 611 }; 612 613 gpu: gpu@14850000 { 614 compatible = "renesas,r9a09g057-mali", 615 "arm,mali-bifrost"; 616 reg = <0x0 0x14850000 0x0 0x10000>; 617 interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>; 621 interrupt-names = "job", "mmu", "gpu", "event"; 622 clocks = <&cpg CPG_MOD 0xf0>, 623 <&cpg CPG_MOD 0xf1>, 624 <&cpg CPG_MOD 0xf2>; 625 clock-names = "gpu", "bus", "bus_ace"; 626 power-domains = <&cpg>; 627 resets = <&cpg 0xdd>, 628 <&cpg 0xde>, 629 <&cpg 0xdf>; 630 reset-names = "rst", "axi_rst", "ace_rst"; 631 operating-points-v2 = <&gpu_opp_table>; 632 status = "disabled"; 633 }; 634 635 gic: interrupt-controller@14900000 { 636 compatible = "arm,gic-v3"; 637 reg = <0x0 0x14900000 0 0x20000>, 638 <0x0 0x14940000 0 0x80000>; 639 #interrupt-cells = <3>; 640 #address-cells = <0>; 641 interrupt-controller; 642 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 643 }; 644 645 sdhi0: mmc@15c00000 { 646 compatible = "renesas,sdhi-r9a09g057"; 647 reg = <0x0 0x15c00000 0 0x10000>; 648 interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, 651 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; 652 clock-names = "core", "clkh", "cd", "aclk"; 653 resets = <&cpg 0xa7>; 654 power-domains = <&cpg>; 655 status = "disabled"; 656 }; 657 658 sdhi1: mmc@15c10000 { 659 compatible = "renesas,sdhi-r9a09g057"; 660 reg = <0x0 0x15c10000 0 0x10000>; 661 interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, 664 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; 665 clock-names = "core", "clkh", "cd", "aclk"; 666 resets = <&cpg 0xa8>; 667 power-domains = <&cpg>; 668 status = "disabled"; 669 }; 670 671 sdhi2: mmc@15c20000 { 672 compatible = "renesas,sdhi-r9a09g057"; 673 reg = <0x0 0x15c20000 0 0x10000>; 674 interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, 677 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; 678 clock-names = "core", "clkh", "cd", "aclk"; 679 resets = <&cpg 0xa9>; 680 power-domains = <&cpg>; 681 status = "disabled"; 682 }; 683 }; 684 685 timer { 686 compatible = "arm,armv8-timer"; 687 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 688 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 689 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 690 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 691 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 692 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 693 }; 694}; 695