1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G3E SoC 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g047-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a09g047"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_extal_clk: audio-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by the board */ 20 clock-frequency = <0>; 21 }; 22 23 /* 24 * The default cluster table is based on the assumption that the PLLCA55 clock 25 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to 26 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be 27 * clocked to 1.8GHz as well). The table below should be overridden in the board 28 * DTS based on the PLLCA55 clock frequency. 29 */ 30 cluster0_opp: opp-table-0 { 31 compatible = "operating-points-v2"; 32 33 opp-1700000000 { 34 opp-hz = /bits/ 64 <1700000000>; 35 opp-microvolt = <900000>; 36 clock-latency-ns = <300000>; 37 }; 38 opp-850000000 { 39 opp-hz = /bits/ 64 <850000000>; 40 opp-microvolt = <800000>; 41 clock-latency-ns = <300000>; 42 }; 43 opp-425000000 { 44 opp-hz = /bits/ 64 <425000000>; 45 opp-microvolt = <800000>; 46 clock-latency-ns = <300000>; 47 }; 48 opp-212500000 { 49 opp-hz = /bits/ 64 <212500000>; 50 opp-microvolt = <800000>; 51 clock-latency-ns = <300000>; 52 opp-suspend; 53 }; 54 }; 55 56 cpus { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 cpu0: cpu@0 { 61 compatible = "arm,cortex-a55"; 62 reg = <0>; 63 device_type = "cpu"; 64 next-level-cache = <&L3_CA55>; 65 enable-method = "psci"; 66 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>; 67 operating-points-v2 = <&cluster0_opp>; 68 }; 69 70 cpu1: cpu@100 { 71 compatible = "arm,cortex-a55"; 72 reg = <0x100>; 73 device_type = "cpu"; 74 next-level-cache = <&L3_CA55>; 75 enable-method = "psci"; 76 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>; 77 operating-points-v2 = <&cluster0_opp>; 78 }; 79 80 cpu2: cpu@200 { 81 compatible = "arm,cortex-a55"; 82 reg = <0x200>; 83 device_type = "cpu"; 84 next-level-cache = <&L3_CA55>; 85 enable-method = "psci"; 86 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>; 87 operating-points-v2 = <&cluster0_opp>; 88 }; 89 90 cpu3: cpu@300 { 91 compatible = "arm,cortex-a55"; 92 reg = <0x300>; 93 device_type = "cpu"; 94 next-level-cache = <&L3_CA55>; 95 enable-method = "psci"; 96 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>; 97 operating-points-v2 = <&cluster0_opp>; 98 }; 99 100 L3_CA55: cache-controller-0 { 101 compatible = "cache"; 102 cache-unified; 103 cache-size = <0x100000>; 104 cache-level = <3>; 105 }; 106 }; 107 108 psci { 109 compatible = "arm,psci-1.0", "arm,psci-0.2"; 110 method = "smc"; 111 }; 112 113 qextal_clk: qextal-clk { 114 compatible = "fixed-clock"; 115 #clock-cells = <0>; 116 /* This value must be overridden by the board */ 117 clock-frequency = <0>; 118 }; 119 120 rtxin_clk: rtxin-clk { 121 compatible = "fixed-clock"; 122 #clock-cells = <0>; 123 /* This value must be overridden by the board */ 124 clock-frequency = <0>; 125 }; 126 127 soc: soc { 128 compatible = "simple-bus"; 129 interrupt-parent = <&gic>; 130 #address-cells = <2>; 131 #size-cells = <2>; 132 ranges; 133 134 pinctrl: pinctrl@10410000 { 135 compatible = "renesas,r9a09g047-pinctrl"; 136 reg = <0 0x10410000 0 0x10000>; 137 clocks = <&cpg CPG_CORE R9A09G047_IOTOP_0_SHCLK>; 138 gpio-controller; 139 #gpio-cells = <2>; 140 gpio-ranges = <&pinctrl 0 0 232>; 141 #interrupt-cells = <2>; 142 interrupt-controller; 143 power-domains = <&cpg>; 144 resets = <&cpg 0xa5>, <&cpg 0xa6>; 145 }; 146 147 cpg: clock-controller@10420000 { 148 compatible = "renesas,r9a09g047-cpg"; 149 reg = <0 0x10420000 0 0x10000>; 150 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 151 clock-names = "audio_extal", "rtxin", "qextal"; 152 #clock-cells = <2>; 153 #reset-cells = <1>; 154 #power-domain-cells = <0>; 155 }; 156 157 sys: system-controller@10430000 { 158 compatible = "renesas,r9a09g047-sys"; 159 reg = <0 0x10430000 0 0x10000>; 160 clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>; 161 resets = <&cpg 0x30>; 162 }; 163 164 scif0: serial@11c01400 { 165 compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057"; 166 reg = <0 0x11c01400 0 0x400>; 167 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 175 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 176 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 177 "tei", "tei-dri", "rxi-edge", "txi-edge"; 178 clocks = <&cpg CPG_MOD 0x8f>; 179 clock-names = "fck"; 180 power-domains = <&cpg>; 181 resets = <&cpg 0x95>; 182 status = "disabled"; 183 }; 184 185 wdt1: watchdog@14400000 { 186 compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; 187 reg = <0 0x14400000 0 0x400>; 188 clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; 189 clock-names = "pclk", "oscclk"; 190 resets = <&cpg 0x76>; 191 power-domains = <&cpg>; 192 status = "disabled"; 193 }; 194 195 wdt2: watchdog@13000000 { 196 compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; 197 reg = <0 0x13000000 0 0x400>; 198 clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; 199 clock-names = "pclk", "oscclk"; 200 resets = <&cpg 0x77>; 201 power-domains = <&cpg>; 202 status = "disabled"; 203 }; 204 205 wdt3: watchdog@13000400 { 206 compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; 207 reg = <0 0x13000400 0 0x400>; 208 clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; 209 clock-names = "pclk", "oscclk"; 210 resets = <&cpg 0x78>; 211 power-domains = <&cpg>; 212 status = "disabled"; 213 }; 214 215 i2c0: i2c@14400400 { 216 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 217 reg = <0 0x14400400 0 0x400>; 218 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 220 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 221 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 226 interrupt-names = "tei", "ri", "ti", "spi", "sti", 227 "naki", "ali", "tmoi"; 228 clocks = <&cpg CPG_MOD 0x94>; 229 resets = <&cpg 0x98>; 230 power-domains = <&cpg>; 231 #address-cells = <1>; 232 #size-cells = <0>; 233 status = "disabled"; 234 }; 235 236 i2c1: i2c@14400800 { 237 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 238 reg = <0 0x14400800 0 0x400>; 239 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 241 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 242 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 247 interrupt-names = "tei", "ri", "ti", "spi", "sti", 248 "naki", "ali", "tmoi"; 249 clocks = <&cpg CPG_MOD 0x95>; 250 resets = <&cpg 0x99>; 251 power-domains = <&cpg>; 252 #address-cells = <1>; 253 #size-cells = <0>; 254 status = "disabled"; 255 }; 256 257 i2c2: i2c@14400c00 { 258 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 259 reg = <0 0x14400c00 0 0x400>; 260 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 262 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 263 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 268 interrupt-names = "tei", "ri", "ti", "spi", "sti", 269 "naki", "ali", "tmoi"; 270 clocks = <&cpg CPG_MOD 0x96>; 271 resets = <&cpg 0x9a>; 272 power-domains = <&cpg>; 273 #address-cells = <1>; 274 #size-cells = <0>; 275 status = "disabled"; 276 }; 277 278 i2c3: i2c@14401000 { 279 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 280 reg = <0 0x14401000 0 0x400>; 281 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 283 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 284 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 289 interrupt-names = "tei", "ri", "ti", "spi", "sti", 290 "naki", "ali", "tmoi"; 291 clocks = <&cpg CPG_MOD 0x97>; 292 resets = <&cpg 0x9b>; 293 power-domains = <&cpg>; 294 #address-cells = <1>; 295 #size-cells = <0>; 296 status = "disabled"; 297 }; 298 299 i2c4: i2c@14401400 { 300 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 301 reg = <0 0x14401400 0 0x400>; 302 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 304 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 305 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 310 interrupt-names = "tei", "ri", "ti", "spi", "sti", 311 "naki", "ali", "tmoi"; 312 clocks = <&cpg CPG_MOD 0x98>; 313 resets = <&cpg 0x9c>; 314 power-domains = <&cpg>; 315 #address-cells = <1>; 316 #size-cells = <0>; 317 status = "disabled"; 318 }; 319 320 i2c5: i2c@14401800 { 321 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 322 reg = <0 0x14401800 0 0x400>; 323 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 325 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 326 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 331 interrupt-names = "tei", "ri", "ti", "spi", "sti", 332 "naki", "ali", "tmoi"; 333 clocks = <&cpg CPG_MOD 0x99>; 334 resets = <&cpg 0x9d>; 335 power-domains = <&cpg>; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 status = "disabled"; 339 }; 340 341 i2c6: i2c@14401c00 { 342 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 343 reg = <0 0x14401c00 0 0x400>; 344 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 346 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 347 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 352 interrupt-names = "tei", "ri", "ti", "spi", "sti", 353 "naki", "ali", "tmoi"; 354 clocks = <&cpg CPG_MOD 0x9a>; 355 resets = <&cpg 0x9e>; 356 power-domains = <&cpg>; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 status = "disabled"; 360 }; 361 362 i2c7: i2c@14402000 { 363 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 364 reg = <0 0x14402000 0 0x400>; 365 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 367 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 368 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 373 interrupt-names = "tei", "ri", "ti", "spi", "sti", 374 "naki", "ali", "tmoi"; 375 clocks = <&cpg CPG_MOD 0x9b>; 376 resets = <&cpg 0x9f>; 377 power-domains = <&cpg>; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 status = "disabled"; 381 }; 382 383 i2c8: i2c@11c01000 { 384 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 385 reg = <0 0x11c01000 0 0x400>; 386 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 388 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 389 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 394 interrupt-names = "tei", "ri", "ti", "spi", "sti", 395 "naki", "ali", "tmoi"; 396 clocks = <&cpg CPG_MOD 0x93>; 397 resets = <&cpg 0xa0>; 398 power-domains = <&cpg>; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 status = "disabled"; 402 }; 403 404 gic: interrupt-controller@14900000 { 405 compatible = "arm,gic-v3"; 406 reg = <0x0 0x14900000 0 0x20000>, 407 <0x0 0x14940000 0 0x80000>; 408 #interrupt-cells = <3>; 409 #address-cells = <0>; 410 interrupt-controller; 411 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 412 }; 413 }; 414 415 timer { 416 compatible = "arm,armv8-timer"; 417 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 418 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 419 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 420 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 421 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 422 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 423 }; 424}; 425