1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774a1 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774a1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774a1-sysc.h> 12 13/ { 14 compatible = "renesas,r8a774a1"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* 19 * The external audio clocks are configured as 0 Hz fixed frequency 20 * clocks by default. 21 * Boards that provide audio clocks should override them. 22 */ 23 audio_clk_a: audio_clk_a { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <0>; 27 }; 28 29 audio_clk_b: audio_clk_b { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <0>; 33 }; 34 35 audio_clk_c: audio_clk_c { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <0>; 39 }; 40 41 /* External CAN clock - to be overridden by boards that provide it */ 42 can_clk: can { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <0>; 46 }; 47 48 cluster0_opp: opp-table-0 { 49 compatible = "operating-points-v2"; 50 opp-shared; 51 52 opp-500000000 { 53 opp-hz = /bits/ 64 <500000000>; 54 opp-microvolt = <820000>; 55 clock-latency-ns = <300000>; 56 }; 57 opp-1000000000 { 58 opp-hz = /bits/ 64 <1000000000>; 59 opp-microvolt = <820000>; 60 clock-latency-ns = <300000>; 61 }; 62 opp-1500000000 { 63 opp-hz = /bits/ 64 <1500000000>; 64 opp-microvolt = <820000>; 65 clock-latency-ns = <300000>; 66 opp-suspend; 67 }; 68 }; 69 70 cluster1_opp: opp-table-1 { 71 compatible = "operating-points-v2"; 72 opp-shared; 73 74 opp-800000000 { 75 opp-hz = /bits/ 64 <800000000>; 76 opp-microvolt = <820000>; 77 clock-latency-ns = <300000>; 78 }; 79 opp-1000000000 { 80 opp-hz = /bits/ 64 <1000000000>; 81 opp-microvolt = <820000>; 82 clock-latency-ns = <300000>; 83 }; 84 opp-1200000000 { 85 opp-hz = /bits/ 64 <1200000000>; 86 opp-microvolt = <820000>; 87 clock-latency-ns = <300000>; 88 }; 89 }; 90 91 cpus { 92 #address-cells = <1>; 93 #size-cells = <0>; 94 95 cpu-map { 96 cluster0 { 97 core0 { 98 cpu = <&a57_0>; 99 }; 100 core1 { 101 cpu = <&a57_1>; 102 }; 103 }; 104 105 cluster1 { 106 core0 { 107 cpu = <&a53_0>; 108 }; 109 core1 { 110 cpu = <&a53_1>; 111 }; 112 core2 { 113 cpu = <&a53_2>; 114 }; 115 core3 { 116 cpu = <&a53_3>; 117 }; 118 }; 119 }; 120 121 a57_0: cpu@0 { 122 compatible = "arm,cortex-a57"; 123 reg = <0x0>; 124 device_type = "cpu"; 125 power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; 126 next-level-cache = <&L2_CA57>; 127 enable-method = "psci"; 128 dynamic-power-coefficient = <854>; 129 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; 130 operating-points-v2 = <&cluster0_opp>; 131 capacity-dmips-mhz = <1024>; 132 #cooling-cells = <2>; 133 }; 134 135 a57_1: cpu@1 { 136 compatible = "arm,cortex-a57"; 137 reg = <0x1>; 138 device_type = "cpu"; 139 power-domains = <&sysc R8A774A1_PD_CA57_CPU1>; 140 next-level-cache = <&L2_CA57>; 141 enable-method = "psci"; 142 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; 143 operating-points-v2 = <&cluster0_opp>; 144 capacity-dmips-mhz = <1024>; 145 #cooling-cells = <2>; 146 }; 147 148 a53_0: cpu@100 { 149 compatible = "arm,cortex-a53"; 150 reg = <0x100>; 151 device_type = "cpu"; 152 power-domains = <&sysc R8A774A1_PD_CA53_CPU0>; 153 next-level-cache = <&L2_CA53>; 154 enable-method = "psci"; 155 #cooling-cells = <2>; 156 dynamic-power-coefficient = <277>; 157 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 158 operating-points-v2 = <&cluster1_opp>; 159 capacity-dmips-mhz = <560>; 160 }; 161 162 a53_1: cpu@101 { 163 compatible = "arm,cortex-a53"; 164 reg = <0x101>; 165 device_type = "cpu"; 166 power-domains = <&sysc R8A774A1_PD_CA53_CPU1>; 167 next-level-cache = <&L2_CA53>; 168 enable-method = "psci"; 169 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 170 operating-points-v2 = <&cluster1_opp>; 171 capacity-dmips-mhz = <560>; 172 }; 173 174 a53_2: cpu@102 { 175 compatible = "arm,cortex-a53"; 176 reg = <0x102>; 177 device_type = "cpu"; 178 power-domains = <&sysc R8A774A1_PD_CA53_CPU2>; 179 next-level-cache = <&L2_CA53>; 180 enable-method = "psci"; 181 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 182 operating-points-v2 = <&cluster1_opp>; 183 capacity-dmips-mhz = <560>; 184 }; 185 186 a53_3: cpu@103 { 187 compatible = "arm,cortex-a53"; 188 reg = <0x103>; 189 device_type = "cpu"; 190 power-domains = <&sysc R8A774A1_PD_CA53_CPU3>; 191 next-level-cache = <&L2_CA53>; 192 enable-method = "psci"; 193 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 194 operating-points-v2 = <&cluster1_opp>; 195 capacity-dmips-mhz = <560>; 196 }; 197 198 L2_CA57: cache-controller-0 { 199 compatible = "cache"; 200 power-domains = <&sysc R8A774A1_PD_CA57_SCU>; 201 cache-unified; 202 cache-level = <2>; 203 }; 204 205 L2_CA53: cache-controller-1 { 206 compatible = "cache"; 207 power-domains = <&sysc R8A774A1_PD_CA53_SCU>; 208 cache-unified; 209 cache-level = <2>; 210 }; 211 }; 212 213 extal_clk: extal { 214 compatible = "fixed-clock"; 215 #clock-cells = <0>; 216 /* This value must be overridden by the board */ 217 clock-frequency = <0>; 218 bootph-all; 219 }; 220 221 extalr_clk: extalr { 222 compatible = "fixed-clock"; 223 #clock-cells = <0>; 224 /* This value must be overridden by the board */ 225 clock-frequency = <0>; 226 bootph-all; 227 }; 228 229 /* External PCIe clock - can be overridden by the board */ 230 pcie_bus_clk: pcie_bus { 231 compatible = "fixed-clock"; 232 #clock-cells = <0>; 233 clock-frequency = <0>; 234 }; 235 236 pmu_a53 { 237 compatible = "arm,cortex-a53-pmu"; 238 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 239 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 240 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 241 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 242 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 243 }; 244 245 pmu_a57 { 246 compatible = "arm,cortex-a57-pmu"; 247 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 248 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 249 interrupt-affinity = <&a57_0>, <&a57_1>; 250 }; 251 252 psci { 253 compatible = "arm,psci-1.0", "arm,psci-0.2"; 254 method = "smc"; 255 }; 256 257 /* External SCIF clock - to be overridden by boards that provide it */ 258 scif_clk: scif { 259 compatible = "fixed-clock"; 260 #clock-cells = <0>; 261 clock-frequency = <0>; 262 }; 263 264 soc { 265 compatible = "simple-bus"; 266 interrupt-parent = <&gic>; 267 bootph-all; 268 269 #address-cells = <2>; 270 #size-cells = <2>; 271 ranges; 272 273 rwdt: watchdog@e6020000 { 274 compatible = "renesas,r8a774a1-wdt", 275 "renesas,rcar-gen3-wdt"; 276 reg = <0 0xe6020000 0 0x0c>; 277 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&cpg CPG_MOD 402>; 279 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 280 resets = <&cpg 402>; 281 status = "disabled"; 282 }; 283 284 gpio0: gpio@e6050000 { 285 compatible = "renesas,gpio-r8a774a1", 286 "renesas,rcar-gen3-gpio"; 287 reg = <0 0xe6050000 0 0x50>; 288 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 289 #gpio-cells = <2>; 290 gpio-controller; 291 gpio-ranges = <&pfc 0 0 16>; 292 #interrupt-cells = <2>; 293 interrupt-controller; 294 clocks = <&cpg CPG_MOD 912>; 295 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 296 resets = <&cpg 912>; 297 }; 298 299 gpio1: gpio@e6051000 { 300 compatible = "renesas,gpio-r8a774a1", 301 "renesas,rcar-gen3-gpio"; 302 reg = <0 0xe6051000 0 0x50>; 303 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 304 #gpio-cells = <2>; 305 gpio-controller; 306 gpio-ranges = <&pfc 0 32 29>; 307 #interrupt-cells = <2>; 308 interrupt-controller; 309 clocks = <&cpg CPG_MOD 911>; 310 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 311 resets = <&cpg 911>; 312 }; 313 314 gpio2: gpio@e6052000 { 315 compatible = "renesas,gpio-r8a774a1", 316 "renesas,rcar-gen3-gpio"; 317 reg = <0 0xe6052000 0 0x50>; 318 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 319 #gpio-cells = <2>; 320 gpio-controller; 321 gpio-ranges = <&pfc 0 64 15>; 322 #interrupt-cells = <2>; 323 interrupt-controller; 324 clocks = <&cpg CPG_MOD 910>; 325 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 326 resets = <&cpg 910>; 327 }; 328 329 gpio3: gpio@e6053000 { 330 compatible = "renesas,gpio-r8a774a1", 331 "renesas,rcar-gen3-gpio"; 332 reg = <0 0xe6053000 0 0x50>; 333 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 334 #gpio-cells = <2>; 335 gpio-controller; 336 gpio-ranges = <&pfc 0 96 16>; 337 #interrupt-cells = <2>; 338 interrupt-controller; 339 clocks = <&cpg CPG_MOD 909>; 340 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 341 resets = <&cpg 909>; 342 }; 343 344 gpio4: gpio@e6054000 { 345 compatible = "renesas,gpio-r8a774a1", 346 "renesas,rcar-gen3-gpio"; 347 reg = <0 0xe6054000 0 0x50>; 348 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 349 #gpio-cells = <2>; 350 gpio-controller; 351 gpio-ranges = <&pfc 0 128 18>; 352 #interrupt-cells = <2>; 353 interrupt-controller; 354 clocks = <&cpg CPG_MOD 908>; 355 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 356 resets = <&cpg 908>; 357 }; 358 359 gpio5: gpio@e6055000 { 360 compatible = "renesas,gpio-r8a774a1", 361 "renesas,rcar-gen3-gpio"; 362 reg = <0 0xe6055000 0 0x50>; 363 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 364 #gpio-cells = <2>; 365 gpio-controller; 366 gpio-ranges = <&pfc 0 160 26>; 367 #interrupt-cells = <2>; 368 interrupt-controller; 369 clocks = <&cpg CPG_MOD 907>; 370 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 371 resets = <&cpg 907>; 372 }; 373 374 gpio6: gpio@e6055400 { 375 compatible = "renesas,gpio-r8a774a1", 376 "renesas,rcar-gen3-gpio"; 377 reg = <0 0xe6055400 0 0x50>; 378 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 379 #gpio-cells = <2>; 380 gpio-controller; 381 gpio-ranges = <&pfc 0 192 32>; 382 #interrupt-cells = <2>; 383 interrupt-controller; 384 clocks = <&cpg CPG_MOD 906>; 385 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 386 resets = <&cpg 906>; 387 }; 388 389 gpio7: gpio@e6055800 { 390 compatible = "renesas,gpio-r8a774a1", 391 "renesas,rcar-gen3-gpio"; 392 reg = <0 0xe6055800 0 0x50>; 393 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 394 #gpio-cells = <2>; 395 gpio-controller; 396 gpio-ranges = <&pfc 0 224 4>; 397 #interrupt-cells = <2>; 398 interrupt-controller; 399 clocks = <&cpg CPG_MOD 905>; 400 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 401 resets = <&cpg 905>; 402 }; 403 404 pfc: pinctrl@e6060000 { 405 compatible = "renesas,pfc-r8a774a1"; 406 reg = <0 0xe6060000 0 0x50c>; 407 bootph-all; 408 }; 409 410 cmt0: timer@e60f0000 { 411 compatible = "renesas,r8a774a1-cmt0", 412 "renesas,rcar-gen3-cmt0"; 413 reg = <0 0xe60f0000 0 0x1004>; 414 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&cpg CPG_MOD 303>; 417 clock-names = "fck"; 418 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 419 resets = <&cpg 303>; 420 status = "disabled"; 421 }; 422 423 cmt1: timer@e6130000 { 424 compatible = "renesas,r8a774a1-cmt1", 425 "renesas,rcar-gen3-cmt1"; 426 reg = <0 0xe6130000 0 0x1004>; 427 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&cpg CPG_MOD 302>; 436 clock-names = "fck"; 437 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 438 resets = <&cpg 302>; 439 status = "disabled"; 440 }; 441 442 cmt2: timer@e6140000 { 443 compatible = "renesas,r8a774a1-cmt1", 444 "renesas,rcar-gen3-cmt1"; 445 reg = <0 0xe6140000 0 0x1004>; 446 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&cpg CPG_MOD 301>; 455 clock-names = "fck"; 456 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 457 resets = <&cpg 301>; 458 status = "disabled"; 459 }; 460 461 cmt3: timer@e6148000 { 462 compatible = "renesas,r8a774a1-cmt1", 463 "renesas,rcar-gen3-cmt1"; 464 reg = <0 0xe6148000 0 0x1004>; 465 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&cpg CPG_MOD 300>; 474 clock-names = "fck"; 475 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 476 resets = <&cpg 300>; 477 status = "disabled"; 478 }; 479 480 cpg: clock-controller@e6150000 { 481 compatible = "renesas,r8a774a1-cpg-mssr"; 482 reg = <0 0xe6150000 0 0x0bb0>; 483 clocks = <&extal_clk>, <&extalr_clk>; 484 clock-names = "extal", "extalr"; 485 #clock-cells = <2>; 486 #power-domain-cells = <0>; 487 #reset-cells = <1>; 488 bootph-all; 489 }; 490 491 rst: reset-controller@e6160000 { 492 compatible = "renesas,r8a774a1-rst"; 493 reg = <0 0xe6160000 0 0x018c>; 494 bootph-all; 495 }; 496 497 sysc: system-controller@e6180000 { 498 compatible = "renesas,r8a774a1-sysc"; 499 reg = <0 0xe6180000 0 0x0400>; 500 #power-domain-cells = <1>; 501 }; 502 503 tsc: thermal@e6198000 { 504 compatible = "renesas,r8a774a1-thermal"; 505 reg = <0 0xe6198000 0 0x100>, 506 <0 0xe61a0000 0 0x100>, 507 <0 0xe61a8000 0 0x100>; 508 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&cpg CPG_MOD 522>; 512 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 513 resets = <&cpg 522>; 514 #thermal-sensor-cells = <1>; 515 }; 516 517 intc_ex: interrupt-controller@e61c0000 { 518 compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc"; 519 #interrupt-cells = <2>; 520 interrupt-controller; 521 reg = <0 0xe61c0000 0 0x200>; 522 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&cpg CPG_MOD 407>; 529 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 530 resets = <&cpg 407>; 531 }; 532 533 tmu0: timer@e61e0000 { 534 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 535 reg = <0 0xe61e0000 0 0x30>; 536 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 539 interrupt-names = "tuni0", "tuni1", "tuni2"; 540 clocks = <&cpg CPG_MOD 125>; 541 clock-names = "fck"; 542 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 543 resets = <&cpg 125>; 544 status = "disabled"; 545 }; 546 547 tmu1: timer@e6fc0000 { 548 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 549 reg = <0 0xe6fc0000 0 0x30>; 550 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 554 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 555 clocks = <&cpg CPG_MOD 124>; 556 clock-names = "fck"; 557 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 558 resets = <&cpg 124>; 559 status = "disabled"; 560 }; 561 562 tmu2: timer@e6fd0000 { 563 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 564 reg = <0 0xe6fd0000 0 0x30>; 565 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 569 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 570 clocks = <&cpg CPG_MOD 123>; 571 clock-names = "fck"; 572 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 573 resets = <&cpg 123>; 574 status = "disabled"; 575 }; 576 577 tmu3: timer@e6fe0000 { 578 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 579 reg = <0 0xe6fe0000 0 0x30>; 580 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 583 interrupt-names = "tuni0", "tuni1", "tuni2"; 584 clocks = <&cpg CPG_MOD 122>; 585 clock-names = "fck"; 586 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 587 resets = <&cpg 122>; 588 status = "disabled"; 589 }; 590 591 tmu4: timer@ffc00000 { 592 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 593 reg = <0 0xffc00000 0 0x30>; 594 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 597 interrupt-names = "tuni0", "tuni1", "tuni2"; 598 clocks = <&cpg CPG_MOD 121>; 599 clock-names = "fck"; 600 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 601 resets = <&cpg 121>; 602 status = "disabled"; 603 }; 604 605 i2c0: i2c@e6500000 { 606 #address-cells = <1>; 607 #size-cells = <0>; 608 compatible = "renesas,i2c-r8a774a1", 609 "renesas,rcar-gen3-i2c"; 610 reg = <0 0xe6500000 0 0x40>; 611 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&cpg CPG_MOD 931>; 613 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 614 resets = <&cpg 931>; 615 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 616 <&dmac2 0x91>, <&dmac2 0x90>; 617 dma-names = "tx", "rx", "tx", "rx"; 618 i2c-scl-internal-delay-ns = <110>; 619 status = "disabled"; 620 }; 621 622 i2c1: i2c@e6508000 { 623 #address-cells = <1>; 624 #size-cells = <0>; 625 compatible = "renesas,i2c-r8a774a1", 626 "renesas,rcar-gen3-i2c"; 627 reg = <0 0xe6508000 0 0x40>; 628 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&cpg CPG_MOD 930>; 630 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 631 resets = <&cpg 930>; 632 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 633 <&dmac2 0x93>, <&dmac2 0x92>; 634 dma-names = "tx", "rx", "tx", "rx"; 635 i2c-scl-internal-delay-ns = <6>; 636 status = "disabled"; 637 }; 638 639 i2c2: i2c@e6510000 { 640 #address-cells = <1>; 641 #size-cells = <0>; 642 compatible = "renesas,i2c-r8a774a1", 643 "renesas,rcar-gen3-i2c"; 644 reg = <0 0xe6510000 0 0x40>; 645 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&cpg CPG_MOD 929>; 647 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 648 resets = <&cpg 929>; 649 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 650 <&dmac2 0x95>, <&dmac2 0x94>; 651 dma-names = "tx", "rx", "tx", "rx"; 652 i2c-scl-internal-delay-ns = <6>; 653 status = "disabled"; 654 }; 655 656 i2c3: i2c@e66d0000 { 657 #address-cells = <1>; 658 #size-cells = <0>; 659 compatible = "renesas,i2c-r8a774a1", 660 "renesas,rcar-gen3-i2c"; 661 reg = <0 0xe66d0000 0 0x40>; 662 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&cpg CPG_MOD 928>; 664 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 665 resets = <&cpg 928>; 666 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 667 dma-names = "tx", "rx"; 668 i2c-scl-internal-delay-ns = <110>; 669 status = "disabled"; 670 }; 671 672 i2c4: i2c@e66d8000 { 673 #address-cells = <1>; 674 #size-cells = <0>; 675 compatible = "renesas,i2c-r8a774a1", 676 "renesas,rcar-gen3-i2c"; 677 reg = <0 0xe66d8000 0 0x40>; 678 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&cpg CPG_MOD 927>; 680 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 681 resets = <&cpg 927>; 682 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 683 dma-names = "tx", "rx"; 684 i2c-scl-internal-delay-ns = <110>; 685 status = "disabled"; 686 }; 687 688 i2c5: i2c@e66e0000 { 689 #address-cells = <1>; 690 #size-cells = <0>; 691 compatible = "renesas,i2c-r8a774a1", 692 "renesas,rcar-gen3-i2c"; 693 reg = <0 0xe66e0000 0 0x40>; 694 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&cpg CPG_MOD 919>; 696 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 697 resets = <&cpg 919>; 698 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 699 dma-names = "tx", "rx"; 700 i2c-scl-internal-delay-ns = <110>; 701 status = "disabled"; 702 }; 703 704 i2c6: i2c@e66e8000 { 705 #address-cells = <1>; 706 #size-cells = <0>; 707 compatible = "renesas,i2c-r8a774a1", 708 "renesas,rcar-gen3-i2c"; 709 reg = <0 0xe66e8000 0 0x40>; 710 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&cpg CPG_MOD 918>; 712 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 713 resets = <&cpg 918>; 714 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 715 dma-names = "tx", "rx"; 716 i2c-scl-internal-delay-ns = <6>; 717 status = "disabled"; 718 }; 719 720 iic_pmic: i2c@e60b0000 { 721 #address-cells = <1>; 722 #size-cells = <0>; 723 compatible = "renesas,iic-r8a774a1", 724 "renesas,rcar-gen3-iic", 725 "renesas,rmobile-iic"; 726 reg = <0 0xe60b0000 0 0x425>; 727 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 728 clocks = <&cpg CPG_MOD 926>; 729 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 730 resets = <&cpg 926>; 731 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 732 dma-names = "tx", "rx"; 733 status = "disabled"; 734 }; 735 736 hscif0: serial@e6540000 { 737 compatible = "renesas,hscif-r8a774a1", 738 "renesas,rcar-gen3-hscif", 739 "renesas,hscif"; 740 reg = <0 0xe6540000 0 0x60>; 741 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 742 clocks = <&cpg CPG_MOD 520>, 743 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 744 <&scif_clk>; 745 clock-names = "fck", "brg_int", "scif_clk"; 746 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 747 <&dmac2 0x31>, <&dmac2 0x30>; 748 dma-names = "tx", "rx", "tx", "rx"; 749 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 750 resets = <&cpg 520>; 751 status = "disabled"; 752 }; 753 754 hscif1: serial@e6550000 { 755 compatible = "renesas,hscif-r8a774a1", 756 "renesas,rcar-gen3-hscif", 757 "renesas,hscif"; 758 reg = <0 0xe6550000 0 0x60>; 759 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 760 clocks = <&cpg CPG_MOD 519>, 761 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 762 <&scif_clk>; 763 clock-names = "fck", "brg_int", "scif_clk"; 764 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 765 <&dmac2 0x33>, <&dmac2 0x32>; 766 dma-names = "tx", "rx", "tx", "rx"; 767 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 768 resets = <&cpg 519>; 769 status = "disabled"; 770 }; 771 772 hscif2: serial@e6560000 { 773 compatible = "renesas,hscif-r8a774a1", 774 "renesas,rcar-gen3-hscif", 775 "renesas,hscif"; 776 reg = <0 0xe6560000 0 0x60>; 777 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 778 clocks = <&cpg CPG_MOD 518>, 779 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 780 <&scif_clk>; 781 clock-names = "fck", "brg_int", "scif_clk"; 782 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 783 <&dmac2 0x35>, <&dmac2 0x34>; 784 dma-names = "tx", "rx", "tx", "rx"; 785 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 786 resets = <&cpg 518>; 787 status = "disabled"; 788 }; 789 790 hscif3: serial@e66a0000 { 791 compatible = "renesas,hscif-r8a774a1", 792 "renesas,rcar-gen3-hscif", 793 "renesas,hscif"; 794 reg = <0 0xe66a0000 0 0x60>; 795 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&cpg CPG_MOD 517>, 797 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 798 <&scif_clk>; 799 clock-names = "fck", "brg_int", "scif_clk"; 800 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 801 dma-names = "tx", "rx"; 802 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 803 resets = <&cpg 517>; 804 status = "disabled"; 805 }; 806 807 hscif4: serial@e66b0000 { 808 compatible = "renesas,hscif-r8a774a1", 809 "renesas,rcar-gen3-hscif", 810 "renesas,hscif"; 811 reg = <0 0xe66b0000 0 0x60>; 812 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&cpg CPG_MOD 516>, 814 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 815 <&scif_clk>; 816 clock-names = "fck", "brg_int", "scif_clk"; 817 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 818 dma-names = "tx", "rx"; 819 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 820 resets = <&cpg 516>; 821 status = "disabled"; 822 }; 823 824 hsusb: usb@e6590000 { 825 compatible = "renesas,usbhs-r8a774a1", 826 "renesas,rcar-gen3-usbhs"; 827 reg = <0 0xe6590000 0 0x200>; 828 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 829 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 830 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 831 <&usb_dmac1 0>, <&usb_dmac1 1>; 832 dma-names = "ch0", "ch1", "ch2", "ch3"; 833 renesas,buswait = <11>; 834 phys = <&usb2_phy0 3>; 835 phy-names = "usb"; 836 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 837 resets = <&cpg 704>, <&cpg 703>; 838 status = "disabled"; 839 }; 840 841 usb2_clksel: clock-controller@e6590630 { 842 compatible = "renesas,r8a774a1-rcar-usb2-clock-sel", 843 "renesas,rcar-gen3-usb2-clock-sel"; 844 reg = <0 0xe6590630 0 0x02>; 845 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, 846 <&usb_extal_clk>, <&usb3s0_clk>; 847 clock-names = "ehci_ohci", "hs-usb-if", 848 "usb_extal", "usb_xtal"; 849 #clock-cells = <0>; 850 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 851 resets = <&cpg 703>, <&cpg 704>; 852 reset-names = "ehci_ohci", "hs-usb-if"; 853 status = "disabled"; 854 }; 855 856 usb_dmac0: dma-controller@e65a0000 { 857 compatible = "renesas,r8a774a1-usb-dmac", 858 "renesas,usb-dmac"; 859 reg = <0 0xe65a0000 0 0x100>; 860 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 862 interrupt-names = "ch0", "ch1"; 863 clocks = <&cpg CPG_MOD 330>; 864 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 865 resets = <&cpg 330>; 866 #dma-cells = <1>; 867 dma-channels = <2>; 868 }; 869 870 usb_dmac1: dma-controller@e65b0000 { 871 compatible = "renesas,r8a774a1-usb-dmac", 872 "renesas,usb-dmac"; 873 reg = <0 0xe65b0000 0 0x100>; 874 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 876 interrupt-names = "ch0", "ch1"; 877 clocks = <&cpg CPG_MOD 331>; 878 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 879 resets = <&cpg 331>; 880 #dma-cells = <1>; 881 dma-channels = <2>; 882 }; 883 884 usb3_phy0: usb-phy@e65ee000 { 885 compatible = "renesas,r8a774a1-usb3-phy", 886 "renesas,rcar-gen3-usb3-phy"; 887 reg = <0 0xe65ee000 0 0x90>; 888 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 889 <&usb_extal_clk>; 890 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 891 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 892 resets = <&cpg 328>; 893 #phy-cells = <0>; 894 status = "disabled"; 895 }; 896 897 dmac0: dma-controller@e6700000 { 898 compatible = "renesas,dmac-r8a774a1", 899 "renesas,rcar-dmac"; 900 reg = <0 0xe6700000 0 0x10000>; 901 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 918 interrupt-names = "error", 919 "ch0", "ch1", "ch2", "ch3", 920 "ch4", "ch5", "ch6", "ch7", 921 "ch8", "ch9", "ch10", "ch11", 922 "ch12", "ch13", "ch14", "ch15"; 923 clocks = <&cpg CPG_MOD 219>; 924 clock-names = "fck"; 925 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 926 resets = <&cpg 219>; 927 #dma-cells = <1>; 928 dma-channels = <16>; 929 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 930 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 931 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 932 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 933 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 934 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 935 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 936 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 937 }; 938 939 dmac1: dma-controller@e7300000 { 940 compatible = "renesas,dmac-r8a774a1", 941 "renesas,rcar-dmac"; 942 reg = <0 0xe7300000 0 0x10000>; 943 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 960 interrupt-names = "error", 961 "ch0", "ch1", "ch2", "ch3", 962 "ch4", "ch5", "ch6", "ch7", 963 "ch8", "ch9", "ch10", "ch11", 964 "ch12", "ch13", "ch14", "ch15"; 965 clocks = <&cpg CPG_MOD 218>; 966 clock-names = "fck"; 967 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 968 resets = <&cpg 218>; 969 #dma-cells = <1>; 970 dma-channels = <16>; 971 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 972 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 973 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 974 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 975 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 976 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 977 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 978 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 979 }; 980 981 dmac2: dma-controller@e7310000 { 982 compatible = "renesas,dmac-r8a774a1", 983 "renesas,rcar-dmac"; 984 reg = <0 0xe7310000 0 0x10000>; 985 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 1002 interrupt-names = "error", 1003 "ch0", "ch1", "ch2", "ch3", 1004 "ch4", "ch5", "ch6", "ch7", 1005 "ch8", "ch9", "ch10", "ch11", 1006 "ch12", "ch13", "ch14", "ch15"; 1007 clocks = <&cpg CPG_MOD 217>; 1008 clock-names = "fck"; 1009 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1010 resets = <&cpg 217>; 1011 #dma-cells = <1>; 1012 dma-channels = <16>; 1013 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1014 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1015 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1016 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1017 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1018 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1019 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1020 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1021 }; 1022 1023 ipmmu_ds0: iommu@e6740000 { 1024 compatible = "renesas,ipmmu-r8a774a1"; 1025 reg = <0 0xe6740000 0 0x1000>; 1026 renesas,ipmmu-main = <&ipmmu_mm 0>; 1027 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1028 #iommu-cells = <1>; 1029 }; 1030 1031 ipmmu_ds1: iommu@e7740000 { 1032 compatible = "renesas,ipmmu-r8a774a1"; 1033 reg = <0 0xe7740000 0 0x1000>; 1034 renesas,ipmmu-main = <&ipmmu_mm 1>; 1035 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1036 #iommu-cells = <1>; 1037 }; 1038 1039 ipmmu_hc: iommu@e6570000 { 1040 compatible = "renesas,ipmmu-r8a774a1"; 1041 reg = <0 0xe6570000 0 0x1000>; 1042 renesas,ipmmu-main = <&ipmmu_mm 2>; 1043 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1044 #iommu-cells = <1>; 1045 }; 1046 1047 ipmmu_mm: iommu@e67b0000 { 1048 compatible = "renesas,ipmmu-r8a774a1"; 1049 reg = <0 0xe67b0000 0 0x1000>; 1050 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1052 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1053 #iommu-cells = <1>; 1054 }; 1055 1056 ipmmu_mp: iommu@ec670000 { 1057 compatible = "renesas,ipmmu-r8a774a1"; 1058 reg = <0 0xec670000 0 0x1000>; 1059 renesas,ipmmu-main = <&ipmmu_mm 4>; 1060 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1061 #iommu-cells = <1>; 1062 }; 1063 1064 ipmmu_pv0: iommu@fd800000 { 1065 compatible = "renesas,ipmmu-r8a774a1"; 1066 reg = <0 0xfd800000 0 0x1000>; 1067 renesas,ipmmu-main = <&ipmmu_mm 5>; 1068 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1069 #iommu-cells = <1>; 1070 }; 1071 1072 ipmmu_pv1: iommu@fd950000 { 1073 compatible = "renesas,ipmmu-r8a774a1"; 1074 reg = <0 0xfd950000 0 0x1000>; 1075 renesas,ipmmu-main = <&ipmmu_mm 6>; 1076 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1077 #iommu-cells = <1>; 1078 }; 1079 1080 ipmmu_vc0: iommu@fe6b0000 { 1081 compatible = "renesas,ipmmu-r8a774a1"; 1082 reg = <0 0xfe6b0000 0 0x1000>; 1083 renesas,ipmmu-main = <&ipmmu_mm 8>; 1084 power-domains = <&sysc R8A774A1_PD_A3VC>; 1085 #iommu-cells = <1>; 1086 }; 1087 1088 ipmmu_vi0: iommu@febd0000 { 1089 compatible = "renesas,ipmmu-r8a774a1"; 1090 reg = <0 0xfebd0000 0 0x1000>; 1091 renesas,ipmmu-main = <&ipmmu_mm 9>; 1092 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1093 #iommu-cells = <1>; 1094 }; 1095 1096 avb: ethernet@e6800000 { 1097 compatible = "renesas,etheravb-r8a774a1", 1098 "renesas,etheravb-rcar-gen3"; 1099 reg = <0 0xe6800000 0 0x800>; 1100 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1125 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1126 "ch4", "ch5", "ch6", "ch7", 1127 "ch8", "ch9", "ch10", "ch11", 1128 "ch12", "ch13", "ch14", "ch15", 1129 "ch16", "ch17", "ch18", "ch19", 1130 "ch20", "ch21", "ch22", "ch23", 1131 "ch24"; 1132 clocks = <&cpg CPG_MOD 812>; 1133 clock-names = "fck"; 1134 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1135 resets = <&cpg 812>; 1136 phy-mode = "rgmii"; 1137 rx-internal-delay-ps = <0>; 1138 tx-internal-delay-ps = <0>; 1139 iommus = <&ipmmu_ds0 16>; 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 status = "disabled"; 1143 }; 1144 1145 can0: can@e6c30000 { 1146 compatible = "renesas,can-r8a774a1", 1147 "renesas,rcar-gen3-can"; 1148 reg = <0 0xe6c30000 0 0x1000>; 1149 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1150 clocks = <&cpg CPG_MOD 916>, 1151 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1152 <&can_clk>; 1153 clock-names = "clkp1", "clkp2", "can_clk"; 1154 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; 1155 assigned-clock-rates = <40000000>; 1156 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1157 resets = <&cpg 916>; 1158 status = "disabled"; 1159 }; 1160 1161 can1: can@e6c38000 { 1162 compatible = "renesas,can-r8a774a1", 1163 "renesas,rcar-gen3-can"; 1164 reg = <0 0xe6c38000 0 0x1000>; 1165 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1166 clocks = <&cpg CPG_MOD 915>, 1167 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1168 <&can_clk>; 1169 clock-names = "clkp1", "clkp2", "can_clk"; 1170 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; 1171 assigned-clock-rates = <40000000>; 1172 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1173 resets = <&cpg 915>; 1174 status = "disabled"; 1175 }; 1176 1177 canfd: can@e66c0000 { 1178 compatible = "renesas,r8a774a1-canfd", 1179 "renesas,rcar-gen3-canfd"; 1180 reg = <0 0xe66c0000 0 0x8000>; 1181 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1183 interrupt-names = "ch_int", "g_int"; 1184 clocks = <&cpg CPG_MOD 914>, 1185 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1186 <&can_clk>; 1187 clock-names = "fck", "canfd", "can_clk"; 1188 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; 1189 assigned-clock-rates = <40000000>; 1190 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1191 resets = <&cpg 914>; 1192 status = "disabled"; 1193 1194 channel0 { 1195 status = "disabled"; 1196 }; 1197 1198 channel1 { 1199 status = "disabled"; 1200 }; 1201 }; 1202 1203 pwm0: pwm@e6e30000 { 1204 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1205 reg = <0 0xe6e30000 0 0x8>; 1206 #pwm-cells = <2>; 1207 clocks = <&cpg CPG_MOD 523>; 1208 resets = <&cpg 523>; 1209 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1210 status = "disabled"; 1211 }; 1212 1213 pwm1: pwm@e6e31000 { 1214 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1215 reg = <0 0xe6e31000 0 0x8>; 1216 #pwm-cells = <2>; 1217 clocks = <&cpg CPG_MOD 523>; 1218 resets = <&cpg 523>; 1219 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1220 status = "disabled"; 1221 }; 1222 1223 pwm2: pwm@e6e32000 { 1224 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1225 reg = <0 0xe6e32000 0 0x8>; 1226 #pwm-cells = <2>; 1227 clocks = <&cpg CPG_MOD 523>; 1228 resets = <&cpg 523>; 1229 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1230 status = "disabled"; 1231 }; 1232 1233 pwm3: pwm@e6e33000 { 1234 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1235 reg = <0 0xe6e33000 0 0x8>; 1236 #pwm-cells = <2>; 1237 clocks = <&cpg CPG_MOD 523>; 1238 resets = <&cpg 523>; 1239 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1240 status = "disabled"; 1241 }; 1242 1243 pwm4: pwm@e6e34000 { 1244 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1245 reg = <0 0xe6e34000 0 0x8>; 1246 #pwm-cells = <2>; 1247 clocks = <&cpg CPG_MOD 523>; 1248 resets = <&cpg 523>; 1249 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1250 status = "disabled"; 1251 }; 1252 1253 pwm5: pwm@e6e35000 { 1254 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1255 reg = <0 0xe6e35000 0 0x8>; 1256 #pwm-cells = <2>; 1257 clocks = <&cpg CPG_MOD 523>; 1258 resets = <&cpg 523>; 1259 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1260 status = "disabled"; 1261 }; 1262 1263 pwm6: pwm@e6e36000 { 1264 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1265 reg = <0 0xe6e36000 0 0x8>; 1266 #pwm-cells = <2>; 1267 clocks = <&cpg CPG_MOD 523>; 1268 resets = <&cpg 523>; 1269 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1270 status = "disabled"; 1271 }; 1272 1273 scif0: serial@e6e60000 { 1274 compatible = "renesas,scif-r8a774a1", 1275 "renesas,rcar-gen3-scif", "renesas,scif"; 1276 reg = <0 0xe6e60000 0 0x40>; 1277 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1278 clocks = <&cpg CPG_MOD 207>, 1279 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1280 <&scif_clk>; 1281 clock-names = "fck", "brg_int", "scif_clk"; 1282 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1283 <&dmac2 0x51>, <&dmac2 0x50>; 1284 dma-names = "tx", "rx", "tx", "rx"; 1285 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1286 resets = <&cpg 207>; 1287 status = "disabled"; 1288 }; 1289 1290 scif1: serial@e6e68000 { 1291 compatible = "renesas,scif-r8a774a1", 1292 "renesas,rcar-gen3-scif", "renesas,scif"; 1293 reg = <0 0xe6e68000 0 0x40>; 1294 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1295 clocks = <&cpg CPG_MOD 206>, 1296 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1297 <&scif_clk>; 1298 clock-names = "fck", "brg_int", "scif_clk"; 1299 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1300 <&dmac2 0x53>, <&dmac2 0x52>; 1301 dma-names = "tx", "rx", "tx", "rx"; 1302 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1303 resets = <&cpg 206>; 1304 status = "disabled"; 1305 }; 1306 1307 scif2: serial@e6e88000 { 1308 compatible = "renesas,scif-r8a774a1", 1309 "renesas,rcar-gen3-scif", "renesas,scif"; 1310 reg = <0 0xe6e88000 0 0x40>; 1311 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1312 clocks = <&cpg CPG_MOD 310>, 1313 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1314 <&scif_clk>; 1315 clock-names = "fck", "brg_int", "scif_clk"; 1316 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1317 <&dmac2 0x13>, <&dmac2 0x12>; 1318 dma-names = "tx", "rx", "tx", "rx"; 1319 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1320 resets = <&cpg 310>; 1321 status = "disabled"; 1322 }; 1323 1324 scif3: serial@e6c50000 { 1325 compatible = "renesas,scif-r8a774a1", 1326 "renesas,rcar-gen3-scif", "renesas,scif"; 1327 reg = <0 0xe6c50000 0 0x40>; 1328 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1329 clocks = <&cpg CPG_MOD 204>, 1330 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1331 <&scif_clk>; 1332 clock-names = "fck", "brg_int", "scif_clk"; 1333 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1334 dma-names = "tx", "rx"; 1335 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1336 resets = <&cpg 204>; 1337 status = "disabled"; 1338 }; 1339 1340 scif4: serial@e6c40000 { 1341 compatible = "renesas,scif-r8a774a1", 1342 "renesas,rcar-gen3-scif", "renesas,scif"; 1343 reg = <0 0xe6c40000 0 0x40>; 1344 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1345 clocks = <&cpg CPG_MOD 203>, 1346 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1347 <&scif_clk>; 1348 clock-names = "fck", "brg_int", "scif_clk"; 1349 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1350 dma-names = "tx", "rx"; 1351 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1352 resets = <&cpg 203>; 1353 status = "disabled"; 1354 }; 1355 1356 scif5: serial@e6f30000 { 1357 compatible = "renesas,scif-r8a774a1", 1358 "renesas,rcar-gen3-scif", "renesas,scif"; 1359 reg = <0 0xe6f30000 0 0x40>; 1360 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1361 clocks = <&cpg CPG_MOD 202>, 1362 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1363 <&scif_clk>; 1364 clock-names = "fck", "brg_int", "scif_clk"; 1365 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1366 <&dmac2 0x5b>, <&dmac2 0x5a>; 1367 dma-names = "tx", "rx", "tx", "rx"; 1368 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1369 resets = <&cpg 202>; 1370 status = "disabled"; 1371 }; 1372 1373 msiof0: spi@e6e90000 { 1374 compatible = "renesas,msiof-r8a774a1", 1375 "renesas,rcar-gen3-msiof"; 1376 reg = <0 0xe6e90000 0 0x0064>; 1377 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1378 clocks = <&cpg CPG_MOD 211>; 1379 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1380 <&dmac2 0x41>, <&dmac2 0x40>; 1381 dma-names = "tx", "rx", "tx", "rx"; 1382 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1383 resets = <&cpg 211>; 1384 #address-cells = <1>; 1385 #size-cells = <0>; 1386 status = "disabled"; 1387 }; 1388 1389 msiof1: spi@e6ea0000 { 1390 compatible = "renesas,msiof-r8a774a1", 1391 "renesas,rcar-gen3-msiof"; 1392 reg = <0 0xe6ea0000 0 0x0064>; 1393 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1394 clocks = <&cpg CPG_MOD 210>; 1395 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1396 <&dmac2 0x43>, <&dmac2 0x42>; 1397 dma-names = "tx", "rx", "tx", "rx"; 1398 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1399 resets = <&cpg 210>; 1400 #address-cells = <1>; 1401 #size-cells = <0>; 1402 status = "disabled"; 1403 }; 1404 1405 msiof2: spi@e6c00000 { 1406 compatible = "renesas,msiof-r8a774a1", 1407 "renesas,rcar-gen3-msiof"; 1408 reg = <0 0xe6c00000 0 0x0064>; 1409 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1410 clocks = <&cpg CPG_MOD 209>; 1411 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1412 dma-names = "tx", "rx"; 1413 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1414 resets = <&cpg 209>; 1415 #address-cells = <1>; 1416 #size-cells = <0>; 1417 status = "disabled"; 1418 }; 1419 1420 msiof3: spi@e6c10000 { 1421 compatible = "renesas,msiof-r8a774a1", 1422 "renesas,rcar-gen3-msiof"; 1423 reg = <0 0xe6c10000 0 0x0064>; 1424 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1425 clocks = <&cpg CPG_MOD 208>; 1426 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1427 dma-names = "tx", "rx"; 1428 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1429 resets = <&cpg 208>; 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 status = "disabled"; 1433 }; 1434 1435 vin0: video@e6ef0000 { 1436 compatible = "renesas,vin-r8a774a1"; 1437 reg = <0 0xe6ef0000 0 0x1000>; 1438 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1439 clocks = <&cpg CPG_MOD 811>; 1440 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1441 resets = <&cpg 811>; 1442 renesas,id = <0>; 1443 status = "disabled"; 1444 1445 ports { 1446 #address-cells = <1>; 1447 #size-cells = <0>; 1448 1449 port@1 { 1450 #address-cells = <1>; 1451 #size-cells = <0>; 1452 1453 reg = <1>; 1454 1455 vin0csi20: endpoint@0 { 1456 reg = <0>; 1457 remote-endpoint = <&csi20vin0>; 1458 }; 1459 vin0csi40: endpoint@2 { 1460 reg = <2>; 1461 remote-endpoint = <&csi40vin0>; 1462 }; 1463 }; 1464 }; 1465 }; 1466 1467 vin1: video@e6ef1000 { 1468 compatible = "renesas,vin-r8a774a1"; 1469 reg = <0 0xe6ef1000 0 0x1000>; 1470 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1471 clocks = <&cpg CPG_MOD 810>; 1472 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1473 resets = <&cpg 810>; 1474 renesas,id = <1>; 1475 status = "disabled"; 1476 1477 ports { 1478 #address-cells = <1>; 1479 #size-cells = <0>; 1480 1481 port@1 { 1482 #address-cells = <1>; 1483 #size-cells = <0>; 1484 1485 reg = <1>; 1486 1487 vin1csi20: endpoint@0 { 1488 reg = <0>; 1489 remote-endpoint = <&csi20vin1>; 1490 }; 1491 vin1csi40: endpoint@2 { 1492 reg = <2>; 1493 remote-endpoint = <&csi40vin1>; 1494 }; 1495 }; 1496 }; 1497 }; 1498 1499 vin2: video@e6ef2000 { 1500 compatible = "renesas,vin-r8a774a1"; 1501 reg = <0 0xe6ef2000 0 0x1000>; 1502 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1503 clocks = <&cpg CPG_MOD 809>; 1504 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1505 resets = <&cpg 809>; 1506 renesas,id = <2>; 1507 status = "disabled"; 1508 1509 ports { 1510 #address-cells = <1>; 1511 #size-cells = <0>; 1512 1513 port@1 { 1514 #address-cells = <1>; 1515 #size-cells = <0>; 1516 1517 reg = <1>; 1518 1519 vin2csi20: endpoint@0 { 1520 reg = <0>; 1521 remote-endpoint = <&csi20vin2>; 1522 }; 1523 vin2csi40: endpoint@2 { 1524 reg = <2>; 1525 remote-endpoint = <&csi40vin2>; 1526 }; 1527 }; 1528 }; 1529 }; 1530 1531 vin3: video@e6ef3000 { 1532 compatible = "renesas,vin-r8a774a1"; 1533 reg = <0 0xe6ef3000 0 0x1000>; 1534 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1535 clocks = <&cpg CPG_MOD 808>; 1536 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1537 resets = <&cpg 808>; 1538 renesas,id = <3>; 1539 status = "disabled"; 1540 1541 ports { 1542 #address-cells = <1>; 1543 #size-cells = <0>; 1544 1545 port@1 { 1546 #address-cells = <1>; 1547 #size-cells = <0>; 1548 1549 reg = <1>; 1550 1551 vin3csi20: endpoint@0 { 1552 reg = <0>; 1553 remote-endpoint = <&csi20vin3>; 1554 }; 1555 vin3csi40: endpoint@2 { 1556 reg = <2>; 1557 remote-endpoint = <&csi40vin3>; 1558 }; 1559 }; 1560 }; 1561 }; 1562 1563 vin4: video@e6ef4000 { 1564 compatible = "renesas,vin-r8a774a1"; 1565 reg = <0 0xe6ef4000 0 0x1000>; 1566 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1567 clocks = <&cpg CPG_MOD 807>; 1568 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1569 resets = <&cpg 807>; 1570 renesas,id = <4>; 1571 status = "disabled"; 1572 1573 ports { 1574 #address-cells = <1>; 1575 #size-cells = <0>; 1576 1577 port@1 { 1578 #address-cells = <1>; 1579 #size-cells = <0>; 1580 1581 reg = <1>; 1582 1583 vin4csi20: endpoint@0 { 1584 reg = <0>; 1585 remote-endpoint = <&csi20vin4>; 1586 }; 1587 vin4csi40: endpoint@2 { 1588 reg = <2>; 1589 remote-endpoint = <&csi40vin4>; 1590 }; 1591 }; 1592 }; 1593 }; 1594 1595 vin5: video@e6ef5000 { 1596 compatible = "renesas,vin-r8a774a1"; 1597 reg = <0 0xe6ef5000 0 0x1000>; 1598 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1599 clocks = <&cpg CPG_MOD 806>; 1600 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1601 resets = <&cpg 806>; 1602 renesas,id = <5>; 1603 status = "disabled"; 1604 1605 ports { 1606 #address-cells = <1>; 1607 #size-cells = <0>; 1608 1609 port@1 { 1610 #address-cells = <1>; 1611 #size-cells = <0>; 1612 1613 reg = <1>; 1614 1615 vin5csi20: endpoint@0 { 1616 reg = <0>; 1617 remote-endpoint = <&csi20vin5>; 1618 }; 1619 vin5csi40: endpoint@2 { 1620 reg = <2>; 1621 remote-endpoint = <&csi40vin5>; 1622 }; 1623 }; 1624 }; 1625 }; 1626 1627 vin6: video@e6ef6000 { 1628 compatible = "renesas,vin-r8a774a1"; 1629 reg = <0 0xe6ef6000 0 0x1000>; 1630 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1631 clocks = <&cpg CPG_MOD 805>; 1632 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1633 resets = <&cpg 805>; 1634 renesas,id = <6>; 1635 status = "disabled"; 1636 1637 ports { 1638 #address-cells = <1>; 1639 #size-cells = <0>; 1640 1641 port@1 { 1642 #address-cells = <1>; 1643 #size-cells = <0>; 1644 1645 reg = <1>; 1646 1647 vin6csi20: endpoint@0 { 1648 reg = <0>; 1649 remote-endpoint = <&csi20vin6>; 1650 }; 1651 vin6csi40: endpoint@2 { 1652 reg = <2>; 1653 remote-endpoint = <&csi40vin6>; 1654 }; 1655 }; 1656 }; 1657 }; 1658 1659 vin7: video@e6ef7000 { 1660 compatible = "renesas,vin-r8a774a1"; 1661 reg = <0 0xe6ef7000 0 0x1000>; 1662 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1663 clocks = <&cpg CPG_MOD 804>; 1664 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1665 resets = <&cpg 804>; 1666 renesas,id = <7>; 1667 status = "disabled"; 1668 1669 ports { 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 1673 port@1 { 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 1677 reg = <1>; 1678 1679 vin7csi20: endpoint@0 { 1680 reg = <0>; 1681 remote-endpoint = <&csi20vin7>; 1682 }; 1683 vin7csi40: endpoint@2 { 1684 reg = <2>; 1685 remote-endpoint = <&csi40vin7>; 1686 }; 1687 }; 1688 }; 1689 }; 1690 1691 rcar_sound: sound@ec500000 { 1692 /* 1693 * #sound-dai-cells is required if simple-card 1694 * 1695 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1696 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1697 */ 1698 /* 1699 * #clock-cells is required for audio_clkout0/1/2/3 1700 * 1701 * clkout : #clock-cells = <0>; <&rcar_sound>; 1702 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1703 */ 1704 compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3"; 1705 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1706 <0 0xec5a0000 0 0x100>, /* ADG */ 1707 <0 0xec540000 0 0x1000>, /* SSIU */ 1708 <0 0xec541000 0 0x280>, /* SSI */ 1709 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1710 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1711 1712 clocks = <&cpg CPG_MOD 1005>, 1713 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1714 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1715 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1716 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1717 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1718 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1719 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1720 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1721 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1722 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1723 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1724 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1725 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1726 <&audio_clk_a>, <&audio_clk_b>, 1727 <&audio_clk_c>, 1728 <&cpg CPG_MOD 922>; 1729 clock-names = "ssi-all", 1730 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1731 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1732 "ssi.1", "ssi.0", 1733 "src.9", "src.8", "src.7", "src.6", 1734 "src.5", "src.4", "src.3", "src.2", 1735 "src.1", "src.0", 1736 "mix.1", "mix.0", 1737 "ctu.1", "ctu.0", 1738 "dvc.0", "dvc.1", 1739 "clk_a", "clk_b", "clk_c", "clk_i"; 1740 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1741 resets = <&cpg 1005>, 1742 <&cpg 1006>, <&cpg 1007>, 1743 <&cpg 1008>, <&cpg 1009>, 1744 <&cpg 1010>, <&cpg 1011>, 1745 <&cpg 1012>, <&cpg 1013>, 1746 <&cpg 1014>, <&cpg 1015>; 1747 reset-names = "ssi-all", 1748 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1749 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1750 "ssi.1", "ssi.0"; 1751 status = "disabled"; 1752 1753 rcar_sound,ctu { 1754 ctu00: ctu-0 { }; 1755 ctu01: ctu-1 { }; 1756 ctu02: ctu-2 { }; 1757 ctu03: ctu-3 { }; 1758 ctu10: ctu-4 { }; 1759 ctu11: ctu-5 { }; 1760 ctu12: ctu-6 { }; 1761 ctu13: ctu-7 { }; 1762 }; 1763 1764 rcar_sound,dvc { 1765 dvc0: dvc-0 { 1766 dmas = <&audma1 0xbc>; 1767 dma-names = "tx"; 1768 }; 1769 dvc1: dvc-1 { 1770 dmas = <&audma1 0xbe>; 1771 dma-names = "tx"; 1772 }; 1773 }; 1774 1775 rcar_sound,mix { 1776 mix0: mix-0 { }; 1777 mix1: mix-1 { }; 1778 }; 1779 1780 rcar_sound,src { 1781 src0: src-0 { 1782 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1783 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1784 dma-names = "rx", "tx"; 1785 }; 1786 src1: src-1 { 1787 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1788 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1789 dma-names = "rx", "tx"; 1790 }; 1791 src2: src-2 { 1792 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1793 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1794 dma-names = "rx", "tx"; 1795 }; 1796 src3: src-3 { 1797 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1798 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1799 dma-names = "rx", "tx"; 1800 }; 1801 src4: src-4 { 1802 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1803 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1804 dma-names = "rx", "tx"; 1805 }; 1806 src5: src-5 { 1807 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1808 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1809 dma-names = "rx", "tx"; 1810 }; 1811 src6: src-6 { 1812 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1813 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1814 dma-names = "rx", "tx"; 1815 }; 1816 src7: src-7 { 1817 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1818 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1819 dma-names = "rx", "tx"; 1820 }; 1821 src8: src-8 { 1822 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1823 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1824 dma-names = "rx", "tx"; 1825 }; 1826 src9: src-9 { 1827 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1828 dmas = <&audma0 0x97>, <&audma1 0xba>; 1829 dma-names = "rx", "tx"; 1830 }; 1831 }; 1832 1833 rcar_sound,ssi { 1834 ssi0: ssi-0 { 1835 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1836 dmas = <&audma0 0x01>, <&audma1 0x02>; 1837 dma-names = "rx", "tx"; 1838 }; 1839 ssi1: ssi-1 { 1840 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1841 dmas = <&audma0 0x03>, <&audma1 0x04>; 1842 dma-names = "rx", "tx"; 1843 }; 1844 ssi2: ssi-2 { 1845 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1846 dmas = <&audma0 0x05>, <&audma1 0x06>; 1847 dma-names = "rx", "tx"; 1848 }; 1849 ssi3: ssi-3 { 1850 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1851 dmas = <&audma0 0x07>, <&audma1 0x08>; 1852 dma-names = "rx", "tx"; 1853 }; 1854 ssi4: ssi-4 { 1855 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1856 dmas = <&audma0 0x09>, <&audma1 0x0a>; 1857 dma-names = "rx", "tx"; 1858 }; 1859 ssi5: ssi-5 { 1860 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1861 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 1862 dma-names = "rx", "tx"; 1863 }; 1864 ssi6: ssi-6 { 1865 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1866 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 1867 dma-names = "rx", "tx"; 1868 }; 1869 ssi7: ssi-7 { 1870 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1871 dmas = <&audma0 0x0f>, <&audma1 0x10>; 1872 dma-names = "rx", "tx"; 1873 }; 1874 ssi8: ssi-8 { 1875 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1876 dmas = <&audma0 0x11>, <&audma1 0x12>; 1877 dma-names = "rx", "tx"; 1878 }; 1879 ssi9: ssi-9 { 1880 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1881 dmas = <&audma0 0x13>, <&audma1 0x14>; 1882 dma-names = "rx", "tx"; 1883 }; 1884 }; 1885 1886 rcar_sound,ssiu { 1887 ssiu00: ssiu-0 { 1888 dmas = <&audma0 0x15>, <&audma1 0x16>; 1889 dma-names = "rx", "tx"; 1890 }; 1891 ssiu01: ssiu-1 { 1892 dmas = <&audma0 0x35>, <&audma1 0x36>; 1893 dma-names = "rx", "tx"; 1894 }; 1895 ssiu02: ssiu-2 { 1896 dmas = <&audma0 0x37>, <&audma1 0x38>; 1897 dma-names = "rx", "tx"; 1898 }; 1899 ssiu03: ssiu-3 { 1900 dmas = <&audma0 0x47>, <&audma1 0x48>; 1901 dma-names = "rx", "tx"; 1902 }; 1903 ssiu04: ssiu-4 { 1904 dmas = <&audma0 0x3F>, <&audma1 0x40>; 1905 dma-names = "rx", "tx"; 1906 }; 1907 ssiu05: ssiu-5 { 1908 dmas = <&audma0 0x43>, <&audma1 0x44>; 1909 dma-names = "rx", "tx"; 1910 }; 1911 ssiu06: ssiu-6 { 1912 dmas = <&audma0 0x4F>, <&audma1 0x50>; 1913 dma-names = "rx", "tx"; 1914 }; 1915 ssiu07: ssiu-7 { 1916 dmas = <&audma0 0x53>, <&audma1 0x54>; 1917 dma-names = "rx", "tx"; 1918 }; 1919 ssiu10: ssiu-8 { 1920 dmas = <&audma0 0x49>, <&audma1 0x4a>; 1921 dma-names = "rx", "tx"; 1922 }; 1923 ssiu11: ssiu-9 { 1924 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 1925 dma-names = "rx", "tx"; 1926 }; 1927 ssiu12: ssiu-10 { 1928 dmas = <&audma0 0x57>, <&audma1 0x58>; 1929 dma-names = "rx", "tx"; 1930 }; 1931 ssiu13: ssiu-11 { 1932 dmas = <&audma0 0x59>, <&audma1 0x5A>; 1933 dma-names = "rx", "tx"; 1934 }; 1935 ssiu14: ssiu-12 { 1936 dmas = <&audma0 0x5F>, <&audma1 0x60>; 1937 dma-names = "rx", "tx"; 1938 }; 1939 ssiu15: ssiu-13 { 1940 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 1941 dma-names = "rx", "tx"; 1942 }; 1943 ssiu16: ssiu-14 { 1944 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 1945 dma-names = "rx", "tx"; 1946 }; 1947 ssiu17: ssiu-15 { 1948 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 1949 dma-names = "rx", "tx"; 1950 }; 1951 ssiu20: ssiu-16 { 1952 dmas = <&audma0 0x63>, <&audma1 0x64>; 1953 dma-names = "rx", "tx"; 1954 }; 1955 ssiu21: ssiu-17 { 1956 dmas = <&audma0 0x67>, <&audma1 0x68>; 1957 dma-names = "rx", "tx"; 1958 }; 1959 ssiu22: ssiu-18 { 1960 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 1961 dma-names = "rx", "tx"; 1962 }; 1963 ssiu23: ssiu-19 { 1964 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 1965 dma-names = "rx", "tx"; 1966 }; 1967 ssiu24: ssiu-20 { 1968 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 1969 dma-names = "rx", "tx"; 1970 }; 1971 ssiu25: ssiu-21 { 1972 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 1973 dma-names = "rx", "tx"; 1974 }; 1975 ssiu26: ssiu-22 { 1976 dmas = <&audma0 0xED>, <&audma1 0xEE>; 1977 dma-names = "rx", "tx"; 1978 }; 1979 ssiu27: ssiu-23 { 1980 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 1981 dma-names = "rx", "tx"; 1982 }; 1983 ssiu30: ssiu-24 { 1984 dmas = <&audma0 0x6f>, <&audma1 0x70>; 1985 dma-names = "rx", "tx"; 1986 }; 1987 ssiu31: ssiu-25 { 1988 dmas = <&audma0 0x21>, <&audma1 0x22>; 1989 dma-names = "rx", "tx"; 1990 }; 1991 ssiu32: ssiu-26 { 1992 dmas = <&audma0 0x23>, <&audma1 0x24>; 1993 dma-names = "rx", "tx"; 1994 }; 1995 ssiu33: ssiu-27 { 1996 dmas = <&audma0 0x25>, <&audma1 0x26>; 1997 dma-names = "rx", "tx"; 1998 }; 1999 ssiu34: ssiu-28 { 2000 dmas = <&audma0 0x27>, <&audma1 0x28>; 2001 dma-names = "rx", "tx"; 2002 }; 2003 ssiu35: ssiu-29 { 2004 dmas = <&audma0 0x29>, <&audma1 0x2A>; 2005 dma-names = "rx", "tx"; 2006 }; 2007 ssiu36: ssiu-30 { 2008 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 2009 dma-names = "rx", "tx"; 2010 }; 2011 ssiu37: ssiu-31 { 2012 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 2013 dma-names = "rx", "tx"; 2014 }; 2015 ssiu40: ssiu-32 { 2016 dmas = <&audma0 0x71>, <&audma1 0x72>; 2017 dma-names = "rx", "tx"; 2018 }; 2019 ssiu41: ssiu-33 { 2020 dmas = <&audma0 0x17>, <&audma1 0x18>; 2021 dma-names = "rx", "tx"; 2022 }; 2023 ssiu42: ssiu-34 { 2024 dmas = <&audma0 0x19>, <&audma1 0x1A>; 2025 dma-names = "rx", "tx"; 2026 }; 2027 ssiu43: ssiu-35 { 2028 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 2029 dma-names = "rx", "tx"; 2030 }; 2031 ssiu44: ssiu-36 { 2032 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 2033 dma-names = "rx", "tx"; 2034 }; 2035 ssiu45: ssiu-37 { 2036 dmas = <&audma0 0x1F>, <&audma1 0x20>; 2037 dma-names = "rx", "tx"; 2038 }; 2039 ssiu46: ssiu-38 { 2040 dmas = <&audma0 0x31>, <&audma1 0x32>; 2041 dma-names = "rx", "tx"; 2042 }; 2043 ssiu47: ssiu-39 { 2044 dmas = <&audma0 0x33>, <&audma1 0x34>; 2045 dma-names = "rx", "tx"; 2046 }; 2047 ssiu50: ssiu-40 { 2048 dmas = <&audma0 0x73>, <&audma1 0x74>; 2049 dma-names = "rx", "tx"; 2050 }; 2051 ssiu60: ssiu-41 { 2052 dmas = <&audma0 0x75>, <&audma1 0x76>; 2053 dma-names = "rx", "tx"; 2054 }; 2055 ssiu70: ssiu-42 { 2056 dmas = <&audma0 0x79>, <&audma1 0x7a>; 2057 dma-names = "rx", "tx"; 2058 }; 2059 ssiu80: ssiu-43 { 2060 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 2061 dma-names = "rx", "tx"; 2062 }; 2063 ssiu90: ssiu-44 { 2064 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 2065 dma-names = "rx", "tx"; 2066 }; 2067 ssiu91: ssiu-45 { 2068 dmas = <&audma0 0x7F>, <&audma1 0x80>; 2069 dma-names = "rx", "tx"; 2070 }; 2071 ssiu92: ssiu-46 { 2072 dmas = <&audma0 0x81>, <&audma1 0x82>; 2073 dma-names = "rx", "tx"; 2074 }; 2075 ssiu93: ssiu-47 { 2076 dmas = <&audma0 0x83>, <&audma1 0x84>; 2077 dma-names = "rx", "tx"; 2078 }; 2079 ssiu94: ssiu-48 { 2080 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 2081 dma-names = "rx", "tx"; 2082 }; 2083 ssiu95: ssiu-49 { 2084 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 2085 dma-names = "rx", "tx"; 2086 }; 2087 ssiu96: ssiu-50 { 2088 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 2089 dma-names = "rx", "tx"; 2090 }; 2091 ssiu97: ssiu-51 { 2092 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 2093 dma-names = "rx", "tx"; 2094 }; 2095 }; 2096 }; 2097 2098 audma0: dma-controller@ec700000 { 2099 compatible = "renesas,dmac-r8a774a1", 2100 "renesas,rcar-dmac"; 2101 reg = <0 0xec700000 0 0x10000>; 2102 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2113 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2117 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2118 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 2119 interrupt-names = "error", 2120 "ch0", "ch1", "ch2", "ch3", 2121 "ch4", "ch5", "ch6", "ch7", 2122 "ch8", "ch9", "ch10", "ch11", 2123 "ch12", "ch13", "ch14", "ch15"; 2124 clocks = <&cpg CPG_MOD 502>; 2125 clock-names = "fck"; 2126 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2127 resets = <&cpg 502>; 2128 #dma-cells = <1>; 2129 dma-channels = <16>; 2130 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 2131 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 2132 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 2133 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 2134 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 2135 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 2136 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 2137 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 2138 }; 2139 2140 audma1: dma-controller@ec720000 { 2141 compatible = "renesas,dmac-r8a774a1", 2142 "renesas,rcar-dmac"; 2143 reg = <0 0xec720000 0 0x10000>; 2144 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 2145 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2146 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2147 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2148 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2149 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2150 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2151 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2152 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2153 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2154 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2155 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 2156 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2157 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 2158 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 2159 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 2160 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 2161 interrupt-names = "error", 2162 "ch0", "ch1", "ch2", "ch3", 2163 "ch4", "ch5", "ch6", "ch7", 2164 "ch8", "ch9", "ch10", "ch11", 2165 "ch12", "ch13", "ch14", "ch15"; 2166 clocks = <&cpg CPG_MOD 501>; 2167 clock-names = "fck"; 2168 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2169 resets = <&cpg 501>; 2170 #dma-cells = <1>; 2171 dma-channels = <16>; 2172 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, 2173 <&ipmmu_mp 18>, <&ipmmu_mp 19>, 2174 <&ipmmu_mp 20>, <&ipmmu_mp 21>, 2175 <&ipmmu_mp 22>, <&ipmmu_mp 23>, 2176 <&ipmmu_mp 24>, <&ipmmu_mp 25>, 2177 <&ipmmu_mp 26>, <&ipmmu_mp 27>, 2178 <&ipmmu_mp 28>, <&ipmmu_mp 29>, 2179 <&ipmmu_mp 30>, <&ipmmu_mp 31>; 2180 }; 2181 2182 xhci0: usb@ee000000 { 2183 compatible = "renesas,xhci-r8a774a1", 2184 "renesas,rcar-gen3-xhci"; 2185 reg = <0 0xee000000 0 0xc00>; 2186 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2187 clocks = <&cpg CPG_MOD 328>; 2188 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2189 resets = <&cpg 328>; 2190 status = "disabled"; 2191 }; 2192 2193 usb3_peri0: usb@ee020000 { 2194 compatible = "renesas,r8a774a1-usb3-peri", 2195 "renesas,rcar-gen3-usb3-peri"; 2196 reg = <0 0xee020000 0 0x400>; 2197 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2198 clocks = <&cpg CPG_MOD 328>; 2199 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2200 resets = <&cpg 328>; 2201 status = "disabled"; 2202 }; 2203 2204 ohci0: usb@ee080000 { 2205 compatible = "generic-ohci"; 2206 reg = <0 0xee080000 0 0x100>; 2207 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2208 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2209 phys = <&usb2_phy0 1>; 2210 phy-names = "usb"; 2211 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2212 resets = <&cpg 703>, <&cpg 704>; 2213 status = "disabled"; 2214 }; 2215 2216 ohci1: usb@ee0a0000 { 2217 compatible = "generic-ohci"; 2218 reg = <0 0xee0a0000 0 0x100>; 2219 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2220 clocks = <&cpg CPG_MOD 702>; 2221 phys = <&usb2_phy1 1>; 2222 phy-names = "usb"; 2223 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2224 resets = <&cpg 702>; 2225 status = "disabled"; 2226 }; 2227 2228 ehci0: usb@ee080100 { 2229 compatible = "generic-ehci"; 2230 reg = <0 0xee080100 0 0x100>; 2231 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2232 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2233 phys = <&usb2_phy0 2>; 2234 phy-names = "usb"; 2235 companion = <&ohci0>; 2236 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2237 resets = <&cpg 703>, <&cpg 704>; 2238 status = "disabled"; 2239 }; 2240 2241 ehci1: usb@ee0a0100 { 2242 compatible = "generic-ehci"; 2243 reg = <0 0xee0a0100 0 0x100>; 2244 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2245 clocks = <&cpg CPG_MOD 702>; 2246 phys = <&usb2_phy1 2>; 2247 phy-names = "usb"; 2248 companion = <&ohci1>; 2249 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2250 resets = <&cpg 702>; 2251 status = "disabled"; 2252 }; 2253 2254 usb2_phy0: usb-phy@ee080200 { 2255 compatible = "renesas,usb2-phy-r8a774a1", 2256 "renesas,rcar-gen3-usb2-phy"; 2257 reg = <0 0xee080200 0 0x700>; 2258 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2259 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2260 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2261 resets = <&cpg 703>, <&cpg 704>; 2262 #phy-cells = <1>; 2263 status = "disabled"; 2264 }; 2265 2266 usb2_phy1: usb-phy@ee0a0200 { 2267 compatible = "renesas,usb2-phy-r8a774a1", 2268 "renesas,rcar-gen3-usb2-phy"; 2269 reg = <0 0xee0a0200 0 0x700>; 2270 clocks = <&cpg CPG_MOD 702>; 2271 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2272 resets = <&cpg 702>; 2273 #phy-cells = <1>; 2274 status = "disabled"; 2275 }; 2276 2277 sdhi0: mmc@ee100000 { 2278 compatible = "renesas,sdhi-r8a774a1", 2279 "renesas,rcar-gen3-sdhi"; 2280 reg = <0 0xee100000 0 0x2000>; 2281 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 2282 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774A1_CLK_SD0H>; 2283 clock-names = "core", "clkh"; 2284 max-frequency = <200000000>; 2285 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2286 resets = <&cpg 314>; 2287 iommus = <&ipmmu_ds1 32>; 2288 status = "disabled"; 2289 }; 2290 2291 sdhi1: mmc@ee120000 { 2292 compatible = "renesas,sdhi-r8a774a1", 2293 "renesas,rcar-gen3-sdhi"; 2294 reg = <0 0xee120000 0 0x2000>; 2295 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 2296 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774A1_CLK_SD1H>; 2297 clock-names = "core", "clkh"; 2298 max-frequency = <200000000>; 2299 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2300 resets = <&cpg 313>; 2301 iommus = <&ipmmu_ds1 33>; 2302 status = "disabled"; 2303 }; 2304 2305 sdhi2: mmc@ee140000 { 2306 compatible = "renesas,sdhi-r8a774a1", 2307 "renesas,rcar-gen3-sdhi"; 2308 reg = <0 0xee140000 0 0x2000>; 2309 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 2310 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774A1_CLK_SD2H>; 2311 clock-names = "core", "clkh"; 2312 max-frequency = <200000000>; 2313 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2314 resets = <&cpg 312>; 2315 iommus = <&ipmmu_ds1 34>; 2316 status = "disabled"; 2317 }; 2318 2319 sdhi3: mmc@ee160000 { 2320 compatible = "renesas,sdhi-r8a774a1", 2321 "renesas,rcar-gen3-sdhi"; 2322 reg = <0 0xee160000 0 0x2000>; 2323 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 2324 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774A1_CLK_SD3H>; 2325 clock-names = "core", "clkh"; 2326 max-frequency = <200000000>; 2327 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2328 resets = <&cpg 311>; 2329 iommus = <&ipmmu_ds1 35>; 2330 status = "disabled"; 2331 }; 2332 2333 rpc: spi@ee200000 { 2334 compatible = "renesas,r8a774a1-rpc-if", 2335 "renesas,rcar-gen3-rpc-if"; 2336 reg = <0 0xee200000 0 0x200>, 2337 <0 0x08000000 0 0x4000000>, 2338 <0 0xee208000 0 0x100>; 2339 reg-names = "regs", "dirmap", "wbuf"; 2340 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 2341 clocks = <&cpg CPG_MOD 917>; 2342 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2343 resets = <&cpg 917>; 2344 #address-cells = <1>; 2345 #size-cells = <0>; 2346 status = "disabled"; 2347 }; 2348 2349 gic: interrupt-controller@f1010000 { 2350 compatible = "arm,gic-400"; 2351 #interrupt-cells = <3>; 2352 #address-cells = <0>; 2353 interrupt-controller; 2354 reg = <0x0 0xf1010000 0 0x1000>, 2355 <0x0 0xf1020000 0 0x20000>, 2356 <0x0 0xf1040000 0 0x20000>, 2357 <0x0 0xf1060000 0 0x20000>; 2358 interrupts = <GIC_PPI 9 2359 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 2360 clocks = <&cpg CPG_MOD 408>; 2361 clock-names = "clk"; 2362 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2363 resets = <&cpg 408>; 2364 }; 2365 2366 pciec0: pcie@fe000000 { 2367 compatible = "renesas,pcie-r8a774a1", 2368 "renesas,pcie-rcar-gen3"; 2369 reg = <0 0xfe000000 0 0x80000>; 2370 #address-cells = <3>; 2371 #size-cells = <2>; 2372 bus-range = <0x00 0xff>; 2373 device_type = "pci"; 2374 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 2375 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 2376 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 2377 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 2378 /* Map all possible DDR/IOMMU as inbound ranges */ 2379 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; 2380 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2381 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2382 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2383 #interrupt-cells = <1>; 2384 interrupt-map-mask = <0 0 0 0>; 2385 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2386 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2387 clock-names = "pcie", "pcie_bus"; 2388 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2389 resets = <&cpg 319>; 2390 iommu-map = <0 &ipmmu_hc 0 1>; 2391 iommu-map-mask = <0>; 2392 status = "disabled"; 2393 }; 2394 2395 pciec1: pcie@ee800000 { 2396 compatible = "renesas,pcie-r8a774a1", 2397 "renesas,pcie-rcar-gen3"; 2398 reg = <0 0xee800000 0 0x80000>; 2399 #address-cells = <3>; 2400 #size-cells = <2>; 2401 bus-range = <0x00 0xff>; 2402 device_type = "pci"; 2403 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 2404 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 2405 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 2406 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2407 /* Map all possible DDR/IOMMU as inbound ranges */ 2408 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; 2409 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2410 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2411 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2412 #interrupt-cells = <1>; 2413 interrupt-map-mask = <0 0 0 0>; 2414 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2415 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2416 clock-names = "pcie", "pcie_bus"; 2417 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2418 resets = <&cpg 318>; 2419 iommu-map = <0 &ipmmu_hc 1 1>; 2420 iommu-map-mask = <0>; 2421 status = "disabled"; 2422 }; 2423 2424 pciec0_ep: pcie-ep@fe000000 { 2425 compatible = "renesas,r8a774a1-pcie-ep", 2426 "renesas,rcar-gen3-pcie-ep"; 2427 reg = <0x0 0xfe000000 0 0x80000>, 2428 <0x0 0xfe100000 0 0x100000>, 2429 <0x0 0xfe200000 0 0x200000>, 2430 <0x0 0x30000000 0 0x8000000>, 2431 <0x0 0x38000000 0 0x8000000>; 2432 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 2433 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2434 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2435 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2436 clocks = <&cpg CPG_MOD 319>; 2437 clock-names = "pcie"; 2438 resets = <&cpg 319>; 2439 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2440 status = "disabled"; 2441 }; 2442 2443 pciec1_ep: pcie-ep@ee800000 { 2444 compatible = "renesas,r8a774a1-pcie-ep", 2445 "renesas,rcar-gen3-pcie-ep"; 2446 reg = <0x0 0xee800000 0 0x80000>, 2447 <0x0 0xee900000 0 0x100000>, 2448 <0x0 0xeea00000 0 0x200000>, 2449 <0x0 0xc0000000 0 0x8000000>, 2450 <0x0 0xc8000000 0 0x8000000>; 2451 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 2452 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2453 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2454 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2455 clocks = <&cpg CPG_MOD 318>; 2456 clock-names = "pcie"; 2457 resets = <&cpg 318>; 2458 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2459 status = "disabled"; 2460 }; 2461 2462 fdp1@fe940000 { 2463 compatible = "renesas,fdp1"; 2464 reg = <0 0xfe940000 0 0x2400>; 2465 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 2466 clocks = <&cpg CPG_MOD 119>; 2467 power-domains = <&sysc R8A774A1_PD_A3VC>; 2468 resets = <&cpg 119>; 2469 renesas,fcp = <&fcpf0>; 2470 }; 2471 2472 fcpf0: fcp@fe950000 { 2473 compatible = "renesas,fcpf"; 2474 reg = <0 0xfe950000 0 0x200>; 2475 clocks = <&cpg CPG_MOD 615>; 2476 power-domains = <&sysc R8A774A1_PD_A3VC>; 2477 resets = <&cpg 615>; 2478 iommus = <&ipmmu_vc0 16>; 2479 }; 2480 2481 fcpvb0: fcp@fe96f000 { 2482 compatible = "renesas,fcpv"; 2483 reg = <0 0xfe96f000 0 0x200>; 2484 clocks = <&cpg CPG_MOD 607>; 2485 power-domains = <&sysc R8A774A1_PD_A3VC>; 2486 resets = <&cpg 607>; 2487 iommus = <&ipmmu_vi0 5>; 2488 }; 2489 2490 fcpvd0: fcp@fea27000 { 2491 compatible = "renesas,fcpv"; 2492 reg = <0 0xfea27000 0 0x200>; 2493 clocks = <&cpg CPG_MOD 603>; 2494 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2495 resets = <&cpg 603>; 2496 iommus = <&ipmmu_vi0 8>; 2497 }; 2498 2499 fcpvd1: fcp@fea2f000 { 2500 compatible = "renesas,fcpv"; 2501 reg = <0 0xfea2f000 0 0x200>; 2502 clocks = <&cpg CPG_MOD 602>; 2503 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2504 resets = <&cpg 602>; 2505 iommus = <&ipmmu_vi0 9>; 2506 }; 2507 2508 fcpvd2: fcp@fea37000 { 2509 compatible = "renesas,fcpv"; 2510 reg = <0 0xfea37000 0 0x200>; 2511 clocks = <&cpg CPG_MOD 601>; 2512 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2513 resets = <&cpg 601>; 2514 iommus = <&ipmmu_vi0 10>; 2515 }; 2516 2517 fcpvi0: fcp@fe9af000 { 2518 compatible = "renesas,fcpv"; 2519 reg = <0 0xfe9af000 0 0x200>; 2520 clocks = <&cpg CPG_MOD 611>; 2521 power-domains = <&sysc R8A774A1_PD_A3VC>; 2522 resets = <&cpg 611>; 2523 iommus = <&ipmmu_vc0 19>; 2524 }; 2525 2526 vspb: vsp@fe960000 { 2527 compatible = "renesas,vsp2"; 2528 reg = <0 0xfe960000 0 0x8000>; 2529 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2530 clocks = <&cpg CPG_MOD 626>; 2531 power-domains = <&sysc R8A774A1_PD_A3VC>; 2532 resets = <&cpg 626>; 2533 2534 renesas,fcp = <&fcpvb0>; 2535 }; 2536 2537 vspd0: vsp@fea20000 { 2538 compatible = "renesas,vsp2"; 2539 reg = <0 0xfea20000 0 0x5000>; 2540 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2541 clocks = <&cpg CPG_MOD 623>; 2542 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2543 resets = <&cpg 623>; 2544 2545 renesas,fcp = <&fcpvd0>; 2546 }; 2547 2548 vspd1: vsp@fea28000 { 2549 compatible = "renesas,vsp2"; 2550 reg = <0 0xfea28000 0 0x5000>; 2551 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2552 clocks = <&cpg CPG_MOD 622>; 2553 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2554 resets = <&cpg 622>; 2555 2556 renesas,fcp = <&fcpvd1>; 2557 }; 2558 2559 vspd2: vsp@fea30000 { 2560 compatible = "renesas,vsp2"; 2561 reg = <0 0xfea30000 0 0x5000>; 2562 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2563 clocks = <&cpg CPG_MOD 621>; 2564 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2565 resets = <&cpg 621>; 2566 2567 renesas,fcp = <&fcpvd2>; 2568 }; 2569 2570 vspi0: vsp@fe9a0000 { 2571 compatible = "renesas,vsp2"; 2572 reg = <0 0xfe9a0000 0 0x8000>; 2573 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2574 clocks = <&cpg CPG_MOD 631>; 2575 power-domains = <&sysc R8A774A1_PD_A3VC>; 2576 resets = <&cpg 631>; 2577 2578 renesas,fcp = <&fcpvi0>; 2579 }; 2580 2581 csi20: csi2@fea80000 { 2582 compatible = "renesas,r8a774a1-csi2"; 2583 reg = <0 0xfea80000 0 0x10000>; 2584 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2585 clocks = <&cpg CPG_MOD 714>; 2586 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2587 resets = <&cpg 714>; 2588 status = "disabled"; 2589 2590 ports { 2591 #address-cells = <1>; 2592 #size-cells = <0>; 2593 2594 port@0 { 2595 reg = <0>; 2596 }; 2597 2598 port@1 { 2599 #address-cells = <1>; 2600 #size-cells = <0>; 2601 2602 reg = <1>; 2603 2604 csi20vin0: endpoint@0 { 2605 reg = <0>; 2606 remote-endpoint = <&vin0csi20>; 2607 }; 2608 csi20vin1: endpoint@1 { 2609 reg = <1>; 2610 remote-endpoint = <&vin1csi20>; 2611 }; 2612 csi20vin2: endpoint@2 { 2613 reg = <2>; 2614 remote-endpoint = <&vin2csi20>; 2615 }; 2616 csi20vin3: endpoint@3 { 2617 reg = <3>; 2618 remote-endpoint = <&vin3csi20>; 2619 }; 2620 csi20vin4: endpoint@4 { 2621 reg = <4>; 2622 remote-endpoint = <&vin4csi20>; 2623 }; 2624 csi20vin5: endpoint@5 { 2625 reg = <5>; 2626 remote-endpoint = <&vin5csi20>; 2627 }; 2628 csi20vin6: endpoint@6 { 2629 reg = <6>; 2630 remote-endpoint = <&vin6csi20>; 2631 }; 2632 csi20vin7: endpoint@7 { 2633 reg = <7>; 2634 remote-endpoint = <&vin7csi20>; 2635 }; 2636 }; 2637 }; 2638 }; 2639 2640 csi40: csi2@feaa0000 { 2641 compatible = "renesas,r8a774a1-csi2"; 2642 reg = <0 0xfeaa0000 0 0x10000>; 2643 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2644 clocks = <&cpg CPG_MOD 716>; 2645 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2646 resets = <&cpg 716>; 2647 status = "disabled"; 2648 2649 ports { 2650 #address-cells = <1>; 2651 #size-cells = <0>; 2652 2653 port@0 { 2654 reg = <0>; 2655 }; 2656 2657 port@1 { 2658 #address-cells = <1>; 2659 #size-cells = <0>; 2660 2661 reg = <1>; 2662 2663 csi40vin0: endpoint@0 { 2664 reg = <0>; 2665 remote-endpoint = <&vin0csi40>; 2666 }; 2667 csi40vin1: endpoint@1 { 2668 reg = <1>; 2669 remote-endpoint = <&vin1csi40>; 2670 }; 2671 csi40vin2: endpoint@2 { 2672 reg = <2>; 2673 remote-endpoint = <&vin2csi40>; 2674 }; 2675 csi40vin3: endpoint@3 { 2676 reg = <3>; 2677 remote-endpoint = <&vin3csi40>; 2678 }; 2679 csi40vin4: endpoint@4 { 2680 reg = <4>; 2681 remote-endpoint = <&vin4csi40>; 2682 }; 2683 csi40vin5: endpoint@5 { 2684 reg = <5>; 2685 remote-endpoint = <&vin5csi40>; 2686 }; 2687 csi40vin6: endpoint@6 { 2688 reg = <6>; 2689 remote-endpoint = <&vin6csi40>; 2690 }; 2691 csi40vin7: endpoint@7 { 2692 reg = <7>; 2693 remote-endpoint = <&vin7csi40>; 2694 }; 2695 }; 2696 2697 }; 2698 }; 2699 2700 hdmi0: hdmi@fead0000 { 2701 compatible = "renesas,r8a774a1-hdmi", 2702 "renesas,rcar-gen3-hdmi"; 2703 reg = <0 0xfead0000 0 0x10000>; 2704 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 2705 clocks = <&cpg CPG_MOD 729>, 2706 <&cpg CPG_CORE R8A774A1_CLK_HDMI>; 2707 clock-names = "iahb", "isfr"; 2708 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2709 resets = <&cpg 729>; 2710 status = "disabled"; 2711 2712 ports { 2713 #address-cells = <1>; 2714 #size-cells = <0>; 2715 port@0 { 2716 reg = <0>; 2717 dw_hdmi0_in: endpoint { 2718 remote-endpoint = <&du_out_hdmi0>; 2719 }; 2720 }; 2721 port@1 { 2722 reg = <1>; 2723 }; 2724 port@2 { 2725 /* HDMI sound */ 2726 reg = <2>; 2727 }; 2728 }; 2729 }; 2730 2731 du: display@feb00000 { 2732 compatible = "renesas,du-r8a774a1"; 2733 reg = <0 0xfeb00000 0 0x70000>; 2734 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2735 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2736 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2737 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 2738 <&cpg CPG_MOD 722>; 2739 clock-names = "du.0", "du.1", "du.2"; 2740 resets = <&cpg 724>, <&cpg 722>; 2741 reset-names = "du.0", "du.2"; 2742 status = "disabled"; 2743 2744 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; 2745 2746 ports { 2747 #address-cells = <1>; 2748 #size-cells = <0>; 2749 2750 port@0 { 2751 reg = <0>; 2752 }; 2753 port@1 { 2754 reg = <1>; 2755 du_out_hdmi0: endpoint { 2756 remote-endpoint = <&dw_hdmi0_in>; 2757 }; 2758 }; 2759 port@2 { 2760 reg = <2>; 2761 du_out_lvds0: endpoint { 2762 remote-endpoint = <&lvds0_in>; 2763 }; 2764 }; 2765 }; 2766 }; 2767 2768 lvds0: lvds@feb90000 { 2769 compatible = "renesas,r8a774a1-lvds"; 2770 reg = <0 0xfeb90000 0 0x14>; 2771 clocks = <&cpg CPG_MOD 727>; 2772 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2773 resets = <&cpg 727>; 2774 status = "disabled"; 2775 2776 ports { 2777 #address-cells = <1>; 2778 #size-cells = <0>; 2779 2780 port@0 { 2781 reg = <0>; 2782 lvds0_in: endpoint { 2783 remote-endpoint = <&du_out_lvds0>; 2784 }; 2785 }; 2786 port@1 { 2787 reg = <1>; 2788 }; 2789 }; 2790 }; 2791 2792 prr: chipid@fff00044 { 2793 compatible = "renesas,prr"; 2794 reg = <0 0xfff00044 0 4>; 2795 bootph-all; 2796 }; 2797 }; 2798 2799 thermal-zones { 2800 sensor1_thermal: sensor1-thermal { 2801 polling-delay-passive = <250>; 2802 polling-delay = <1000>; 2803 thermal-sensors = <&tsc 0>; 2804 sustainable-power = <3874>; 2805 2806 trips { 2807 sensor1_crit: sensor1-crit { 2808 temperature = <120000>; 2809 hysteresis = <1000>; 2810 type = "critical"; 2811 }; 2812 }; 2813 }; 2814 2815 sensor2_thermal: sensor2-thermal { 2816 polling-delay-passive = <250>; 2817 polling-delay = <1000>; 2818 thermal-sensors = <&tsc 1>; 2819 sustainable-power = <3874>; 2820 2821 trips { 2822 sensor2_crit: sensor2-crit { 2823 temperature = <120000>; 2824 hysteresis = <1000>; 2825 type = "critical"; 2826 }; 2827 }; 2828 }; 2829 2830 sensor3_thermal: sensor3-thermal { 2831 polling-delay-passive = <250>; 2832 polling-delay = <1000>; 2833 thermal-sensors = <&tsc 2>; 2834 sustainable-power = <3874>; 2835 2836 cooling-maps { 2837 map0 { 2838 trip = <&target>; 2839 cooling-device = <&a57_0 0 2>; 2840 contribution = <1024>; 2841 }; 2842 map1 { 2843 trip = <&target>; 2844 cooling-device = <&a53_0 0 2>; 2845 contribution = <1024>; 2846 }; 2847 }; 2848 trips { 2849 target: trip-point1 { 2850 temperature = <100000>; 2851 hysteresis = <1000>; 2852 type = "passive"; 2853 }; 2854 2855 sensor3_crit: sensor3-crit { 2856 temperature = <120000>; 2857 hysteresis = <1000>; 2858 type = "critical"; 2859 }; 2860 }; 2861 }; 2862 }; 2863 2864 timer { 2865 compatible = "arm,armv8-timer"; 2866 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2867 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2868 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2869 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 2870 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; 2871 }; 2872 2873 /* External USB clocks - can be overridden by the board */ 2874 usb3s0_clk: usb3s0 { 2875 compatible = "fixed-clock"; 2876 #clock-cells = <0>; 2877 clock-frequency = <0>; 2878 }; 2879 2880 usb_extal_clk: usb_extal { 2881 compatible = "fixed-clock"; 2882 #clock-cells = <0>; 2883 clock-frequency = <0>; 2884 }; 2885}; 2886