1 /*
2 * Flush the host cpu caches.
3 *
4 * This work is licensed under the terms of the GNU GPL, version 2 or later.
5 * See the COPYING file in the top-level directory.
6 */
7
8 #ifndef QEMU_CACHEFLUSH_H
9 #define QEMU_CACHEFLUSH_H
10
11 /**
12 * flush_idcache_range:
13 * @rx: instruction address
14 * @rw: data address
15 * @len: length to flush
16 *
17 * Flush @len bytes of the data cache at @rw and the icache at @rx
18 * to bring them in sync. The two addresses may be different virtual
19 * mappings of the same physical page(s).
20 */
21
22 #if defined(__i386__) || defined(__x86_64__) || defined(__s390__)
23
flush_idcache_range(uintptr_t rx,uintptr_t rw,size_t len)24 static inline void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
25 {
26 /* icache is coherent and does not require flushing. */
27 }
28
29 #elif defined(EMSCRIPTEN)
30
flush_idcache_range(uintptr_t rx,uintptr_t rw,size_t len)31 static inline void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
32 {
33 /* Wasm doesn't have executable region of memory. */
34 }
35
36 #else
37
38 void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len);
39
40 #endif
41
42 #endif /* QEMU_CACHEFLUSH_H */
43