1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2025 Intel Corporation */
3 #include "qat_freebsd.h"
4 #include "adf_cfg.h"
5 #include "adf_common_drv.h"
6 #include "adf_accel_devices.h"
7 #include "adf_dh895xcc_hw_data.h"
8 #include "adf_fw_counters.h"
9 #include "adf_cfg_device.h"
10 #include "adf_dbgfs.h"
11 #include <sys/types.h>
12 #include <sys/kernel.h>
13 #include <sys/malloc.h>
14 #include <machine/bus_dma.h>
15 #include <dev/pci/pcireg.h>
16
17 static MALLOC_DEFINE(M_QAT_DH895XCC, "qat_dh895xcc", "qat_dh895xcc");
18
19 #define ADF_SYSTEM_DEVICE(device_id) \
20 { \
21 PCI_VENDOR_ID_INTEL, device_id \
22 }
23
24 static const struct pci_device_id adf_pci_tbl[] =
25 { ADF_SYSTEM_DEVICE(ADF_DH895XCC_PCI_DEVICE_ID),
26 {
27 0,
28 } };
29
30 static int
adf_probe(device_t dev)31 adf_probe(device_t dev)
32 {
33 const struct pci_device_id *id;
34
35 for (id = adf_pci_tbl; id->vendor != 0; id++) {
36 if (pci_get_vendor(dev) == id->vendor &&
37 pci_get_device(dev) == id->device) {
38 device_set_desc(dev,
39 "Intel " ADF_DH895XCC_DEVICE_NAME
40 " QuickAssist");
41 return BUS_PROBE_DEFAULT;
42 }
43 }
44 return ENXIO;
45 }
46
47 static void
adf_cleanup_accel(struct adf_accel_dev * accel_dev)48 adf_cleanup_accel(struct adf_accel_dev *accel_dev)
49 {
50 struct adf_accel_pci *accel_pci_dev = &accel_dev->accel_pci_dev;
51 int i;
52
53 if (accel_dev->dma_tag)
54 bus_dma_tag_destroy(accel_dev->dma_tag);
55 for (i = 0; i < ADF_PCI_MAX_BARS; i++) {
56 struct adf_bar *bar = &accel_pci_dev->pci_bars[i];
57
58 if (bar->virt_addr)
59 bus_free_resource(accel_pci_dev->pci_dev,
60 SYS_RES_MEMORY,
61 bar->virt_addr);
62 }
63
64 if (accel_dev->hw_device) {
65 switch (pci_get_device(accel_pci_dev->pci_dev)) {
66 case ADF_DH895XCC_PCI_DEVICE_ID:
67 adf_clean_hw_data_dh895xcc(accel_dev->hw_device);
68 break;
69 default:
70 break;
71 }
72 free(accel_dev->hw_device, M_QAT_DH895XCC);
73 accel_dev->hw_device = NULL;
74 }
75 adf_dbgfs_exit(accel_dev);
76 adf_cfg_dev_remove(accel_dev);
77 adf_devmgr_rm_dev(accel_dev, NULL);
78 }
79
80 static int
adf_attach(device_t dev)81 adf_attach(device_t dev)
82 {
83 struct adf_accel_dev *accel_dev;
84 struct adf_accel_pci *accel_pci_dev;
85 struct adf_hw_device_data *hw_data;
86 unsigned int i, bar_nr;
87 int ret = 0, rid;
88 struct adf_cfg_device *cfg_dev = NULL;
89
90 /* Set pci MaxPayLoad to 256. Implemented to avoid the issue of
91 * Pci-passthrough causing Maxpayload to be reset to 128 bytes
92 * when the device is reset. */
93 if (pci_get_max_payload(dev) != 256)
94 pci_set_max_payload(dev, 256);
95
96 accel_dev = device_get_softc(dev);
97
98 mutex_init(&accel_dev->lock);
99 INIT_LIST_HEAD(&accel_dev->crypto_list);
100 accel_pci_dev = &accel_dev->accel_pci_dev;
101 accel_pci_dev->pci_dev = dev;
102
103 if (bus_get_domain(dev, &accel_pci_dev->node) != 0)
104 accel_pci_dev->node = 0;
105
106 /* Add accel device to accel table.
107 * This should be called before adf_cleanup_accel is called */
108 ret = adf_devmgr_add_dev(accel_dev, NULL);
109 if (ret) {
110 device_printf(dev, "Failed to add new accelerator device.\n");
111 goto out_err_lock;
112 }
113
114 /* Allocate and configure device configuration structure */
115 hw_data = malloc(sizeof(*hw_data), M_QAT_DH895XCC, M_WAITOK | M_ZERO);
116
117 accel_dev->hw_device = hw_data;
118 adf_init_hw_data_dh895xcc(accel_dev->hw_device);
119 accel_pci_dev->revid = pci_get_revid(dev);
120 hw_data->fuses = pci_read_config(dev, ADF_DEVICE_FUSECTL_OFFSET, 4);
121
122 /* Get PPAERUCM values and store */
123 ret = adf_aer_store_ppaerucm_reg(dev, hw_data);
124 if (ret)
125 goto out_err;
126
127 /* Get Accelerators and Accelerators Engines masks */
128 hw_data->accel_mask = hw_data->get_accel_mask(accel_dev);
129 hw_data->ae_mask = hw_data->get_ae_mask(accel_dev);
130 hw_data->admin_ae_mask = hw_data->ae_mask;
131 accel_pci_dev->sku = hw_data->get_sku(hw_data);
132 /* If the device has no acceleration engines then ignore it. */
133 if (!hw_data->accel_mask || !hw_data->ae_mask ||
134 ((~hw_data->ae_mask) & 0x01)) {
135 device_printf(dev, "No acceleration units found\n");
136 ret = ENXIO;
137 goto out_err;
138 }
139
140 /* Create device configuration table */
141 ret = adf_cfg_dev_add(accel_dev);
142 if (ret)
143 goto out_err;
144
145 pci_set_max_read_req(dev, 1024);
146
147 ret = bus_dma_tag_create(bus_get_dma_tag(dev),
148 1,
149 0,
150 BUS_SPACE_MAXADDR,
151 BUS_SPACE_MAXADDR,
152 NULL,
153 NULL,
154 BUS_SPACE_MAXSIZE,
155 /* BUS_SPACE_UNRESTRICTED */ 1,
156 BUS_SPACE_MAXSIZE,
157 0,
158 NULL,
159 NULL,
160 &accel_dev->dma_tag);
161 if (ret)
162 goto out_err;
163
164 if (hw_data->get_accel_cap) {
165 hw_data->accel_capabilities_mask =
166 hw_data->get_accel_cap(accel_dev);
167 }
168
169 /* Find and map all the device's BARS */
170 i = 0;
171 for (bar_nr = 0; i < ADF_PCI_MAX_BARS && bar_nr < PCIR_MAX_BAR_0;
172 bar_nr++) {
173 struct adf_bar *bar;
174
175 /*
176 * This will ignore a BAR
177 * that wasn't assigned a valid resource range by the
178 * firmware.
179 */
180 rid = PCIR_BAR(bar_nr);
181 if (bus_get_resource(dev, SYS_RES_MEMORY, rid, NULL, NULL) != 0)
182 continue;
183 bar = &accel_pci_dev->pci_bars[i++];
184 bar->virt_addr = bus_alloc_resource_any(dev,
185 SYS_RES_MEMORY,
186 &rid,
187 RF_ACTIVE);
188 if (bar->virt_addr == NULL) {
189 device_printf(dev, "Failed to map BAR %d\n", bar_nr);
190 ret = ENXIO;
191 goto out_err;
192 }
193 bar->base_addr = rman_get_start(bar->virt_addr);
194 bar->size = rman_get_size(bar->virt_addr);
195 }
196 ret = pci_enable_busmaster(dev);
197 if (ret)
198 goto out_err;
199
200 adf_dbgfs_init(accel_dev);
201
202 if (!accel_dev->hw_device->config_device) {
203 ret = EFAULT;
204 goto out_err_disable;
205 }
206
207 ret = accel_dev->hw_device->config_device(accel_dev);
208 if (ret)
209 goto out_err_disable;
210
211 ret = adf_dev_init(accel_dev);
212 if (ret)
213 goto out_dev_shutdown;
214
215 ret = adf_dev_start(accel_dev);
216 if (ret)
217 goto out_dev_stop;
218
219 cfg_dev = accel_dev->cfg->dev;
220 adf_cfg_device_clear(cfg_dev, accel_dev);
221 free(cfg_dev, M_QAT);
222 accel_dev->cfg->dev = NULL;
223 return ret;
224 out_dev_stop:
225 adf_dev_stop(accel_dev);
226 out_dev_shutdown:
227 adf_dev_shutdown(accel_dev);
228 out_err_disable:
229 pci_disable_busmaster(dev);
230 out_err:
231 adf_cleanup_accel(accel_dev);
232 out_err_lock:
233 mutex_destroy(&accel_dev->lock);
234
235 return ret;
236 }
237
238 static int
adf_detach(device_t dev)239 adf_detach(device_t dev)
240 {
241 struct adf_accel_dev *accel_dev = device_get_softc(dev);
242
243 if (adf_dev_stop(accel_dev)) {
244 device_printf(dev, "Failed to stop QAT accel dev\n");
245 return EBUSY;
246 }
247
248 adf_dev_shutdown(accel_dev);
249
250 pci_disable_busmaster(dev);
251 adf_cleanup_accel(accel_dev);
252 mutex_destroy(&accel_dev->lock);
253
254 return 0;
255 }
256
257 static device_method_t adf_methods[] = { DEVMETHOD(device_probe, adf_probe),
258 DEVMETHOD(device_attach, adf_attach),
259 DEVMETHOD(device_detach, adf_detach),
260
261 DEVMETHOD_END };
262
263 static driver_t adf_driver = { "qat",
264 adf_methods,
265 sizeof(struct adf_accel_dev) };
266
267 DRIVER_MODULE_ORDERED(qat_dh895xcc,
268 pci,
269 adf_driver,
270 NULL,
271 NULL,
272 SI_ORDER_THIRD);
273 MODULE_VERSION(qat_dh895xcc, 1);
274 MODULE_DEPEND(qat_dh895xcc, qat_common, 1, 1, 1);
275 MODULE_DEPEND(qat_dh895xcc, qat_api, 1, 1, 1);
276 MODULE_DEPEND(qat_dh895xcc, linuxkpi, 1, 1, 1);
277