1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2025 Intel Corporation */
3 #include "qat_freebsd.h"
4 #include "adf_cfg.h"
5 #include "adf_common_drv.h"
6 #include "adf_accel_devices.h"
7 #include "adf_200xx_hw_data.h"
8 #include "adf_fw_counters.h"
9 #include "adf_cfg_device.h"
10 #include "adf_dbgfs.h"
11 #include <sys/types.h>
12 #include <sys/kernel.h>
13 #include <sys/malloc.h>
14 #include <machine/bus_dma.h>
15 #include <dev/pci/pcireg.h>
16
17 static MALLOC_DEFINE(M_QAT_200XX, "qat_200xx", "qat_200xx");
18
19 #define ADF_SYSTEM_DEVICE(device_id) \
20 { \
21 PCI_VENDOR_ID_INTEL, device_id \
22 }
23
24 static const struct pci_device_id adf_pci_tbl[] =
25 { ADF_SYSTEM_DEVICE(ADF_200XX_PCI_DEVICE_ID),
26 {
27 0,
28 } };
29
30 static int
adf_probe(device_t dev)31 adf_probe(device_t dev)
32 {
33 const struct pci_device_id *id;
34
35 for (id = adf_pci_tbl; id->vendor != 0; id++) {
36 if (pci_get_vendor(dev) == id->vendor &&
37 pci_get_device(dev) == id->device) {
38 device_set_desc(dev,
39 "Intel " ADF_200XX_DEVICE_NAME
40 " QuickAssist");
41 return BUS_PROBE_GENERIC;
42 }
43 }
44 return ENXIO;
45 }
46
47 static void
adf_cleanup_accel(struct adf_accel_dev * accel_dev)48 adf_cleanup_accel(struct adf_accel_dev *accel_dev)
49 {
50 struct adf_accel_pci *accel_pci_dev = &accel_dev->accel_pci_dev;
51 int i;
52
53 if (accel_dev->dma_tag)
54 bus_dma_tag_destroy(accel_dev->dma_tag);
55 for (i = 0; i < ADF_PCI_MAX_BARS; i++) {
56 struct adf_bar *bar = &accel_pci_dev->pci_bars[i];
57
58 if (bar->virt_addr)
59 bus_free_resource(accel_pci_dev->pci_dev,
60 SYS_RES_MEMORY,
61 bar->virt_addr);
62 }
63
64 if (accel_dev->hw_device) {
65 switch (pci_get_device(accel_pci_dev->pci_dev)) {
66 case ADF_200XX_PCI_DEVICE_ID:
67 adf_clean_hw_data_200xx(accel_dev->hw_device);
68 break;
69 default:
70 break;
71 }
72 free(accel_dev->hw_device, M_QAT_200XX);
73 accel_dev->hw_device = NULL;
74 }
75 adf_dbgfs_exit(accel_dev);
76 adf_cfg_dev_remove(accel_dev);
77 adf_devmgr_rm_dev(accel_dev, NULL);
78 }
79
80 static int
adf_attach(device_t dev)81 adf_attach(device_t dev)
82 {
83 struct adf_accel_dev *accel_dev;
84 struct adf_accel_pci *accel_pci_dev;
85 struct adf_hw_device_data *hw_data;
86 unsigned int i = 0, bar_nr = 0, reg_val = 0;
87 int ret = 0, rid;
88 struct adf_cfg_device *cfg_dev = NULL;
89
90 /* Set pci MaxPayLoad to 256. Implemented to avoid the issue of
91 * Pci-passthrough causing Maxpayload to be reset to 128 bytes
92 * when the device is reset.
93 */
94 if (pci_get_max_payload(dev) != 256)
95 pci_set_max_payload(dev, 256);
96
97 accel_dev = device_get_softc(dev);
98
99 mutex_init(&accel_dev->lock);
100 INIT_LIST_HEAD(&accel_dev->crypto_list);
101 accel_pci_dev = &accel_dev->accel_pci_dev;
102 accel_pci_dev->pci_dev = dev;
103
104 if (bus_get_domain(dev, &accel_pci_dev->node) != 0)
105 accel_pci_dev->node = 0;
106
107 /* XXX: Revisit if we actually need a devmgr table at all. */
108
109 /* Add accel device to accel table.
110 * This should be called before adf_cleanup_accel is called
111 */
112 ret = adf_devmgr_add_dev(accel_dev, NULL);
113 if (ret) {
114 device_printf(dev, "Failed to add new accelerator device.\n");
115 goto out_err_lock;
116 }
117
118 /* Allocate and configure device configuration structure */
119 hw_data = malloc(sizeof(*hw_data), M_QAT_200XX, M_WAITOK | M_ZERO);
120
121 accel_dev->hw_device = hw_data;
122 adf_init_hw_data_200xx(accel_dev->hw_device);
123 accel_pci_dev->revid = pci_get_revid(dev);
124 hw_data->fuses = pci_read_config(dev, ADF_DEVICE_FUSECTL_OFFSET, 4);
125 if (accel_pci_dev->revid == 0x00) {
126 device_printf(dev, "A0 stepping is not supported.\n");
127 ret = ENODEV;
128 goto out_err;
129 }
130
131 /* Get PPAERUCM values and store */
132 ret = adf_aer_store_ppaerucm_reg(dev, hw_data);
133 if (ret)
134 goto out_err;
135
136 /* Clear PFIEERRUNCSTSR register bits if they are set */
137 reg_val = pci_read_config(dev, ADF_200XX_PFIEERRUNCSTSR, 4);
138 if (reg_val) {
139 device_printf(
140 dev,
141 "Clearing PFIEERRUNCSTSR, previous status : %0x\n",
142 reg_val);
143 pci_write_config(dev, ADF_200XX_PFIEERRUNCSTSR, reg_val, 4);
144 }
145
146 /* Get Accelerators and Accelerators Engines masks */
147 hw_data->accel_mask = hw_data->get_accel_mask(accel_dev);
148 hw_data->ae_mask = hw_data->get_ae_mask(accel_dev);
149 hw_data->admin_ae_mask = hw_data->ae_mask;
150
151 accel_pci_dev->sku = hw_data->get_sku(hw_data);
152 /* If the device has no acceleration engines then ignore it. */
153 if (!hw_data->accel_mask || !hw_data->ae_mask ||
154 (~hw_data->ae_mask & 0x01)) {
155 device_printf(dev, "No acceleration units found\n");
156 ret = ENXIO;
157 goto out_err;
158 }
159
160 /* Create device configuration table */
161 ret = adf_cfg_dev_add(accel_dev);
162 if (ret)
163 goto out_err;
164 ret = adf_clock_debugfs_add(accel_dev);
165 if (ret)
166 goto out_err;
167
168 pci_set_max_read_req(dev, 1024);
169
170 ret = bus_dma_tag_create(bus_get_dma_tag(dev),
171 1,
172 0,
173 BUS_SPACE_MAXADDR,
174 BUS_SPACE_MAXADDR,
175 NULL,
176 NULL,
177 BUS_SPACE_MAXSIZE,
178 /* BUS_SPACE_UNRESTRICTED */ 1,
179 BUS_SPACE_MAXSIZE,
180 0,
181 NULL,
182 NULL,
183 &accel_dev->dma_tag);
184 if (ret)
185 goto out_err;
186
187 if (hw_data->get_accel_cap) {
188 hw_data->accel_capabilities_mask =
189 hw_data->get_accel_cap(accel_dev);
190 }
191
192 /* Find and map all the device's BARS */
193 for (bar_nr = 0; i < ADF_PCI_MAX_BARS && bar_nr < PCIR_MAX_BAR_0;
194 bar_nr++) {
195 struct adf_bar *bar;
196
197 /*
198 * XXX: This isn't quite right as it will ignore a BAR
199 * that wasn't assigned a valid resource range by the
200 * firmware.
201 */
202 rid = PCIR_BAR(bar_nr);
203 if (bus_get_resource(dev, SYS_RES_MEMORY, rid, NULL, NULL) != 0)
204 continue;
205 bar = &accel_pci_dev->pci_bars[i++];
206 bar->virt_addr = bus_alloc_resource_any(dev,
207 SYS_RES_MEMORY,
208 &rid,
209 RF_ACTIVE);
210 if (!bar->virt_addr) {
211 device_printf(dev, "Failed to map BAR %d\n", bar_nr);
212 ret = ENXIO;
213 goto out_err;
214 }
215 bar->base_addr = rman_get_start(bar->virt_addr);
216 bar->size = rman_get_size(bar->virt_addr);
217 }
218 ret = pci_enable_busmaster(dev);
219 if (ret)
220 goto out_err;
221
222 adf_dbgfs_init(accel_dev);
223
224 if (!accel_dev->hw_device->config_device) {
225 ret = EFAULT;
226 goto out_err_disable;
227 }
228
229 ret = accel_dev->hw_device->config_device(accel_dev);
230 if (ret)
231 goto out_err_disable;
232
233 ret = adf_dev_init(accel_dev);
234 if (ret)
235 goto out_dev_shutdown;
236
237 ret = adf_dev_start(accel_dev);
238 if (ret)
239 goto out_dev_stop;
240
241 cfg_dev = accel_dev->cfg->dev;
242 adf_cfg_device_clear(cfg_dev, accel_dev);
243 free(cfg_dev, M_QAT);
244 accel_dev->cfg->dev = NULL;
245 return ret;
246 out_dev_stop:
247 adf_dev_stop(accel_dev);
248 out_dev_shutdown:
249 adf_dev_shutdown(accel_dev);
250 out_err_disable:
251 pci_disable_busmaster(dev);
252 out_err:
253 adf_cleanup_accel(accel_dev);
254 out_err_lock:
255 mutex_destroy(&accel_dev->lock);
256
257 return ret;
258 }
259
260 static int
adf_detach(device_t dev)261 adf_detach(device_t dev)
262 {
263 struct adf_accel_dev *accel_dev = device_get_softc(dev);
264
265 if (adf_dev_stop(accel_dev)) {
266 device_printf(dev, "Failed to stop QAT accel dev\n");
267 return EBUSY;
268 }
269
270 adf_dev_shutdown(accel_dev);
271
272 pci_disable_busmaster(dev);
273 adf_cleanup_accel(accel_dev);
274 mutex_destroy(&accel_dev->lock);
275
276 return 0;
277 }
278
279 static device_method_t adf_methods[] = { DEVMETHOD(device_probe, adf_probe),
280 DEVMETHOD(device_attach, adf_attach),
281 DEVMETHOD(device_detach, adf_detach),
282
283 DEVMETHOD_END };
284
285 static driver_t adf_driver = { "qat",
286 adf_methods,
287 sizeof(struct adf_accel_dev) };
288
289 DRIVER_MODULE_ORDERED(qat_200xx, pci, adf_driver, NULL, NULL, SI_ORDER_THIRD);
290 MODULE_VERSION(qat_200xx, 1);
291 MODULE_DEPEND(qat_200xx, qat_common, 1, 1, 1);
292 MODULE_DEPEND(qat_200xx, qat_api, 1, 1, 1);
293 MODULE_DEPEND(qat_200xx, linuxkpi, 1, 1, 1);
294