xref: /qemu/hw/ppc/pnv_occ.c (revision 06b40d250ecfa1633209c2e431a7a38acfd03a98)
1 /*
2  * QEMU PowerPC PowerNV Emulation of a few OCC related registers
3  *
4  * Copyright (c) 2015-2017, IBM Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License, version 2, as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, see <http://www.gnu.org/licenses/>.
17  */
18 
19 #include "qemu/osdep.h"
20 #include "target/ppc/cpu.h"
21 #include "qapi/error.h"
22 #include "qemu/log.h"
23 #include "qemu/module.h"
24 #include "hw/irq.h"
25 #include "hw/qdev-properties.h"
26 #include "hw/ppc/pnv.h"
27 #include "hw/ppc/pnv_chip.h"
28 #include "hw/ppc/pnv_xscom.h"
29 #include "hw/ppc/pnv_occ.h"
30 
31 #define P8_HOMER_OPAL_DATA_OFFSET    0x1F8000
32 #define P9_HOMER_OPAL_DATA_OFFSET    0x0E2000
33 
34 #define OCB_OCI_OCCMISC         0x4020
35 #define OCB_OCI_OCCMISC_AND     0x4021
36 #define OCB_OCI_OCCMISC_OR      0x4022
37 #define   OCCMISC_PSI_IRQ       PPC_BIT(0)
38 #define   OCCMISC_IRQ_SHMEM     PPC_BIT(3)
39 
40 /* OCC sensors */
41 #define OCC_SENSOR_DATA_BLOCK_OFFSET          0x0000
42 #define OCC_SENSOR_DATA_VALID                 0x0001
43 #define OCC_SENSOR_DATA_VERSION               0x0002
44 #define OCC_SENSOR_DATA_READING_VERSION       0x0004
45 #define OCC_SENSOR_DATA_NR_SENSORS            0x0008
46 #define OCC_SENSOR_DATA_NAMES_OFFSET          0x0010
47 #define OCC_SENSOR_DATA_READING_PING_OFFSET   0x0014
48 #define OCC_SENSOR_DATA_READING_PONG_OFFSET   0x000c
49 #define OCC_SENSOR_DATA_NAME_LENGTH           0x000d
50 #define OCC_SENSOR_NAME_STRUCTURE_TYPE        0x0023
51 #define OCC_SENSOR_LOC_CORE                   0x0022
52 #define OCC_SENSOR_LOC_GPU                    0x0020
53 #define OCC_SENSOR_TYPE_POWER                 0x0003
54 #define OCC_SENSOR_NAME                       0x0005
55 #define HWMON_SENSORS_MASK                    0x001e
56 
pnv_occ_set_misc(PnvOCC * occ,uint64_t val)57 static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val)
58 {
59     val &= PPC_BITMASK(0, 18); /* Mask out unimplemented bits */
60 
61     occ->occmisc = val;
62 
63     /*
64      * OCCMISC IRQ bit triggers the interrupt on a 0->1 edge, but not clear
65      * how that is handled in PSI so it is level-triggered here, which is not
66      * really correct (but skiboot is okay with it).
67      */
68     qemu_set_irq(occ->psi_irq, !!(val & OCCMISC_PSI_IRQ));
69 }
70 
pnv_occ_raise_msg_irq(PnvOCC * occ)71 static void pnv_occ_raise_msg_irq(PnvOCC *occ)
72 {
73     pnv_occ_set_misc(occ, occ->occmisc | OCCMISC_PSI_IRQ | OCCMISC_IRQ_SHMEM);
74 }
75 
pnv_occ_power8_xscom_read(void * opaque,hwaddr addr,unsigned size)76 static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr,
77                                           unsigned size)
78 {
79     PnvOCC *occ = PNV_OCC(opaque);
80     uint32_t offset = addr >> 3;
81     uint64_t val = 0;
82 
83     switch (offset) {
84     case OCB_OCI_OCCMISC:
85         val = occ->occmisc;
86         break;
87     default:
88         qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
89                       HWADDR_PRIx "\n", addr >> 3);
90     }
91     return val;
92 }
93 
pnv_occ_power8_xscom_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)94 static void pnv_occ_power8_xscom_write(void *opaque, hwaddr addr,
95                                        uint64_t val, unsigned size)
96 {
97     PnvOCC *occ = PNV_OCC(opaque);
98     uint32_t offset = addr >> 3;
99 
100     switch (offset) {
101     case OCB_OCI_OCCMISC_AND:
102         pnv_occ_set_misc(occ, occ->occmisc & val);
103         break;
104     case OCB_OCI_OCCMISC_OR:
105         pnv_occ_set_misc(occ, occ->occmisc | val);
106         break;
107     case OCB_OCI_OCCMISC:
108         pnv_occ_set_misc(occ, val);
109         break;
110     default:
111         qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
112                       HWADDR_PRIx "\n", addr >> 3);
113     }
114 }
115 
pnv_occ_common_area_read(void * opaque,hwaddr addr,unsigned width)116 static uint64_t pnv_occ_common_area_read(void *opaque, hwaddr addr,
117                                          unsigned width)
118 {
119     switch (addr) {
120     /*
121      * occ-sensor sanity check that asserts the sensor
122      * header block
123      */
124     case OCC_SENSOR_DATA_BLOCK_OFFSET:
125     case OCC_SENSOR_DATA_VALID:
126     case OCC_SENSOR_DATA_VERSION:
127     case OCC_SENSOR_DATA_READING_VERSION:
128     case OCC_SENSOR_DATA_NR_SENSORS:
129     case OCC_SENSOR_DATA_NAMES_OFFSET:
130     case OCC_SENSOR_DATA_READING_PING_OFFSET:
131     case OCC_SENSOR_DATA_READING_PONG_OFFSET:
132     case OCC_SENSOR_NAME_STRUCTURE_TYPE:
133         return 1;
134     case OCC_SENSOR_DATA_NAME_LENGTH:
135         return 0x30;
136     case OCC_SENSOR_LOC_CORE:
137         return 0x0040;
138     case OCC_SENSOR_TYPE_POWER:
139         return 0x0080;
140     case OCC_SENSOR_NAME:
141         return 0x1000;
142     case HWMON_SENSORS_MASK:
143     case OCC_SENSOR_LOC_GPU:
144         return 0x8e00;
145     }
146     return 0;
147 }
148 
pnv_occ_common_area_write(void * opaque,hwaddr addr,uint64_t val,unsigned width)149 static void pnv_occ_common_area_write(void *opaque, hwaddr addr,
150                                              uint64_t val, unsigned width)
151 {
152     /* callback function defined to occ common area write */
153 }
154 
155 static const MemoryRegionOps pnv_occ_power8_xscom_ops = {
156     .read = pnv_occ_power8_xscom_read,
157     .write = pnv_occ_power8_xscom_write,
158     .valid.min_access_size = 8,
159     .valid.max_access_size = 8,
160     .impl.min_access_size = 8,
161     .impl.max_access_size = 8,
162     .endianness = DEVICE_BIG_ENDIAN,
163 };
164 
165 const MemoryRegionOps pnv_occ_sram_ops = {
166     .read = pnv_occ_common_area_read,
167     .write = pnv_occ_common_area_write,
168     .valid.min_access_size = 1,
169     .valid.max_access_size = 8,
170     .impl.min_access_size = 1,
171     .impl.max_access_size = 8,
172     .endianness = DEVICE_BIG_ENDIAN,
173 };
174 
pnv_occ_power8_class_init(ObjectClass * klass,const void * data)175 static void pnv_occ_power8_class_init(ObjectClass *klass, const void *data)
176 {
177     PnvOCCClass *poc = PNV_OCC_CLASS(klass);
178     DeviceClass *dc = DEVICE_CLASS(klass);
179 
180     dc->desc = "PowerNV OCC Controller (POWER8)";
181     poc->opal_shared_memory_offset = P8_HOMER_OPAL_DATA_OFFSET;
182     poc->opal_shared_memory_version = 0x02;
183     poc->xscom_size = PNV_XSCOM_OCC_SIZE;
184     poc->xscom_ops = &pnv_occ_power8_xscom_ops;
185 }
186 
187 static const TypeInfo pnv_occ_power8_type_info = {
188     .name          = TYPE_PNV8_OCC,
189     .parent        = TYPE_PNV_OCC,
190     .instance_size = sizeof(PnvOCC),
191     .class_init    = pnv_occ_power8_class_init,
192 };
193 
194 #define P9_OCB_OCI_OCCMISC              0x6080
195 #define P9_OCB_OCI_OCCMISC_CLEAR        0x6081
196 #define P9_OCB_OCI_OCCMISC_OR           0x6082
197 
198 
pnv_occ_power9_xscom_read(void * opaque,hwaddr addr,unsigned size)199 static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr,
200                                           unsigned size)
201 {
202     PnvOCC *occ = PNV_OCC(opaque);
203     uint32_t offset = addr >> 3;
204     uint64_t val = 0;
205 
206     switch (offset) {
207     case P9_OCB_OCI_OCCMISC:
208         val = occ->occmisc;
209         break;
210     default:
211         qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
212                       HWADDR_PRIx "\n", addr >> 3);
213     }
214     return val;
215 }
216 
pnv_occ_power9_xscom_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)217 static void pnv_occ_power9_xscom_write(void *opaque, hwaddr addr,
218                                        uint64_t val, unsigned size)
219 {
220     PnvOCC *occ = PNV_OCC(opaque);
221     uint32_t offset = addr >> 3;
222 
223     switch (offset) {
224     case P9_OCB_OCI_OCCMISC_CLEAR:
225         pnv_occ_set_misc(occ, 0);
226         break;
227     case P9_OCB_OCI_OCCMISC_OR:
228         pnv_occ_set_misc(occ, occ->occmisc | val);
229         break;
230     case P9_OCB_OCI_OCCMISC:
231         pnv_occ_set_misc(occ, val);
232        break;
233     default:
234         qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
235                       HWADDR_PRIx "\n", addr >> 3);
236     }
237 }
238 
239 static const MemoryRegionOps pnv_occ_power9_xscom_ops = {
240     .read = pnv_occ_power9_xscom_read,
241     .write = pnv_occ_power9_xscom_write,
242     .valid.min_access_size = 8,
243     .valid.max_access_size = 8,
244     .impl.min_access_size = 8,
245     .impl.max_access_size = 8,
246     .endianness = DEVICE_BIG_ENDIAN,
247 };
248 
pnv_occ_power9_class_init(ObjectClass * klass,const void * data)249 static void pnv_occ_power9_class_init(ObjectClass *klass, const void *data)
250 {
251     PnvOCCClass *poc = PNV_OCC_CLASS(klass);
252     DeviceClass *dc = DEVICE_CLASS(klass);
253 
254     dc->desc = "PowerNV OCC Controller (POWER9)";
255     poc->opal_shared_memory_offset = P9_HOMER_OPAL_DATA_OFFSET;
256     poc->opal_shared_memory_version = 0x90;
257     poc->xscom_size = PNV9_XSCOM_OCC_SIZE;
258     poc->xscom_ops = &pnv_occ_power9_xscom_ops;
259     assert(!dc->user_creatable);
260 }
261 
262 static const TypeInfo pnv_occ_power9_type_info = {
263     .name          = TYPE_PNV9_OCC,
264     .parent        = TYPE_PNV_OCC,
265     .instance_size = sizeof(PnvOCC),
266     .class_init    = pnv_occ_power9_class_init,
267 };
268 
pnv_occ_power10_class_init(ObjectClass * klass,const void * data)269 static void pnv_occ_power10_class_init(ObjectClass *klass, const void *data)
270 {
271     PnvOCCClass *poc = PNV_OCC_CLASS(klass);
272     DeviceClass *dc = DEVICE_CLASS(klass);
273 
274     dc->desc = "PowerNV OCC Controller (POWER10)";
275     poc->opal_shared_memory_offset = P9_HOMER_OPAL_DATA_OFFSET;
276     poc->opal_shared_memory_version = 0xA0;
277     poc->xscom_size = PNV9_XSCOM_OCC_SIZE;
278     poc->xscom_ops = &pnv_occ_power9_xscom_ops;
279     assert(!dc->user_creatable);
280 }
281 
282 static const TypeInfo pnv_occ_power10_type_info = {
283     .name          = TYPE_PNV10_OCC,
284     .parent        = TYPE_PNV_OCC,
285     .class_init    = pnv_occ_power10_class_init,
286 };
287 
288 static bool occ_init_homer_memory(PnvOCC *occ, Error **errp);
289 static bool occ_model_tick(PnvOCC *occ);
290 
291 /* Relatively arbitrary */
292 #define OCC_POLL_MS 100
293 
occ_state_machine_timer(void * opaque)294 static void occ_state_machine_timer(void *opaque)
295 {
296     PnvOCC *occ = opaque;
297     uint64_t next = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + OCC_POLL_MS;
298 
299     if (occ_model_tick(occ)) {
300         timer_mod(&occ->state_machine_timer, next);
301     }
302 }
303 
pnv_occ_realize(DeviceState * dev,Error ** errp)304 static void pnv_occ_realize(DeviceState *dev, Error **errp)
305 {
306     PnvOCC *occ = PNV_OCC(dev);
307     PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
308     PnvHomer *homer = occ->homer;
309 
310     assert(homer);
311 
312     if (!occ_init_homer_memory(occ, errp)) {
313         return;
314     }
315 
316     occ->occmisc = 0;
317 
318     /* XScom region for OCC registers */
319     pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), poc->xscom_ops,
320                           occ, "xscom-occ", poc->xscom_size);
321 
322     /* OCC common area mmio region for OCC SRAM registers */
323     memory_region_init_io(&occ->sram_regs, OBJECT(dev), &pnv_occ_sram_ops,
324                           occ, "occ-common-area",
325                           PNV_OCC_SENSOR_DATA_BLOCK_SIZE);
326 
327     qdev_init_gpio_out(dev, &occ->psi_irq, 1);
328 
329     timer_init_ms(&occ->state_machine_timer, QEMU_CLOCK_VIRTUAL,
330                   occ_state_machine_timer, occ);
331     timer_mod(&occ->state_machine_timer, OCC_POLL_MS);
332 }
333 
334 static const Property pnv_occ_properties[] = {
335     DEFINE_PROP_LINK("homer", PnvOCC, homer, TYPE_PNV_HOMER, PnvHomer *),
336 };
337 
pnv_occ_class_init(ObjectClass * klass,const void * data)338 static void pnv_occ_class_init(ObjectClass *klass, const void *data)
339 {
340     DeviceClass *dc = DEVICE_CLASS(klass);
341 
342     dc->realize = pnv_occ_realize;
343     device_class_set_props(dc, pnv_occ_properties);
344     dc->user_creatable = false;
345 }
346 
347 static const TypeInfo pnv_occ_type_info = {
348     .name          = TYPE_PNV_OCC,
349     .parent        = TYPE_DEVICE,
350     .instance_size = sizeof(PnvOCC),
351     .class_init    = pnv_occ_class_init,
352     .class_size    = sizeof(PnvOCCClass),
353     .abstract      = true,
354 };
355 
pnv_occ_register_types(void)356 static void pnv_occ_register_types(void)
357 {
358     type_register_static(&pnv_occ_type_info);
359     type_register_static(&pnv_occ_power8_type_info);
360     type_register_static(&pnv_occ_power9_type_info);
361     type_register_static(&pnv_occ_power10_type_info);
362 }
363 
364 type_init(pnv_occ_register_types);
365 
366 /*
367  * From skiboot/hw/occ.c with following changes:
368  * - tab to space conversion
369  * - Type conversions u8->uint8_t s8->int8_t __be16->uint16_t etc
370  * - __packed -> QEMU_PACKED
371  */
372 /* OCC Communication Area for PStates */
373 
374 #define OPAL_DYNAMIC_DATA_OFFSET        0x0B80
375 /* relative to HOMER_OPAL_DATA_OFFSET */
376 
377 #define MAX_PSTATES                     256
378 #define MAX_P8_CORES                    12
379 #define MAX_P9_CORES                    24
380 #define MAX_P10_CORES                   32
381 
382 #define MAX_OPAL_CMD_DATA_LENGTH        4090
383 #define MAX_OCC_RSP_DATA_LENGTH         8698
384 
385 #define P8_PIR_CORE_MASK                0xFFF8
386 #define P9_PIR_QUAD_MASK                0xFFF0
387 #define P10_PIR_CHIP_MASK               0x0000
388 #define FREQ_MAX_IN_DOMAIN              0
389 #define FREQ_MOST_RECENTLY_SET          1
390 
391 /**
392  * OCC-OPAL Shared Memory Region
393  *
394  * Reference document :
395  * https://github.com/open-power/docs/blob/master/occ/OCC_OpenPwr_FW_Interfaces.pdf
396  *
397  * Supported layout versions:
398  * - 0x01, 0x02 : P8
399  * https://github.com/open-power/occ/blob/master_p8/src/occ/proc/proc_pstate.h
400  *
401  * - 0x90 : P9
402  * https://github.com/open-power/occ/blob/master/src/occ_405/proc/proc_pstate.h
403  *   In 0x90 the data is separated into :-
404  *   -- Static Data (struct occ_pstate_table): Data is written once by OCC
405  *   -- Dynamic Data (struct occ_dynamic_data): Data is updated at runtime
406  *
407  * struct occ_pstate_table -    Pstate table layout
408  * @valid:                      Indicates if data is valid
409  * @version:                    Layout version [Major/Minor]
410  * @v2.throttle:                Reason for limiting the max pstate
411  * @v9.occ_role:                OCC role (Master/Slave)
412  * @v#.pstate_min:              Minimum pstate ever allowed
413  * @v#.pstate_nom:              Nominal pstate
414  * @v#.pstate_turbo:            Maximum turbo pstate
415  * @v#.pstate_ultra_turbo:      Maximum ultra turbo pstate and the maximum
416  *                              pstate ever allowed
417  * @v#.pstates:                 Pstate-id and frequency list from Pmax to Pmin
418  * @v#.pstates.id:              Pstate-id
419  * @v#.pstates.flags:           Pstate-flag(reserved)
420  * @v2.pstates.vdd:             Voltage Identifier
421  * @v2.pstates.vcs:             Voltage Identifier
422  * @v#.pstates.freq_khz:        Frequency in KHz
423  * @v#.core_max[1..N]:          Max pstate with N active cores
424  * @spare/reserved/pad:         Unused data
425  */
426 struct occ_pstate_table {
427     uint8_t valid;
428     uint8_t version;
429     union QEMU_PACKED {
430         struct QEMU_PACKED { /* Version 0x01 and 0x02 */
431             uint8_t throttle;
432             int8_t pstate_min;
433             int8_t pstate_nom;
434             int8_t pstate_turbo;
435             int8_t pstate_ultra_turbo;
436             uint8_t spare;
437             uint64_t reserved;
438             struct QEMU_PACKED {
439                 int8_t id;
440                 uint8_t flags;
441                 uint8_t vdd;
442                 uint8_t vcs;
443                 uint32_t freq_khz;
444             } pstates[MAX_PSTATES];
445             int8_t core_max[MAX_P8_CORES];
446             uint8_t pad[100];
447         } v2;
448         struct QEMU_PACKED { /* Version 0x90 */
449             uint8_t occ_role;
450             uint8_t pstate_min;
451             uint8_t pstate_nom;
452             uint8_t pstate_turbo;
453             uint8_t pstate_ultra_turbo;
454             uint8_t spare;
455             uint64_t reserved1;
456             uint64_t reserved2;
457             struct QEMU_PACKED {
458                 uint8_t id;
459                 uint8_t flags;
460                 uint16_t reserved;
461                 uint32_t freq_khz;
462             } pstates[MAX_PSTATES];
463             uint8_t core_max[MAX_P9_CORES];
464             uint8_t pad[56];
465         } v9;
466         struct QEMU_PACKED { /* Version 0xA0 */
467             uint8_t occ_role;
468             uint8_t pstate_min;
469             uint8_t pstate_fixed_freq;
470             uint8_t pstate_base;
471             uint8_t pstate_ultra_turbo;
472             uint8_t pstate_fmax;
473             uint8_t minor;
474             uint8_t pstate_bottom_throttle;
475             uint8_t spare;
476             uint8_t spare1;
477             uint32_t reserved_32;
478             uint64_t reserved_64;
479             struct QEMU_PACKED {
480                 uint8_t id;
481                 uint8_t valid;
482                 uint16_t reserved;
483                 uint32_t freq_khz;
484             } pstates[MAX_PSTATES];
485             uint8_t core_max[MAX_P10_CORES];
486             uint8_t pad[48];
487         } v10;
488     };
489 } QEMU_PACKED;
490 
491 /**
492  * OPAL-OCC Command Response Interface
493  *
494  * OPAL-OCC Command Buffer
495  *
496  * ---------------------------------------------------------------------
497  * | OPAL  |  Cmd    | OPAL |          | Cmd Data | Cmd Data | OPAL    |
498  * | Cmd   | Request | OCC  | Reserved | Length   | Length   | Cmd     |
499  * | Flags |   ID    | Cmd  |          | (MSB)    | (LSB)    | Data... |
500  * ---------------------------------------------------------------------
501  * |  ….OPAL Command Data up to max of Cmd Data Length 4090 bytes      |
502  * |                                                                   |
503  * ---------------------------------------------------------------------
504  *
505  * OPAL Command Flag
506  *
507  * -----------------------------------------------------------------
508  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
509  * | (msb) |       |       |       |       |       |       | (lsb) |
510  * -----------------------------------------------------------------
511  * |Cmd    |       |       |       |       |       |       |       |
512  * |Ready  |       |       |       |       |       |       |       |
513  * -----------------------------------------------------------------
514  *
515  * struct opal_command_buffer - Defines the layout of OPAL command buffer
516  * @flag:                       Provides general status of the command
517  * @request_id:                 Token to identify request
518  * @cmd:                        Command sent
519  * @data_size:                  Command data length
520  * @data:                       Command specific data
521  * @spare:                      Unused byte
522  */
523 struct opal_command_buffer {
524     uint8_t flag;
525     uint8_t request_id;
526     uint8_t cmd;
527     uint8_t spare;
528     uint16_t data_size;
529     uint8_t data[MAX_OPAL_CMD_DATA_LENGTH];
530 } QEMU_PACKED;
531 
532 /**
533  * OPAL-OCC Response Buffer
534  *
535  * ---------------------------------------------------------------------
536  * | OCC   |  Cmd    | OPAL | Response | Rsp Data | Rsp Data | OPAL    |
537  * | Rsp   | Request | OCC  |  Status  | Length   | Length   | Rsp     |
538  * | Flags |   ID    | Cmd  |          | (MSB)    | (LSB)    | Data... |
539  * ---------------------------------------------------------------------
540  * |  ….OPAL Response Data up to max of Rsp Data Length 8698 bytes     |
541  * |                                                                   |
542  * ---------------------------------------------------------------------
543  *
544  * OCC Response Flag
545  *
546  * -----------------------------------------------------------------
547  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
548  * | (msb) |       |       |       |       |       |       | (lsb) |
549  * -----------------------------------------------------------------
550  * |       |       |       |       |       |       |OCC in  | Rsp  |
551  * |       |       |       |       |       |       |progress|Ready |
552  * -----------------------------------------------------------------
553  *
554  * struct occ_response_buffer - Defines the layout of OCC response buffer
555  * @flag:                       Provides general status of the response
556  * @request_id:                 Token to identify request
557  * @cmd:                        Command requested
558  * @status:                     Indicates success/failure status of
559  *                              the command
560  * @data_size:                  Response data length
561  * @data:                       Response specific data
562  */
563 struct occ_response_buffer {
564     uint8_t flag;
565     uint8_t request_id;
566     uint8_t cmd;
567     uint8_t status;
568     uint16_t data_size;
569     uint8_t data[MAX_OCC_RSP_DATA_LENGTH];
570 } QEMU_PACKED;
571 
572 /**
573  * OCC-OPAL Shared Memory Interface Dynamic Data Vx90
574  *
575  * struct occ_dynamic_data -    Contains runtime attributes
576  * @occ_state:                  Current state of OCC
577  * @major_version:              Major version number
578  * @minor_version:              Minor version number (backwards compatible)
579  *                              Version 1 indicates GPU presence populated
580  * @gpus_present:               Bitmask of GPUs present (on systems where GPU
581  *                              presence is detected through APSS)
582  * @cpu_throttle:               Reason for limiting the max pstate
583  * @mem_throttle:               Reason for throttling memory
584  * @quick_pwr_drop:             Indicates if QPD is asserted
585  * @pwr_shifting_ratio:         Indicates the current percentage of power to
586  *                              take away from the CPU vs GPU when shifting
587  *                              power to maintain a power cap. Value of 100
588  *                              means take all power from CPU.
589  * @pwr_cap_type:               Indicates type of power cap in effect
590  * @hard_min_pwr_cap:           Hard minimum system power cap in Watts.
591  *                              Guaranteed unless hardware failure
592  * @max_pwr_cap:                Maximum allowed system power cap in Watts
593  * @cur_pwr_cap:                Current system power cap
594  * @soft_min_pwr_cap:           Soft powercap minimum. OCC may or may not be
595  *                              able to maintain this
596  * @spare/reserved:             Unused data
597  * @cmd:                        Opal Command Buffer
598  * @rsp:                        OCC Response Buffer
599  */
600 struct occ_dynamic_data {
601     uint8_t occ_state;
602     uint8_t major_version;
603     uint8_t minor_version;
604     uint8_t gpus_present;
605     union QEMU_PACKED {
606         struct QEMU_PACKED { /* Version 0x90 */
607             uint8_t spare1;
608         } v9;
609         struct QEMU_PACKED { /* Version 0xA0 */
610             uint8_t wof_enabled;
611         } v10;
612     };
613     uint8_t cpu_throttle;
614     uint8_t mem_throttle;
615     uint8_t quick_pwr_drop;
616     uint8_t pwr_shifting_ratio;
617     uint8_t pwr_cap_type;
618     uint16_t hard_min_pwr_cap;
619     uint16_t max_pwr_cap;
620     uint16_t cur_pwr_cap;
621     uint16_t soft_min_pwr_cap;
622     uint8_t pad[110];
623     struct opal_command_buffer cmd;
624     struct occ_response_buffer rsp;
625 } QEMU_PACKED;
626 
627 enum occ_response_status {
628     OCC_RSP_SUCCESS                 = 0x00,
629     OCC_RSP_INVALID_COMMAND         = 0x11,
630     OCC_RSP_INVALID_CMD_DATA_LENGTH = 0x12,
631     OCC_RSP_INVALID_DATA            = 0x13,
632     OCC_RSP_INTERNAL_ERROR          = 0x15,
633 };
634 
635 #define OCC_ROLE_SLAVE                  0x00
636 #define OCC_ROLE_MASTER                 0x01
637 
638 #define OCC_FLAG_RSP_READY              0x01
639 #define OCC_FLAG_CMD_IN_PROGRESS        0x02
640 #define OPAL_FLAG_CMD_READY             0x80
641 
642 #define PCAP_MAX_POWER_W                100
643 #define PCAP_SOFT_MIN_POWER_W            20
644 #define PCAP_HARD_MIN_POWER_W            10
645 
occ_write_static_data(PnvOCC * occ,struct occ_pstate_table * static_data,Error ** errp)646 static bool occ_write_static_data(PnvOCC *occ,
647                                  struct occ_pstate_table *static_data,
648                                  Error **errp)
649 {
650     PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
651     PnvHomer *homer = occ->homer;
652     hwaddr static_addr = homer->base + poc->opal_shared_memory_offset;
653     MemTxResult ret;
654 
655     ret = address_space_write(&address_space_memory, static_addr,
656                              MEMTXATTRS_UNSPECIFIED, static_data,
657                              sizeof(*static_data));
658     if (ret != MEMTX_OK) {
659         error_setg(errp, "OCC: cannot write OCC-OPAL static data");
660         return false;
661     }
662 
663     return true;
664 }
665 
occ_read_dynamic_data(PnvOCC * occ,struct occ_dynamic_data * dynamic_data,Error ** errp)666 static bool occ_read_dynamic_data(PnvOCC *occ,
667                                   struct occ_dynamic_data *dynamic_data,
668                                   Error **errp)
669 {
670     PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
671     PnvHomer *homer = occ->homer;
672     hwaddr static_addr = homer->base + poc->opal_shared_memory_offset;
673     hwaddr dynamic_addr = static_addr + OPAL_DYNAMIC_DATA_OFFSET;
674     MemTxResult ret;
675 
676     ret = address_space_read(&address_space_memory, dynamic_addr,
677                              MEMTXATTRS_UNSPECIFIED, dynamic_data,
678                              sizeof(*dynamic_data));
679     if (ret != MEMTX_OK) {
680         error_setg(errp, "OCC: cannot read OCC-OPAL dynamic data");
681         return false;
682     }
683 
684     return true;
685 }
686 
occ_write_dynamic_data(PnvOCC * occ,struct occ_dynamic_data * dynamic_data,Error ** errp)687 static bool occ_write_dynamic_data(PnvOCC *occ,
688                                   struct occ_dynamic_data *dynamic_data,
689                                   Error **errp)
690 {
691     PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
692     PnvHomer *homer = occ->homer;
693     hwaddr static_addr = homer->base + poc->opal_shared_memory_offset;
694     hwaddr dynamic_addr = static_addr + OPAL_DYNAMIC_DATA_OFFSET;
695     MemTxResult ret;
696 
697     ret = address_space_write(&address_space_memory, dynamic_addr,
698                              MEMTXATTRS_UNSPECIFIED, dynamic_data,
699                              sizeof(*dynamic_data));
700     if (ret != MEMTX_OK) {
701         error_setg(errp, "OCC: cannot write OCC-OPAL dynamic data");
702         return false;
703     }
704 
705     return true;
706 }
707 
occ_opal_send_response(PnvOCC * occ,struct occ_dynamic_data * dynamic_data,enum occ_response_status status,uint8_t * data,uint16_t datalen)708 static bool occ_opal_send_response(PnvOCC *occ,
709                                    struct occ_dynamic_data *dynamic_data,
710                                    enum occ_response_status status,
711                                    uint8_t *data, uint16_t datalen)
712 {
713     struct opal_command_buffer *cmd = &dynamic_data->cmd;
714     struct occ_response_buffer *rsp = &dynamic_data->rsp;
715 
716     rsp->request_id = cmd->request_id;
717     rsp->cmd = cmd->cmd;
718     rsp->status = status;
719     rsp->data_size = cpu_to_be16(datalen);
720     if (datalen) {
721         memcpy(rsp->data, data, datalen);
722     }
723     if (!occ_write_dynamic_data(occ, dynamic_data, NULL)) {
724         return false;
725     }
726     /* Would be a memory barrier here */
727     rsp->flag = OCC_FLAG_RSP_READY;
728     cmd->flag = 0;
729     if (!occ_write_dynamic_data(occ, dynamic_data, NULL)) {
730         return false;
731     }
732 
733     pnv_occ_raise_msg_irq(occ);
734 
735     return true;
736 }
737 
738 /* Returns error status */
occ_opal_process_command(PnvOCC * occ,struct occ_dynamic_data * dynamic_data)739 static bool occ_opal_process_command(PnvOCC *occ,
740                                      struct occ_dynamic_data *dynamic_data)
741 {
742     struct opal_command_buffer *cmd = &dynamic_data->cmd;
743     struct occ_response_buffer *rsp = &dynamic_data->rsp;
744 
745     if (rsp->flag == 0) {
746         /* Spend one "tick" in the in-progress state */
747         rsp->flag = OCC_FLAG_CMD_IN_PROGRESS;
748         return occ_write_dynamic_data(occ, dynamic_data, NULL);
749     } else if (rsp->flag != OCC_FLAG_CMD_IN_PROGRESS) {
750         return occ_opal_send_response(occ, dynamic_data,
751                                       OCC_RSP_INTERNAL_ERROR,
752                                       NULL, 0);
753     }
754 
755     switch (cmd->cmd) {
756     case 0xD1: { /* SET_POWER_CAP */
757         uint16_t data;
758         if (be16_to_cpu(cmd->data_size) != 2) {
759             return occ_opal_send_response(occ, dynamic_data,
760                                           OCC_RSP_INVALID_CMD_DATA_LENGTH,
761                                           (uint8_t *)&dynamic_data->cur_pwr_cap,
762                                           2);
763         }
764         data = be16_to_cpu(*(uint16_t *)cmd->data);
765         if (data == 0) { /* clear power cap */
766             dynamic_data->pwr_cap_type = 0x00; /* none */
767             data = PCAP_MAX_POWER_W;
768         } else {
769             dynamic_data->pwr_cap_type = 0x02; /* user set in-band */
770             if (data < PCAP_HARD_MIN_POWER_W) {
771                 data = PCAP_HARD_MIN_POWER_W;
772             } else if (data > PCAP_MAX_POWER_W) {
773                 data = PCAP_MAX_POWER_W;
774             }
775         }
776         dynamic_data->cur_pwr_cap = cpu_to_be16(data);
777         return occ_opal_send_response(occ, dynamic_data,
778                                       OCC_RSP_SUCCESS,
779                                       (uint8_t *)&dynamic_data->cur_pwr_cap, 2);
780     }
781 
782     default:
783         return occ_opal_send_response(occ, dynamic_data,
784                                       OCC_RSP_INVALID_COMMAND,
785                                       NULL, 0);
786     }
787     g_assert_not_reached();
788 }
789 
occ_model_tick(PnvOCC * occ)790 static bool occ_model_tick(PnvOCC *occ)
791 {
792     struct occ_dynamic_data dynamic_data;
793 
794     if (!occ_read_dynamic_data(occ, &dynamic_data, NULL)) {
795         /* Can't move OCC state field to safe because we can't map it! */
796         qemu_log("OCC: failed to read HOMER data, shutting down OCC\n");
797         return false;
798     }
799     if (dynamic_data.cmd.flag == OPAL_FLAG_CMD_READY) {
800         if (!occ_opal_process_command(occ, &dynamic_data)) {
801             qemu_log("OCC: failed to write HOMER data, shutting down OCC\n");
802             return false;
803         }
804     }
805 
806     return true;
807 }
808 
occ_init_homer_memory(PnvOCC * occ,Error ** errp)809 static bool occ_init_homer_memory(PnvOCC *occ, Error **errp)
810 {
811     PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
812     PnvHomer *homer = occ->homer;
813     PnvChip *chip = homer->chip;
814     struct occ_pstate_table static_data;
815     struct occ_dynamic_data dynamic_data;
816     int i;
817 
818     memset(&static_data, 0, sizeof(static_data));
819     static_data.valid = 1;
820     static_data.version = poc->opal_shared_memory_version;
821     switch (poc->opal_shared_memory_version) {
822     case 0x02:
823         static_data.v2.throttle = 0;
824         static_data.v2.pstate_min = -2;
825         static_data.v2.pstate_nom = -1;
826         static_data.v2.pstate_turbo = -1;
827         static_data.v2.pstate_ultra_turbo = 0;
828         static_data.v2.pstates[0].id = 0;
829         static_data.v2.pstates[1].freq_khz = cpu_to_be32(4000000);
830         static_data.v2.pstates[1].id = -1;
831         static_data.v2.pstates[1].freq_khz = cpu_to_be32(3000000);
832         static_data.v2.pstates[2].id = -2;
833         static_data.v2.pstates[2].freq_khz = cpu_to_be32(2000000);
834         for (i = 0; i < chip->nr_cores; i++) {
835             static_data.v2.core_max[i] = 1;
836         }
837         break;
838     case 0x90:
839         if (chip->chip_id == 0) {
840             static_data.v9.occ_role = OCC_ROLE_MASTER;
841         } else {
842             static_data.v9.occ_role = OCC_ROLE_SLAVE;
843         }
844         static_data.v9.pstate_min = 2;
845         static_data.v9.pstate_nom = 1;
846         static_data.v9.pstate_turbo = 1;
847         static_data.v9.pstate_ultra_turbo = 0;
848         static_data.v9.pstates[0].id = 0;
849         static_data.v9.pstates[0].freq_khz = cpu_to_be32(4000000);
850         static_data.v9.pstates[1].id = 1;
851         static_data.v9.pstates[1].freq_khz = cpu_to_be32(3000000);
852         static_data.v9.pstates[2].id = 2;
853         static_data.v9.pstates[2].freq_khz = cpu_to_be32(2000000);
854         for (i = 0; i < chip->nr_cores; i++) {
855             static_data.v9.core_max[i] = 1;
856         }
857         break;
858     case 0xA0:
859         if (chip->chip_id == 0) {
860             static_data.v10.occ_role = OCC_ROLE_MASTER;
861         } else {
862             static_data.v10.occ_role = OCC_ROLE_SLAVE;
863         }
864         static_data.v10.pstate_min = 4;
865         static_data.v10.pstate_fixed_freq = 3;
866         static_data.v10.pstate_base = 2;
867         static_data.v10.pstate_ultra_turbo = 0;
868         static_data.v10.pstate_fmax = 1;
869         static_data.v10.minor = 0x01;
870         static_data.v10.pstates[0].valid = 1;
871         static_data.v10.pstates[0].id = 0;
872         static_data.v10.pstates[0].freq_khz = cpu_to_be32(4200000);
873         static_data.v10.pstates[1].valid = 1;
874         static_data.v10.pstates[1].id = 1;
875         static_data.v10.pstates[1].freq_khz = cpu_to_be32(4000000);
876         static_data.v10.pstates[2].valid = 1;
877         static_data.v10.pstates[2].id = 2;
878         static_data.v10.pstates[2].freq_khz = cpu_to_be32(3800000);
879         static_data.v10.pstates[3].valid = 1;
880         static_data.v10.pstates[3].id = 3;
881         static_data.v10.pstates[3].freq_khz = cpu_to_be32(3000000);
882         static_data.v10.pstates[4].valid = 1;
883         static_data.v10.pstates[4].id = 4;
884         static_data.v10.pstates[4].freq_khz = cpu_to_be32(2000000);
885         for (i = 0; i < chip->nr_cores; i++) {
886             static_data.v10.core_max[i] = 1;
887         }
888         break;
889     default:
890         g_assert_not_reached();
891     }
892     if (!occ_write_static_data(occ, &static_data, errp)) {
893         return false;
894     }
895 
896     memset(&dynamic_data, 0, sizeof(dynamic_data));
897     dynamic_data.occ_state = 0x3; /* active */
898     dynamic_data.major_version = 0x0;
899     dynamic_data.hard_min_pwr_cap = cpu_to_be16(PCAP_HARD_MIN_POWER_W);
900     dynamic_data.max_pwr_cap = cpu_to_be16(PCAP_MAX_POWER_W);
901     dynamic_data.cur_pwr_cap = cpu_to_be16(PCAP_MAX_POWER_W);
902     dynamic_data.soft_min_pwr_cap = cpu_to_be16(PCAP_SOFT_MIN_POWER_W);
903     switch (poc->opal_shared_memory_version) {
904     case 0xA0:
905         dynamic_data.minor_version = 0x1;
906         dynamic_data.v10.wof_enabled = 0x1;
907         break;
908     case 0x90:
909         dynamic_data.minor_version = 0x1;
910         break;
911     case 0x02:
912         dynamic_data.minor_version = 0x0;
913         break;
914     default:
915         g_assert_not_reached();
916     }
917     if (!occ_write_dynamic_data(occ, &dynamic_data, errp)) {
918         return false;
919     }
920 
921     return true;
922 }
923