1 /*
2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include "qemu/osdep.h"
29 #include "cpu.h"
30 #include "exec/cpu-interrupt.h"
31 #include "hw/irq.h"
32 #include "qemu/log.h"
33 #include "qemu/timer.h"
34 #include "qemu/atomic.h"
35
check_interrupts(CPUXtensaState * env)36 void check_interrupts(CPUXtensaState *env)
37 {
38 CPUState *cs = env_cpu(env);
39 int minlevel = xtensa_get_cintlevel(env);
40 uint32_t int_set_enabled = env->sregs[INTSET] &
41 (env->sregs[INTENABLE] | env->config->inttype_mask[INTTYPE_NMI]);
42 int level;
43
44 if (minlevel >= env->config->nmi_level) {
45 minlevel = env->config->nmi_level - 1;
46 }
47 for (level = env->config->nlevel; level > minlevel; --level) {
48 if (env->config->level_mask[level] & int_set_enabled) {
49 env->pending_irq_level = level;
50 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
51 qemu_log_mask(CPU_LOG_INT,
52 "%s level = %d, cintlevel = %d, "
53 "pc = %08x, a0 = %08x, ps = %08x, "
54 "intset = %08x, intenable = %08x, "
55 "ccount = %08x\n",
56 __func__, level, xtensa_get_cintlevel(env),
57 env->pc, env->regs[0], env->sregs[PS],
58 env->sregs[INTSET], env->sregs[INTENABLE],
59 env->sregs[CCOUNT]);
60 return;
61 }
62 }
63 env->pending_irq_level = 0;
64 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
65 }
66
xtensa_set_irq(void * opaque,int irq,int active)67 static void xtensa_set_irq(void *opaque, int irq, int active)
68 {
69 CPUXtensaState *env = opaque;
70
71 if (irq >= env->config->ninterrupt) {
72 qemu_log("%s: bad IRQ %d\n", __func__, irq);
73 } else {
74 uint32_t irq_bit = 1 << irq;
75
76 if (active) {
77 qatomic_or(&env->sregs[INTSET], irq_bit);
78 } else if (env->config->interrupt[irq].inttype == INTTYPE_LEVEL) {
79 qatomic_and(&env->sregs[INTSET], ~irq_bit);
80 }
81
82 check_interrupts(env);
83 }
84 }
85
xtensa_ccompare_cb(void * opaque)86 static void xtensa_ccompare_cb(void *opaque)
87 {
88 XtensaCcompareTimer *ccompare = opaque;
89 CPUXtensaState *env = ccompare->env;
90 unsigned i = ccompare - env->ccompare;
91
92 qemu_set_irq(env->irq_inputs[env->config->timerint[i]], 1);
93 }
94
xtensa_set_runstall(void * opaque,int irq,int active)95 static void xtensa_set_runstall(void *opaque, int irq, int active)
96 {
97 CPUXtensaState *env = opaque;
98 xtensa_runstall(env, active);
99 }
100
xtensa_irq_init(CPUXtensaState * env)101 void xtensa_irq_init(CPUXtensaState *env)
102 {
103 unsigned i;
104
105 env->irq_inputs = qemu_allocate_irqs(xtensa_set_irq, env,
106 env->config->ninterrupt);
107 if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
108 env->time_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
109 env->ccount_base = env->sregs[CCOUNT];
110 for (i = 0; i < env->config->nccompare; ++i) {
111 env->ccompare[i].env = env;
112 env->ccompare[i].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
113 xtensa_ccompare_cb, env->ccompare + i);
114 }
115 }
116 for (i = 0; i < env->config->nextint; ++i) {
117 unsigned irq = env->config->extint[i];
118
119 env->ext_irq_inputs[i] = env->irq_inputs[irq];
120 }
121 env->runstall_irq = qemu_allocate_irq(xtensa_set_runstall, env, 0);
122 }
123
xtensa_get_extints(CPUXtensaState * env)124 qemu_irq *xtensa_get_extints(CPUXtensaState *env)
125 {
126 return env->ext_irq_inputs;
127 }
128
xtensa_get_runstall(CPUXtensaState * env)129 qemu_irq xtensa_get_runstall(CPUXtensaState *env)
130 {
131 return env->runstall_irq;
132 }
133