1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include CONFIG_DEVICES
27
28 #include "qemu/units.h"
29 #include "hw/char/parallel-isa.h"
30 #include "hw/dma/i8257.h"
31 #include "hw/loader.h"
32 #include "hw/i386/x86.h"
33 #include "hw/i386/pc.h"
34 #include "hw/i386/apic.h"
35 #include "hw/pci-host/i440fx.h"
36 #include "hw/rtc/mc146818rtc.h"
37 #include "hw/southbridge/piix.h"
38 #include "hw/display/ramfb.h"
39 #include "hw/pci/pci.h"
40 #include "hw/pci/pci_ids.h"
41 #include "hw/usb.h"
42 #include "net/net.h"
43 #include "hw/ide/isa.h"
44 #include "hw/ide/pci.h"
45 #include "hw/irq.h"
46 #include "system/kvm.h"
47 #include "hw/i386/kvm/clock.h"
48 #include "hw/sysbus.h"
49 #include "hw/i2c/smbus_eeprom.h"
50 #include "system/memory.h"
51 #include "hw/acpi/acpi.h"
52 #include "qapi/error.h"
53 #include "qemu/error-report.h"
54 #include "system/xen.h"
55 #ifdef CONFIG_XEN
56 #include <xen/hvm/hvm_info_table.h>
57 #include "hw/xen/xen_pt.h"
58 #include "hw/xen/xen_igd.h"
59 #endif
60 #include "hw/xen/xen-x86.h"
61 #include "hw/xen/xen.h"
62 #include "migration/global_state.h"
63 #include "migration/misc.h"
64 #include "system/runstate.h"
65 #include "system/numa.h"
66 #include "hw/hyperv/vmbus-bridge.h"
67 #include "hw/mem/nvdimm.h"
68 #include "hw/uefi/var-service-api.h"
69 #include "hw/i386/acpi-build.h"
70 #include "target/i386/cpu.h"
71
72 #define XEN_IOAPIC_NUM_PIRQS 128ULL
73
74 #ifdef CONFIG_IDE_ISA
75 static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 };
76 static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
77 static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
78 #endif
79
80 /*
81 * Return the global irq number corresponding to a given device irq
82 * pin. We could also use the bus number to have a more precise mapping.
83 */
pc_pci_slot_get_pirq(PCIDevice * pci_dev,int pci_intx)84 static int pc_pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
85 {
86 int slot_addend;
87 slot_addend = PCI_SLOT(pci_dev->devfn) - 1;
88 return (pci_intx + slot_addend) & 3;
89 }
90
piix_intx_routing_notifier_xen(PCIDevice * dev)91 static void piix_intx_routing_notifier_xen(PCIDevice *dev)
92 {
93 int i;
94
95 /* Scan for updates to PCI link routes. */
96 for (i = 0; i < PIIX_NUM_PIRQS; i++) {
97 const PCIINTxRoute route = pci_device_route_intx_to_irq(dev, i);
98 const uint8_t v = route.mode == PCI_INTX_ENABLED ? route.irq : 0;
99 xen_set_pci_link_route(i, v);
100 }
101 }
102
103 /* PC hardware initialisation */
pc_init1(MachineState * machine,const char * pci_type)104 static void pc_init1(MachineState *machine, const char *pci_type)
105 {
106 PCMachineState *pcms = PC_MACHINE(machine);
107 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
108 X86MachineState *x86ms = X86_MACHINE(machine);
109 MemoryRegion *system_memory = get_system_memory();
110 MemoryRegion *system_io = get_system_io();
111 Object *phb = NULL;
112 ISABus *isa_bus;
113 Object *piix4_pm = NULL;
114 qemu_irq smi_irq;
115 GSIState *gsi_state;
116 MemoryRegion *ram_memory;
117 MemoryRegion *pci_memory = NULL;
118 MemoryRegion *rom_memory = system_memory;
119 ram_addr_t lowmem;
120 uint64_t hole64_size = 0;
121
122 /*
123 * Calculate ram split, for memory below and above 4G. It's a bit
124 * complicated for backward compatibility reasons ...
125 *
126 * - Traditional split is 3.5G (lowmem = 0xe0000000). This is the
127 * default value for max_ram_below_4g now.
128 *
129 * - Then, to gigabyte align the memory, we move the split to 3G
130 * (lowmem = 0xc0000000). But only in case we have to split in
131 * the first place, i.e. ram_size is larger than (traditional)
132 * lowmem. And for new machine types (gigabyte_align = true)
133 * only, for live migration compatibility reasons.
134 *
135 * - Next the max-ram-below-4g option was added, which allowed to
136 * reduce lowmem to a smaller value, to allow a larger PCI I/O
137 * window below 4G. qemu doesn't enforce gigabyte alignment here,
138 * but prints a warning.
139 *
140 * - Finally max-ram-below-4g got updated to also allow raising lowmem,
141 * so legacy non-PAE guests can get as much memory as possible in
142 * the 32bit address space below 4G.
143 *
144 * - Note that Xen has its own ram setup code in xen_ram_init(),
145 * called via xen_hvm_init_pc().
146 *
147 * Examples:
148 * qemu -M pc-1.7 -m 4G (old default) -> 3584M low, 512M high
149 * qemu -M pc -m 4G (new default) -> 3072M low, 1024M high
150 * qemu -M pc,max-ram-below-4g=2G -m 4G -> 2048M low, 2048M high
151 * qemu -M pc,max-ram-below-4g=4G -m 3968M -> 3968M low (=4G-128M)
152 */
153 if (xen_enabled()) {
154 xen_hvm_init_pc(pcms, &ram_memory);
155 } else {
156 ram_memory = machine->ram;
157 if (!pcms->max_ram_below_4g) {
158 pcms->max_ram_below_4g = 0xe0000000; /* default: 3.5G */
159 }
160 lowmem = pcms->max_ram_below_4g;
161 if (machine->ram_size >= pcms->max_ram_below_4g) {
162 if (pcmc->gigabyte_align) {
163 if (lowmem > 0xc0000000) {
164 lowmem = 0xc0000000;
165 }
166 if (lowmem & (1 * GiB - 1)) {
167 warn_report("Large machine and max_ram_below_4g "
168 "(%" PRIu64 ") not a multiple of 1G; "
169 "possible bad performance.",
170 pcms->max_ram_below_4g);
171 }
172 }
173 }
174
175 if (machine->ram_size >= lowmem) {
176 x86ms->above_4g_mem_size = machine->ram_size - lowmem;
177 x86ms->below_4g_mem_size = lowmem;
178 } else {
179 x86ms->above_4g_mem_size = 0;
180 x86ms->below_4g_mem_size = machine->ram_size;
181 }
182 }
183
184 pc_machine_init_sgx_epc(pcms);
185 x86_cpus_init(x86ms, pcmc->default_cpu_version);
186
187 if (kvm_enabled()) {
188 kvmclock_create(pcmc->kvmclock_create_always);
189 }
190
191 if (pcmc->pci_enabled) {
192 pci_memory = g_new(MemoryRegion, 1);
193 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
194 rom_memory = pci_memory;
195
196 phb = OBJECT(qdev_new(TYPE_I440FX_PCI_HOST_BRIDGE));
197 object_property_add_child(OBJECT(machine), "i440fx", phb);
198 object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM,
199 OBJECT(ram_memory), &error_fatal);
200 object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM,
201 OBJECT(pci_memory), &error_fatal);
202 object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM,
203 OBJECT(system_memory), &error_fatal);
204 object_property_set_link(phb, PCI_HOST_PROP_IO_MEM,
205 OBJECT(system_io), &error_fatal);
206 object_property_set_uint(phb, PCI_HOST_BELOW_4G_MEM_SIZE,
207 x86ms->below_4g_mem_size, &error_fatal);
208 object_property_set_uint(phb, PCI_HOST_ABOVE_4G_MEM_SIZE,
209 x86ms->above_4g_mem_size, &error_fatal);
210 object_property_set_str(phb, I440FX_HOST_PROP_PCI_TYPE, pci_type,
211 &error_fatal);
212 sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal);
213
214 pcms->pcibus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pci.0"));
215 pci_bus_map_irqs(pcms->pcibus,
216 xen_enabled() ? xen_pci_slot_get_pirq
217 : pc_pci_slot_get_pirq);
218
219 hole64_size = object_property_get_uint(phb,
220 PCI_HOST_PROP_PCI_HOLE64_SIZE,
221 &error_abort);
222 }
223
224 /* allocate ram and load rom/bios */
225 if (!xen_enabled()) {
226 pc_memory_init(pcms, system_memory, rom_memory, hole64_size);
227 } else {
228 assert(machine->ram_size == x86ms->below_4g_mem_size +
229 x86ms->above_4g_mem_size);
230
231 pc_system_flash_cleanup_unused(pcms);
232 if (machine->kernel_filename != NULL) {
233 /* For xen HVM direct kernel boot, load linux here */
234 xen_load_linux(pcms);
235 }
236 }
237
238 gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
239
240 if (pcmc->pci_enabled) {
241 PCIDevice *pci_dev;
242 DeviceState *dev;
243 size_t i;
244
245 pci_dev = pci_new_multifunction(-1, pcms->south_bridge);
246 object_property_set_bool(OBJECT(pci_dev), "has-usb",
247 machine_usb(machine), &error_abort);
248 object_property_set_bool(OBJECT(pci_dev), "has-acpi",
249 x86_machine_is_acpi_enabled(x86ms),
250 &error_abort);
251 object_property_set_bool(OBJECT(pci_dev), "has-pic", false,
252 &error_abort);
253 object_property_set_bool(OBJECT(pci_dev), "has-pit", false,
254 &error_abort);
255 qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100);
256 object_property_set_bool(OBJECT(pci_dev), "smm-enabled",
257 x86_machine_is_smm_enabled(x86ms),
258 &error_abort);
259 dev = DEVICE(pci_dev);
260 for (i = 0; i < ISA_NUM_IRQS; i++) {
261 qdev_connect_gpio_out_named(dev, "isa-irqs", i, x86ms->gsi[i]);
262 }
263 pci_realize_and_unref(pci_dev, pcms->pcibus, &error_fatal);
264
265 if (xen_enabled()) {
266 pci_device_set_intx_routing_notifier(
267 pci_dev, piix_intx_routing_notifier_xen);
268
269 /*
270 * Xen supports additional interrupt routes from the PCI devices to
271 * the IOAPIC: the four pins of each PCI device on the bus are also
272 * connected to the IOAPIC directly.
273 * These additional routes can be discovered through ACPI.
274 */
275 pci_bus_irqs(pcms->pcibus, xen_intx_set_irq, pci_dev,
276 XEN_IOAPIC_NUM_PIRQS);
277 }
278
279 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0"));
280 x86ms->rtc = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev),
281 "rtc"));
282 piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm");
283 dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide"));
284 pci_ide_create_devs(PCI_DEVICE(dev));
285 pcms->idebus[0] = qdev_get_child_bus(dev, "ide.0");
286 pcms->idebus[1] = qdev_get_child_bus(dev, "ide.1");
287 } else {
288 uint32_t irq;
289
290 isa_bus = isa_bus_new(NULL, system_memory, system_io,
291 &error_abort);
292 isa_bus_register_input_irqs(isa_bus, x86ms->gsi);
293
294 x86ms->rtc = isa_new(TYPE_MC146818_RTC);
295 qdev_prop_set_int32(DEVICE(x86ms->rtc), "base_year", 2000);
296 isa_realize_and_unref(x86ms->rtc, isa_bus, &error_fatal);
297 irq = object_property_get_uint(OBJECT(x86ms->rtc), "irq",
298 &error_fatal);
299 isa_connect_gpio_out(ISA_DEVICE(x86ms->rtc), 0, irq);
300
301 i8257_dma_init(OBJECT(machine), isa_bus, 0);
302 pcms->hpet_enabled = false;
303 }
304
305 if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) {
306 pc_i8259_create(isa_bus, gsi_state->i8259_irq);
307 }
308
309 if (phb) {
310 ioapic_init_gsi(gsi_state, phb);
311 }
312
313 if (tcg_enabled()) {
314 x86_register_ferr_irq(x86ms->gsi[13]);
315 }
316
317 pc_vga_init(isa_bus, pcmc->pci_enabled ? pcms->pcibus : NULL);
318
319 /* init basic PC hardware */
320 pc_basic_device_init(pcms, isa_bus, x86ms->gsi, x86ms->rtc,
321 !MACHINE_CLASS(pcmc)->no_floppy, 0x4);
322
323 pc_nic_init(pcmc, isa_bus, pcms->pcibus);
324
325 #ifdef CONFIG_IDE_ISA
326 if (!pcmc->pci_enabled) {
327 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
328 int i;
329
330 ide_drive_get(hd, ARRAY_SIZE(hd));
331 for (i = 0; i < MAX_IDE_BUS; i++) {
332 ISADevice *dev;
333 char busname[] = "ide.0";
334 dev = isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i],
335 ide_irq[i],
336 hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
337 /*
338 * The ide bus name is ide.0 for the first bus and ide.1 for the
339 * second one.
340 */
341 busname[4] = '0' + i;
342 pcms->idebus[i] = qdev_get_child_bus(DEVICE(dev), busname);
343 }
344 }
345 #endif
346
347 if (piix4_pm) {
348 smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0);
349
350 qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_irq);
351 pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c"));
352 /* TODO: Populate SPD eeprom data. */
353 smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
354
355 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
356 TYPE_HOTPLUG_HANDLER,
357 (Object **)&x86ms->acpi_dev,
358 object_property_allow_set_link,
359 OBJ_PROP_LINK_STRONG);
360 object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
361 piix4_pm, &error_abort);
362 }
363
364 if (machine->nvdimms_state->is_enabled) {
365 nvdimm_init_acpi_state(machine->nvdimms_state, system_io,
366 x86_nvdimm_acpi_dsmio,
367 x86ms->fw_cfg, OBJECT(pcms));
368 }
369 }
370
371 typedef enum PCSouthBridgeOption {
372 PC_SOUTH_BRIDGE_OPTION_PIIX3,
373 PC_SOUTH_BRIDGE_OPTION_PIIX4,
374 PC_SOUTH_BRIDGE_OPTION_MAX,
375 } PCSouthBridgeOption;
376
377 static const QEnumLookup PCSouthBridgeOption_lookup = {
378 .array = (const char *const[]) {
379 [PC_SOUTH_BRIDGE_OPTION_PIIX3] = TYPE_PIIX3_DEVICE,
380 [PC_SOUTH_BRIDGE_OPTION_PIIX4] = TYPE_PIIX4_PCI_DEVICE,
381 },
382 .size = PC_SOUTH_BRIDGE_OPTION_MAX
383 };
384
pc_get_south_bridge(Object * obj,Error ** errp)385 static int pc_get_south_bridge(Object *obj, Error **errp)
386 {
387 PCMachineState *pcms = PC_MACHINE(obj);
388 int i;
389
390 for (i = 0; i < PCSouthBridgeOption_lookup.size; i++) {
391 if (g_strcmp0(PCSouthBridgeOption_lookup.array[i],
392 pcms->south_bridge) == 0) {
393 return i;
394 }
395 }
396
397 error_setg(errp, "Invalid south bridge value set");
398 return 0;
399 }
400
pc_set_south_bridge(Object * obj,int value,Error ** errp)401 static void pc_set_south_bridge(Object *obj, int value, Error **errp)
402 {
403 PCMachineState *pcms = PC_MACHINE(obj);
404
405 if (value < 0) {
406 error_setg(errp, "Value can't be negative");
407 return;
408 }
409
410 if (value >= PCSouthBridgeOption_lookup.size) {
411 error_setg(errp, "Value too big");
412 return;
413 }
414
415 pcms->south_bridge = PCSouthBridgeOption_lookup.array[value];
416 }
417
418 #ifdef CONFIG_ISAPC
pc_init_isa(MachineState * machine)419 static void pc_init_isa(MachineState *machine)
420 {
421 pc_init1(machine, NULL);
422 }
423 #endif
424
425 #ifdef CONFIG_XEN
pc_xen_hvm_init_pci(MachineState * machine)426 static void pc_xen_hvm_init_pci(MachineState *machine)
427 {
428 const char *pci_type = xen_igd_gfx_pt_enabled() ?
429 TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE : TYPE_I440FX_PCI_DEVICE;
430
431 pc_init1(machine, pci_type);
432 }
433
pc_xen_hvm_init(MachineState * machine)434 static void pc_xen_hvm_init(MachineState *machine)
435 {
436 PCMachineState *pcms = PC_MACHINE(machine);
437
438 if (!xen_enabled()) {
439 error_report("xenfv machine requires the xen accelerator");
440 exit(1);
441 }
442
443 pc_xen_hvm_init_pci(machine);
444 xen_igd_reserve_slot(pcms->pcibus);
445 pci_create_simple(pcms->pcibus, -1, "xen-platform");
446 }
447 #endif
448
pc_i440fx_init(MachineState * machine)449 static void pc_i440fx_init(MachineState *machine)
450 {
451 pc_init1(machine, TYPE_I440FX_PCI_DEVICE);
452 }
453
454 #define DEFINE_I440FX_MACHINE(major, minor) \
455 DEFINE_PC_VER_MACHINE(pc_i440fx, "pc-i440fx", pc_i440fx_init, false, NULL, major, minor);
456
457 #define DEFINE_I440FX_MACHINE_AS_LATEST(major, minor) \
458 DEFINE_PC_VER_MACHINE(pc_i440fx, "pc-i440fx", pc_i440fx_init, true, "pc", major, minor);
459
pc_i440fx_machine_options(MachineClass * m)460 static void pc_i440fx_machine_options(MachineClass *m)
461 {
462 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
463 ObjectClass *oc = OBJECT_CLASS(m);
464 pcmc->default_south_bridge = TYPE_PIIX3_DEVICE;
465 pcmc->pci_root_uid = 0;
466 pcmc->default_cpu_version = 1;
467
468 m->family = "pc_piix";
469 m->desc = "Standard PC (i440FX + PIIX, 1996)";
470 m->default_machine_opts = "firmware=bios-256k.bin";
471 m->default_display = "std";
472 m->default_nic = "e1000";
473 m->no_floppy = !module_object_class_by_name(TYPE_ISA_FDC);
474 m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL);
475 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
476 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE);
477 machine_class_allow_dynamic_sysbus_dev(m, TYPE_UEFI_VARS_X64);
478
479 object_class_property_add_enum(oc, "x-south-bridge", "PCSouthBridgeOption",
480 &PCSouthBridgeOption_lookup,
481 pc_get_south_bridge,
482 pc_set_south_bridge);
483 object_class_property_set_description(oc, "x-south-bridge",
484 "Use a different south bridge than PIIX3");
485 }
486
pc_i440fx_machine_10_1_options(MachineClass * m)487 static void pc_i440fx_machine_10_1_options(MachineClass *m)
488 {
489 pc_i440fx_machine_options(m);
490 }
491
492 DEFINE_I440FX_MACHINE_AS_LATEST(10, 1);
493
pc_i440fx_machine_10_0_options(MachineClass * m)494 static void pc_i440fx_machine_10_0_options(MachineClass *m)
495 {
496 pc_i440fx_machine_10_1_options(m);
497 compat_props_add(m->compat_props, hw_compat_10_0, hw_compat_10_0_len);
498 compat_props_add(m->compat_props, pc_compat_10_0, pc_compat_10_0_len);
499 }
500
501 DEFINE_I440FX_MACHINE(10, 0);
502
pc_i440fx_machine_9_2_options(MachineClass * m)503 static void pc_i440fx_machine_9_2_options(MachineClass *m)
504 {
505 pc_i440fx_machine_10_0_options(m);
506 compat_props_add(m->compat_props, hw_compat_9_2, hw_compat_9_2_len);
507 compat_props_add(m->compat_props, pc_compat_9_2, pc_compat_9_2_len);
508 }
509
510 DEFINE_I440FX_MACHINE(9, 2);
511
pc_i440fx_machine_9_1_options(MachineClass * m)512 static void pc_i440fx_machine_9_1_options(MachineClass *m)
513 {
514 pc_i440fx_machine_9_2_options(m);
515 compat_props_add(m->compat_props, hw_compat_9_1, hw_compat_9_1_len);
516 compat_props_add(m->compat_props, pc_compat_9_1, pc_compat_9_1_len);
517 }
518
519 DEFINE_I440FX_MACHINE(9, 1);
520
pc_i440fx_machine_9_0_options(MachineClass * m)521 static void pc_i440fx_machine_9_0_options(MachineClass *m)
522 {
523 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
524
525 pc_i440fx_machine_9_1_options(m);
526 m->smbios_memory_device_size = 16 * GiB;
527
528 compat_props_add(m->compat_props, hw_compat_9_0, hw_compat_9_0_len);
529 compat_props_add(m->compat_props, pc_compat_9_0, pc_compat_9_0_len);
530 pcmc->isa_bios_alias = false;
531 }
532
533 DEFINE_I440FX_MACHINE(9, 0);
534
pc_i440fx_machine_8_2_options(MachineClass * m)535 static void pc_i440fx_machine_8_2_options(MachineClass *m)
536 {
537 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
538
539 pc_i440fx_machine_9_0_options(m);
540
541 compat_props_add(m->compat_props, hw_compat_8_2, hw_compat_8_2_len);
542 compat_props_add(m->compat_props, pc_compat_8_2, pc_compat_8_2_len);
543 /* For pc-i44fx-8.2 and 8.1, use SMBIOS 3.X by default */
544 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64;
545 }
546
547 DEFINE_I440FX_MACHINE(8, 2);
548
pc_i440fx_machine_8_1_options(MachineClass * m)549 static void pc_i440fx_machine_8_1_options(MachineClass *m)
550 {
551 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
552
553 pc_i440fx_machine_8_2_options(m);
554 pcmc->broken_32bit_mem_addr_check = true;
555
556 compat_props_add(m->compat_props, hw_compat_8_1, hw_compat_8_1_len);
557 compat_props_add(m->compat_props, pc_compat_8_1, pc_compat_8_1_len);
558 }
559
560 DEFINE_I440FX_MACHINE(8, 1);
561
pc_i440fx_machine_8_0_options(MachineClass * m)562 static void pc_i440fx_machine_8_0_options(MachineClass *m)
563 {
564 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
565
566 pc_i440fx_machine_8_1_options(m);
567 compat_props_add(m->compat_props, hw_compat_8_0, hw_compat_8_0_len);
568 compat_props_add(m->compat_props, pc_compat_8_0, pc_compat_8_0_len);
569
570 /* For pc-i44fx-8.0 and older, use SMBIOS 2.8 by default */
571 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32;
572 }
573
574 DEFINE_I440FX_MACHINE(8, 0);
575
pc_i440fx_machine_7_2_options(MachineClass * m)576 static void pc_i440fx_machine_7_2_options(MachineClass *m)
577 {
578 pc_i440fx_machine_8_0_options(m);
579 compat_props_add(m->compat_props, hw_compat_7_2, hw_compat_7_2_len);
580 compat_props_add(m->compat_props, pc_compat_7_2, pc_compat_7_2_len);
581 }
582
583 DEFINE_I440FX_MACHINE(7, 2)
584
pc_i440fx_machine_7_1_options(MachineClass * m)585 static void pc_i440fx_machine_7_1_options(MachineClass *m)
586 {
587 pc_i440fx_machine_7_2_options(m);
588 compat_props_add(m->compat_props, hw_compat_7_1, hw_compat_7_1_len);
589 compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len);
590 }
591
592 DEFINE_I440FX_MACHINE(7, 1);
593
pc_i440fx_machine_7_0_options(MachineClass * m)594 static void pc_i440fx_machine_7_0_options(MachineClass *m)
595 {
596 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
597 pc_i440fx_machine_7_1_options(m);
598 pcmc->enforce_amd_1tb_hole = false;
599 compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len);
600 compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len);
601 }
602
603 DEFINE_I440FX_MACHINE(7, 0);
604
pc_i440fx_machine_6_2_options(MachineClass * m)605 static void pc_i440fx_machine_6_2_options(MachineClass *m)
606 {
607 pc_i440fx_machine_7_0_options(m);
608 compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len);
609 compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len);
610 }
611
612 DEFINE_I440FX_MACHINE(6, 2);
613
pc_i440fx_machine_6_1_options(MachineClass * m)614 static void pc_i440fx_machine_6_1_options(MachineClass *m)
615 {
616 pc_i440fx_machine_6_2_options(m);
617 compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len);
618 compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len);
619 m->smp_props.prefer_sockets = true;
620 }
621
622 DEFINE_I440FX_MACHINE(6, 1);
623
pc_i440fx_machine_6_0_options(MachineClass * m)624 static void pc_i440fx_machine_6_0_options(MachineClass *m)
625 {
626 pc_i440fx_machine_6_1_options(m);
627 compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len);
628 compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len);
629 }
630
631 DEFINE_I440FX_MACHINE(6, 0);
632
pc_i440fx_machine_5_2_options(MachineClass * m)633 static void pc_i440fx_machine_5_2_options(MachineClass *m)
634 {
635 pc_i440fx_machine_6_0_options(m);
636 compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len);
637 compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len);
638 }
639
640 DEFINE_I440FX_MACHINE(5, 2);
641
pc_i440fx_machine_5_1_options(MachineClass * m)642 static void pc_i440fx_machine_5_1_options(MachineClass *m)
643 {
644 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
645
646 pc_i440fx_machine_5_2_options(m);
647 compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len);
648 compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len);
649 pcmc->kvmclock_create_always = false;
650 pcmc->pci_root_uid = 1;
651 }
652
653 DEFINE_I440FX_MACHINE(5, 1);
654
pc_i440fx_machine_5_0_options(MachineClass * m)655 static void pc_i440fx_machine_5_0_options(MachineClass *m)
656 {
657 pc_i440fx_machine_5_1_options(m);
658 m->numa_mem_supported = true;
659 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len);
660 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len);
661 m->auto_enable_numa_with_memdev = false;
662 }
663
664 DEFINE_I440FX_MACHINE(5, 0);
665
pc_i440fx_machine_4_2_options(MachineClass * m)666 static void pc_i440fx_machine_4_2_options(MachineClass *m)
667 {
668 pc_i440fx_machine_5_0_options(m);
669 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len);
670 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len);
671 }
672
673 DEFINE_I440FX_MACHINE(4, 2);
674
pc_i440fx_machine_4_1_options(MachineClass * m)675 static void pc_i440fx_machine_4_1_options(MachineClass *m)
676 {
677 pc_i440fx_machine_4_2_options(m);
678 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len);
679 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len);
680 }
681
682 DEFINE_I440FX_MACHINE(4, 1);
683
pc_i440fx_machine_4_0_options(MachineClass * m)684 static void pc_i440fx_machine_4_0_options(MachineClass *m)
685 {
686 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
687 pc_i440fx_machine_4_1_options(m);
688 pcmc->default_cpu_version = CPU_VERSION_LEGACY;
689 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len);
690 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len);
691 }
692
693 DEFINE_I440FX_MACHINE(4, 0);
694
pc_i440fx_machine_3_1_options(MachineClass * m)695 static void pc_i440fx_machine_3_1_options(MachineClass *m)
696 {
697 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
698
699 pc_i440fx_machine_4_0_options(m);
700 m->smbus_no_migration_support = true;
701 pcmc->pvh_enabled = false;
702 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len);
703 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len);
704 }
705
706 DEFINE_I440FX_MACHINE(3, 1);
707
pc_i440fx_machine_3_0_options(MachineClass * m)708 static void pc_i440fx_machine_3_0_options(MachineClass *m)
709 {
710 pc_i440fx_machine_3_1_options(m);
711 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len);
712 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len);
713 }
714
715 DEFINE_I440FX_MACHINE(3, 0);
716
pc_i440fx_machine_2_12_options(MachineClass * m)717 static void pc_i440fx_machine_2_12_options(MachineClass *m)
718 {
719 pc_i440fx_machine_3_0_options(m);
720 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len);
721 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len);
722 }
723
724 DEFINE_I440FX_MACHINE(2, 12);
725
pc_i440fx_machine_2_11_options(MachineClass * m)726 static void pc_i440fx_machine_2_11_options(MachineClass *m)
727 {
728 pc_i440fx_machine_2_12_options(m);
729 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len);
730 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len);
731 }
732
733 DEFINE_I440FX_MACHINE(2, 11);
734
pc_i440fx_machine_2_10_options(MachineClass * m)735 static void pc_i440fx_machine_2_10_options(MachineClass *m)
736 {
737 pc_i440fx_machine_2_11_options(m);
738 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len);
739 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len);
740 m->auto_enable_numa_with_memhp = false;
741 }
742
743 DEFINE_I440FX_MACHINE(2, 10);
744
pc_i440fx_machine_2_9_options(MachineClass * m)745 static void pc_i440fx_machine_2_9_options(MachineClass *m)
746 {
747 pc_i440fx_machine_2_10_options(m);
748 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len);
749 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len);
750 }
751
752 DEFINE_I440FX_MACHINE(2, 9);
753
pc_i440fx_machine_2_8_options(MachineClass * m)754 static void pc_i440fx_machine_2_8_options(MachineClass *m)
755 {
756 pc_i440fx_machine_2_9_options(m);
757 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len);
758 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len);
759 }
760
761 DEFINE_I440FX_MACHINE(2, 8);
762
pc_i440fx_machine_2_7_options(MachineClass * m)763 static void pc_i440fx_machine_2_7_options(MachineClass *m)
764 {
765 pc_i440fx_machine_2_8_options(m);
766 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len);
767 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len);
768 }
769
770 DEFINE_I440FX_MACHINE(2, 7);
771
pc_i440fx_machine_2_6_options(MachineClass * m)772 static void pc_i440fx_machine_2_6_options(MachineClass *m)
773 {
774 X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
775 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
776
777 pc_i440fx_machine_2_7_options(m);
778 pcmc->legacy_cpu_hotplug = true;
779 x86mc->fwcfg_dma_enabled = false;
780 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len);
781 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len);
782 }
783
784 DEFINE_I440FX_MACHINE(2, 6);
785
786 #ifdef CONFIG_ISAPC
isapc_machine_options(MachineClass * m)787 static void isapc_machine_options(MachineClass *m)
788 {
789 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
790 m->desc = "ISA-only PC";
791 m->max_cpus = 1;
792 m->option_rom_has_mr = true;
793 m->rom_file_has_mr = false;
794 pcmc->pci_enabled = false;
795 pcmc->has_acpi_build = false;
796 pcmc->smbios_defaults = false;
797 pcmc->gigabyte_align = false;
798 pcmc->smbios_legacy_mode = true;
799 pcmc->has_reserved_memory = false;
800 m->default_nic = "ne2k_isa";
801 m->default_cpu_type = X86_CPU_TYPE_NAME("486");
802 m->no_floppy = !module_object_class_by_name(TYPE_ISA_FDC);
803 m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL);
804 }
805
806 DEFINE_PC_MACHINE(isapc, "isapc", pc_init_isa,
807 isapc_machine_options);
808 #endif
809
810 #ifdef CONFIG_XEN
xenfv_machine_4_2_options(MachineClass * m)811 static void xenfv_machine_4_2_options(MachineClass *m)
812 {
813 pc_i440fx_machine_4_2_options(m);
814 m->desc = "Xen Fully-virtualized PC";
815 m->max_cpus = HVM_MAX_VCPUS;
816 m->default_machine_opts = "accel=xen,suppress-vmdesc=on";
817 }
818
819 DEFINE_PC_MACHINE(xenfv_4_2, "xenfv-4.2", pc_xen_hvm_init,
820 xenfv_machine_4_2_options);
821
xenfv_machine_3_1_options(MachineClass * m)822 static void xenfv_machine_3_1_options(MachineClass *m)
823 {
824 pc_i440fx_machine_3_1_options(m);
825 m->desc = "Xen Fully-virtualized PC";
826 m->alias = "xenfv";
827 m->max_cpus = HVM_MAX_VCPUS;
828 m->default_machine_opts = "accel=xen,suppress-vmdesc=on";
829 }
830
831 DEFINE_PC_MACHINE(xenfv, "xenfv-3.1", pc_xen_hvm_init,
832 xenfv_machine_3_1_options);
833 #endif
834