1 /* 2 * Header file required by picodlp panel driver 3 * 4 * Copyright (C) 2009-2011 Texas Instruments 5 * Author: Mythri P K <mythripk@ti.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef __OMAP2_DISPLAY_PANEL_PICODLP_H 21 #define __OMAP2_DISPLAY_PANEL_PICODLP_H 22 23 /* Commands used for configuring picodlp panel */ 24 25 #define MAIN_STATUS 0x03 26 #define PBC_CONTROL 0x08 27 #define INPUT_SOURCE 0x0B 28 #define INPUT_RESOLUTION 0x0C 29 #define DATA_FORMAT 0x0D 30 #define IMG_ROTATION 0x0E 31 #define LONG_FLIP 0x0F 32 #define SHORT_FLIP 0x10 33 #define TEST_PAT_SELECT 0x11 34 #define R_DRIVE_CURRENT 0x12 35 #define G_DRIVE_CURRENT 0x13 36 #define B_DRIVE_CURRENT 0x14 37 #define READ_REG_SELECT 0x15 38 #define RGB_DRIVER_ENABLE 0x16 39 40 #define CPU_IF_MODE 0x18 41 #define FRAME_RATE 0x19 42 #define CPU_IF_SYNC_METHOD 0x1A 43 #define CPU_IF_SOF 0x1B 44 #define CPU_IF_EOF 0x1C 45 #define CPU_IF_SLEEP 0x1D 46 47 #define SEQUENCE_MODE 0x1E 48 #define SOFT_RESET 0x1F 49 #define FRONT_END_RESET 0x21 50 #define AUTO_PWR_ENABLE 0x22 51 52 #define VSYNC_LINE_DELAY 0x23 53 #define CPU_PI_HORIZ_START 0x24 54 #define CPU_PI_VERT_START 0x25 55 #define CPU_PI_HORIZ_WIDTH 0x26 56 #define CPU_PI_VERT_HEIGHT 0x27 57 58 #define PIXEL_MASK_CROP 0x28 59 #define CROP_FIRST_LINE 0x29 60 #define CROP_LAST_LINE 0x2A 61 #define CROP_FIRST_PIXEL 0x2B 62 #define CROP_LAST_PIXEL 0x2C 63 #define DMD_PARK_TRIGGER 0x2D 64 65 #define MISC_REG 0x30 66 67 /* AGC registers */ 68 #define AGC_CTRL 0x50 69 #define AGC_CLIPPED_PIXS 0x55 70 #define AGC_BRIGHT_PIXS 0x56 71 #define AGC_BG_PIXS 0x57 72 #define AGC_SAFETY_MARGIN 0x17 73 74 /* Color Coordinate Adjustment registers */ 75 #define CCA_ENABLE 0x5E 76 #define CCA_C1A 0x5F 77 #define CCA_C1B 0x60 78 #define CCA_C1C 0x61 79 #define CCA_C2A 0x62 80 #define CCA_C2B 0x63 81 #define CCA_C2C 0x64 82 #define CCA_C3A 0x65 83 #define CCA_C3B 0x66 84 #define CCA_C3C 0x67 85 #define CCA_C7A 0x71 86 #define CCA_C7B 0x72 87 #define CCA_C7C 0x73 88 89 /** 90 * DLP Pico Processor 2600 comes with flash 91 * We can do DMA operations from flash for accessing Look Up Tables 92 */ 93 #define DMA_STATUS 0x100 94 #define FLASH_ADDR_BYTES 0x74 95 #define FLASH_DUMMY_BYTES 0x75 96 #define FLASH_WRITE_BYTES 0x76 97 #define FLASH_READ_BYTES 0x77 98 #define FLASH_OPCODE 0x78 99 #define FLASH_START_ADDR 0x79 100 #define FLASH_DUMMY2 0x7A 101 #define FLASH_WRITE_DATA 0x7B 102 103 #define TEMPORAL_DITH_DISABLE 0x7E 104 #define SEQ_CONTROL 0x82 105 #define SEQ_VECTOR 0x83 106 107 /* DMD is Digital Micromirror Device */ 108 #define DMD_BLOCK_COUNT 0x84 109 #define DMD_VCC_CONTROL 0x86 110 #define DMD_PARK_PULSE_COUNT 0x87 111 #define DMD_PARK_PULSE_WIDTH 0x88 112 #define DMD_PARK_DELAY 0x89 113 #define DMD_SHADOW_ENABLE 0x8E 114 #define SEQ_STATUS 0x8F 115 #define FLASH_CLOCK_CONTROL 0x98 116 #define DMD_PARK 0x2D 117 118 #define SDRAM_BIST_ENABLE 0x46 119 #define DDR_DRIVER_STRENGTH 0x9A 120 #define SDC_ENABLE 0x9D 121 #define SDC_BUFF_SWAP_DISABLE 0xA3 122 #define CURTAIN_CONTROL 0xA6 123 #define DDR_BUS_SWAP_ENABLE 0xA7 124 #define DMD_TRC_ENABLE 0xA8 125 #define DMD_BUS_SWAP_ENABLE 0xA9 126 127 #define ACTGEN_ENABLE 0xAE 128 #define ACTGEN_CONTROL 0xAF 129 #define ACTGEN_HORIZ_BP 0xB0 130 #define ACTGEN_VERT_BP 0xB1 131 132 /* Look Up Table access */ 133 #define CMT_SPLASH_LUT_START_ADDR 0xFA 134 #define CMT_SPLASH_LUT_DEST_SELECT 0xFB 135 #define CMT_SPLASH_LUT_DATA 0xFC 136 #define SEQ_RESET_LUT_START_ADDR 0xFD 137 #define SEQ_RESET_LUT_DEST_SELECT 0xFE 138 #define SEQ_RESET_LUT_DATA 0xFF 139 140 /* Input source definitions */ 141 #define PARALLEL_RGB 0 142 #define INT_TEST_PATTERN 1 143 #define SPLASH_SCREEN 2 144 #define CPU_INTF 3 145 #define BT656 4 146 147 /* Standard input resolution definitions */ 148 #define QWVGA_LANDSCAPE 3 /* (427h*240v) */ 149 #define WVGA_864_LANDSCAPE 21 /* (864h*480v) */ 150 #define WVGA_DMD_OPTICAL_TEST 35 /* (608h*684v) */ 151 152 /* Standard data format definitions */ 153 #define RGB565 0 154 #define RGB666 1 155 #define RGB888 2 156 157 /* Test Pattern definitions */ 158 #define TPG_CHECKERBOARD 0 159 #define TPG_BLACK 1 160 #define TPG_WHITE 2 161 #define TPG_RED 3 162 #define TPG_BLUE 4 163 #define TPG_GREEN 5 164 #define TPG_VLINES_BLACK 6 165 #define TPG_HLINES_BLACK 7 166 #define TPG_VLINES_ALT 8 167 #define TPG_HLINES_ALT 9 168 #define TPG_DIAG_LINES 10 169 #define TPG_GREYRAMP_VERT 11 170 #define TPG_GREYRAMP_HORIZ 12 171 #define TPG_ANSI_CHECKERBOARD 13 172 173 /* sequence mode definitions */ 174 #define SEQ_FREE_RUN 0 175 #define SEQ_LOCK 1 176 177 /* curtain color definitions */ 178 #define CURTAIN_BLACK 0 179 #define CURTAIN_RED 1 180 #define CURTAIN_GREEN 2 181 #define CURTAIN_BLUE 3 182 #define CURTAIN_YELLOW 4 183 #define CURTAIN_MAGENTA 5 184 #define CURTAIN_CYAN 6 185 #define CURTAIN_WHITE 7 186 187 /* LUT definitions */ 188 #define CMT_LUT_NONE 0 189 #define CMT_LUT_GREEN 1 190 #define CMT_LUT_RED 2 191 #define CMT_LUT_BLUE 3 192 #define CMT_LUT_ALL 4 193 #define SPLASH_LUT 5 194 195 #define SEQ_LUT_NONE 0 196 #define SEQ_DRC_LUT_0 1 197 #define SEQ_DRC_LUT_1 2 198 #define SEQ_DRC_LUT_2 3 199 #define SEQ_DRC_LUT_3 4 200 #define SEQ_SEQ_LUT 5 201 #define SEQ_DRC_LUT_ALL 6 202 #define WPC_PROGRAM_LUT 7 203 204 #define BITSTREAM_START_ADDR 0x00000000 205 #define BITSTREAM_SIZE 0x00040000 206 207 #define WPC_FW_0_START_ADDR 0x00040000 208 #define WPC_FW_0_SIZE 0x00000ce8 209 210 #define SEQUENCE_0_START_ADDR 0x00044000 211 #define SEQUENCE_0_SIZE 0x00001000 212 213 #define SEQUENCE_1_START_ADDR 0x00045000 214 #define SEQUENCE_1_SIZE 0x00000d10 215 216 #define SEQUENCE_2_START_ADDR 0x00046000 217 #define SEQUENCE_2_SIZE 0x00000d10 218 219 #define SEQUENCE_3_START_ADDR 0x00047000 220 #define SEQUENCE_3_SIZE 0x00000d10 221 222 #define SEQUENCE_4_START_ADDR 0x00048000 223 #define SEQUENCE_4_SIZE 0x00000d10 224 225 #define SEQUENCE_5_START_ADDR 0x00049000 226 #define SEQUENCE_5_SIZE 0x00000d10 227 228 #define SEQUENCE_6_START_ADDR 0x0004a000 229 #define SEQUENCE_6_SIZE 0x00000d10 230 231 #define CMT_LUT_0_START_ADDR 0x0004b200 232 #define CMT_LUT_0_SIZE 0x00000600 233 234 #define CMT_LUT_1_START_ADDR 0x0004b800 235 #define CMT_LUT_1_SIZE 0x00000600 236 237 #define CMT_LUT_2_START_ADDR 0x0004be00 238 #define CMT_LUT_2_SIZE 0x00000600 239 240 #define CMT_LUT_3_START_ADDR 0x0004c400 241 #define CMT_LUT_3_SIZE 0x00000600 242 243 #define CMT_LUT_4_START_ADDR 0x0004ca00 244 #define CMT_LUT_4_SIZE 0x00000600 245 246 #define CMT_LUT_5_START_ADDR 0x0004d000 247 #define CMT_LUT_5_SIZE 0x00000600 248 249 #define CMT_LUT_6_START_ADDR 0x0004d600 250 #define CMT_LUT_6_SIZE 0x00000600 251 252 #define DRC_TABLE_0_START_ADDR 0x0004dc00 253 #define DRC_TABLE_0_SIZE 0x00000100 254 255 #define SPLASH_0_START_ADDR 0x0004dd00 256 #define SPLASH_0_SIZE 0x00032280 257 258 #define SEQUENCE_7_START_ADDR 0x00080000 259 #define SEQUENCE_7_SIZE 0x00000d10 260 261 #define SEQUENCE_8_START_ADDR 0x00081800 262 #define SEQUENCE_8_SIZE 0x00000d10 263 264 #define SEQUENCE_9_START_ADDR 0x00083000 265 #define SEQUENCE_9_SIZE 0x00000d10 266 267 #define CMT_LUT_7_START_ADDR 0x0008e000 268 #define CMT_LUT_7_SIZE 0x00000600 269 270 #define CMT_LUT_8_START_ADDR 0x0008e800 271 #define CMT_LUT_8_SIZE 0x00000600 272 273 #define CMT_LUT_9_START_ADDR 0x0008f000 274 #define CMT_LUT_9_SIZE 0x00000600 275 276 #define SPLASH_1_START_ADDR 0x0009a000 277 #define SPLASH_1_SIZE 0x00032280 278 279 #define SPLASH_2_START_ADDR 0x000cd000 280 #define SPLASH_2_SIZE 0x00032280 281 282 #define SPLASH_3_START_ADDR 0x00100000 283 #define SPLASH_3_SIZE 0x00032280 284 285 #define OPT_SPLASH_0_START_ADDR 0x00134000 286 #define OPT_SPLASH_0_SIZE 0x000cb100 287 288 #endif 289