1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * C-Media CMI8788 driver - main driver module
4 *
5 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
6 */
7
8 #include <linux/delay.h>
9 #include <linux/interrupt.h>
10 #include <linux/mutex.h>
11 #include <linux/pci.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <sound/ac97_codec.h>
15 #include <sound/asoundef.h>
16 #include <sound/core.h>
17 #include <sound/info.h>
18 #include <sound/mpu401.h>
19 #include <sound/pcm.h>
20 #include "oxygen.h"
21 #include "cm9780.h"
22
23 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
24 MODULE_DESCRIPTION("C-Media CMI8788 helper library");
25 MODULE_LICENSE("GPL v2");
26
27 #define DRIVER "oxygen"
28
oxygen_uart_input_ready(struct oxygen * chip)29 static inline int oxygen_uart_input_ready(struct oxygen *chip)
30 {
31 return !(oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_RX_EMPTY);
32 }
33
oxygen_read_uart(struct oxygen * chip)34 static void oxygen_read_uart(struct oxygen *chip)
35 {
36 if (unlikely(!oxygen_uart_input_ready(chip))) {
37 /* no data, but read it anyway to clear the interrupt */
38 oxygen_read8(chip, OXYGEN_MPU401);
39 return;
40 }
41 do {
42 u8 data = oxygen_read8(chip, OXYGEN_MPU401);
43 if (data == MPU401_ACK)
44 continue;
45 if (chip->uart_input_count >= ARRAY_SIZE(chip->uart_input))
46 chip->uart_input_count = 0;
47 chip->uart_input[chip->uart_input_count++] = data;
48 } while (oxygen_uart_input_ready(chip));
49 if (chip->model.uart_input)
50 chip->model.uart_input(chip);
51 }
52
oxygen_interrupt(int dummy,void * dev_id)53 static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
54 {
55 struct oxygen *chip = dev_id;
56 unsigned int status, clear, elapsed_streams, i;
57
58 status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
59 if (!status)
60 return IRQ_NONE;
61
62 scoped_guard(spinlock, &chip->reg_lock) {
63 clear = status & (OXYGEN_CHANNEL_A |
64 OXYGEN_CHANNEL_B |
65 OXYGEN_CHANNEL_C |
66 OXYGEN_CHANNEL_SPDIF |
67 OXYGEN_CHANNEL_MULTICH |
68 OXYGEN_CHANNEL_AC97 |
69 OXYGEN_INT_SPDIF_IN_DETECT |
70 OXYGEN_INT_GPIO |
71 OXYGEN_INT_AC97);
72 if (clear) {
73 if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
74 chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
75 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
76 chip->interrupt_mask & ~clear);
77 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
78 chip->interrupt_mask);
79 }
80
81 elapsed_streams = status & chip->pcm_running;
82 }
83
84 for (i = 0; i < PCM_COUNT; ++i)
85 if ((elapsed_streams & (1 << i)) && chip->streams[i])
86 snd_pcm_period_elapsed(chip->streams[i]);
87
88 if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
89 guard(spinlock)(&chip->reg_lock);
90 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
91 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
92 OXYGEN_SPDIF_RATE_INT)) {
93 /* write the interrupt bit(s) to clear */
94 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
95 schedule_work(&chip->spdif_input_bits_work);
96 }
97 }
98
99 if (status & OXYGEN_INT_GPIO)
100 schedule_work(&chip->gpio_work);
101
102 if (status & OXYGEN_INT_MIDI) {
103 if (chip->midi)
104 snd_mpu401_uart_interrupt(0, chip->midi->private_data);
105 else
106 oxygen_read_uart(chip);
107 }
108
109 if (status & OXYGEN_INT_AC97)
110 wake_up(&chip->ac97_waitqueue);
111
112 return IRQ_HANDLED;
113 }
114
oxygen_spdif_input_bits_changed(struct work_struct * work)115 static void oxygen_spdif_input_bits_changed(struct work_struct *work)
116 {
117 struct oxygen *chip = container_of(work, struct oxygen,
118 spdif_input_bits_work);
119 u32 reg;
120
121 /*
122 * This function gets called when there is new activity on the SPDIF
123 * input, or when we lose lock on the input signal, or when the rate
124 * changes.
125 */
126 msleep(1);
127 scoped_guard(spinlock_irq, &chip->reg_lock) {
128 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
129 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
130 OXYGEN_SPDIF_LOCK_STATUS))
131 == OXYGEN_SPDIF_SENSE_STATUS) {
132 /*
133 * If we detect activity on the SPDIF input but cannot lock to
134 * a signal, the clock bit is likely to be wrong.
135 */
136 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
137 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
138 spin_unlock_irq(&chip->reg_lock);
139 msleep(1);
140 spin_lock_irq(&chip->reg_lock);
141 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
142 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
143 OXYGEN_SPDIF_LOCK_STATUS))
144 == OXYGEN_SPDIF_SENSE_STATUS) {
145 /* nothing detected with either clock; give up */
146 if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
147 == OXYGEN_SPDIF_IN_CLOCK_192) {
148 /*
149 * Reset clock to <= 96 kHz because this is
150 * more likely to be received next time.
151 */
152 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
153 reg |= OXYGEN_SPDIF_IN_CLOCK_96;
154 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
155 }
156 }
157 }
158 }
159
160 if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
161 scoped_guard(spinlock_irq, &chip->reg_lock) {
162 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
163 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
164 chip->interrupt_mask);
165 }
166
167 /*
168 * We don't actually know that any channel status bits have
169 * changed, but let's send a notification just to be sure.
170 */
171 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
172 &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
173 }
174 }
175
oxygen_gpio_changed(struct work_struct * work)176 static void oxygen_gpio_changed(struct work_struct *work)
177 {
178 struct oxygen *chip = container_of(work, struct oxygen, gpio_work);
179
180 if (chip->model.gpio_changed)
181 chip->model.gpio_changed(chip);
182 }
183
oxygen_proc_read(struct snd_info_entry * entry,struct snd_info_buffer * buffer)184 static void oxygen_proc_read(struct snd_info_entry *entry,
185 struct snd_info_buffer *buffer)
186 {
187 struct oxygen *chip = entry->private_data;
188 int i, j;
189
190 switch (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_PACKAGE_ID_MASK) {
191 case OXYGEN_PACKAGE_ID_8786: i = '6'; break;
192 case OXYGEN_PACKAGE_ID_8787: i = '7'; break;
193 case OXYGEN_PACKAGE_ID_8788: i = '8'; break;
194 default: i = '?'; break;
195 }
196 snd_iprintf(buffer, "CMI878%c:\n", i);
197 for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) {
198 snd_iprintf(buffer, "%02x:", i);
199 for (j = 0; j < 0x10; ++j)
200 snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
201 snd_iprintf(buffer, "\n");
202 }
203 if (mutex_lock_interruptible(&chip->mutex) < 0)
204 return;
205 if (chip->has_ac97_0) {
206 snd_iprintf(buffer, "\nAC97:\n");
207 for (i = 0; i < 0x80; i += 0x10) {
208 snd_iprintf(buffer, "%02x:", i);
209 for (j = 0; j < 0x10; j += 2)
210 snd_iprintf(buffer, " %04x",
211 oxygen_read_ac97(chip, 0, i + j));
212 snd_iprintf(buffer, "\n");
213 }
214 }
215 if (chip->has_ac97_1) {
216 snd_iprintf(buffer, "\nAC97 2:\n");
217 for (i = 0; i < 0x80; i += 0x10) {
218 snd_iprintf(buffer, "%02x:", i);
219 for (j = 0; j < 0x10; j += 2)
220 snd_iprintf(buffer, " %04x",
221 oxygen_read_ac97(chip, 1, i + j));
222 snd_iprintf(buffer, "\n");
223 }
224 }
225 mutex_unlock(&chip->mutex);
226 if (chip->model.dump_registers)
227 chip->model.dump_registers(chip, buffer);
228 }
229
oxygen_proc_init(struct oxygen * chip)230 static void oxygen_proc_init(struct oxygen *chip)
231 {
232 snd_card_ro_proc_new(chip->card, "oxygen", chip, oxygen_proc_read);
233 }
234
235 static const struct pci_device_id *
oxygen_search_pci_id(struct oxygen * chip,const struct pci_device_id ids[])236 oxygen_search_pci_id(struct oxygen *chip, const struct pci_device_id ids[])
237 {
238 u16 subdevice;
239
240 /*
241 * Make sure the EEPROM pins are available, i.e., not used for SPI.
242 * (This function is called before we initialize or use SPI.)
243 */
244 oxygen_clear_bits8(chip, OXYGEN_FUNCTION,
245 OXYGEN_FUNCTION_ENABLE_SPI_4_5);
246 /*
247 * Read the subsystem device ID directly from the EEPROM, because the
248 * chip didn't if the first EEPROM word was overwritten.
249 */
250 subdevice = oxygen_read_eeprom(chip, 2);
251 /* use default ID if EEPROM is missing */
252 if (subdevice == 0xffff && oxygen_read_eeprom(chip, 1) == 0xffff)
253 subdevice = 0x8788;
254 /*
255 * We use only the subsystem device ID for searching because it is
256 * unique even without the subsystem vendor ID, which may have been
257 * overwritten in the EEPROM.
258 */
259 for (; ids->vendor; ++ids)
260 if (ids->subdevice == subdevice &&
261 ids->driver_data != BROKEN_EEPROM_DRIVER_DATA)
262 return ids;
263 return NULL;
264 }
265
oxygen_restore_eeprom(struct oxygen * chip,const struct pci_device_id * id)266 static void oxygen_restore_eeprom(struct oxygen *chip,
267 const struct pci_device_id *id)
268 {
269 u16 eeprom_id;
270
271 eeprom_id = oxygen_read_eeprom(chip, 0);
272 if (eeprom_id != OXYGEN_EEPROM_ID &&
273 (eeprom_id != 0xffff || id->subdevice != 0x8788)) {
274 /*
275 * This function gets called only when a known card model has
276 * been detected, i.e., we know there is a valid subsystem
277 * product ID at index 2 in the EEPROM. Therefore, we have
278 * been able to deduce the correct subsystem vendor ID, and
279 * this is enough information to restore the original EEPROM
280 * contents.
281 */
282 oxygen_write_eeprom(chip, 1, id->subvendor);
283 oxygen_write_eeprom(chip, 0, OXYGEN_EEPROM_ID);
284
285 oxygen_set_bits8(chip, OXYGEN_MISC,
286 OXYGEN_MISC_WRITE_PCI_SUBID);
287 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID,
288 id->subvendor);
289 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_ID,
290 id->subdevice);
291 oxygen_clear_bits8(chip, OXYGEN_MISC,
292 OXYGEN_MISC_WRITE_PCI_SUBID);
293
294 dev_info(chip->card->dev, "EEPROM ID restored\n");
295 }
296 }
297
configure_pcie_bridge(struct pci_dev * pci)298 static void configure_pcie_bridge(struct pci_dev *pci)
299 {
300 enum { PEX811X, PI7C9X110, XIO2001 };
301 static const struct pci_device_id bridge_ids[] = {
302 { PCI_VDEVICE(PLX, 0x8111), .driver_data = PEX811X },
303 { PCI_VDEVICE(PLX, 0x8112), .driver_data = PEX811X },
304 { PCI_DEVICE(0x12d8, 0xe110), .driver_data = PI7C9X110 },
305 { PCI_VDEVICE(TI, 0x8240), .driver_data = XIO2001 },
306 { }
307 };
308 struct pci_dev *bridge;
309 const struct pci_device_id *id;
310 u32 tmp;
311
312 if (!pci->bus || !pci->bus->self)
313 return;
314 bridge = pci->bus->self;
315
316 id = pci_match_id(bridge_ids, bridge);
317 if (!id)
318 return;
319
320 switch (id->driver_data) {
321 case PEX811X: /* PLX PEX8111/PEX8112 PCIe/PCI bridge */
322 pci_read_config_dword(bridge, 0x48, &tmp);
323 tmp |= 1; /* enable blind prefetching */
324 tmp |= 1 << 11; /* enable beacon generation */
325 pci_write_config_dword(bridge, 0x48, tmp);
326
327 pci_write_config_dword(bridge, 0x84, 0x0c);
328 pci_read_config_dword(bridge, 0x88, &tmp);
329 tmp &= ~(7 << 27);
330 tmp |= 2 << 27; /* set prefetch size to 128 bytes */
331 pci_write_config_dword(bridge, 0x88, tmp);
332 break;
333
334 case PI7C9X110: /* Pericom PI7C9X110 PCIe/PCI bridge */
335 pci_read_config_dword(bridge, 0x40, &tmp);
336 tmp |= 1; /* park the PCI arbiter to the sound chip */
337 pci_write_config_dword(bridge, 0x40, tmp);
338 break;
339
340 case XIO2001: /* Texas Instruments XIO2001 PCIe/PCI bridge */
341 pci_read_config_dword(bridge, 0xe8, &tmp);
342 tmp &= ~0xf; /* request length limit: 64 bytes */
343 tmp &= ~(0xf << 8);
344 tmp |= 1 << 8; /* request count limit: one buffer */
345 pci_write_config_dword(bridge, 0xe8, tmp);
346 break;
347 }
348 }
349
oxygen_init(struct oxygen * chip)350 static void oxygen_init(struct oxygen *chip)
351 {
352 unsigned int i;
353
354 chip->dac_routing = 1;
355 for (i = 0; i < 8; ++i)
356 chip->dac_volume[i] = chip->model.dac_volume_min;
357 chip->dac_mute = 1;
358 chip->spdif_playback_enable = 0;
359 chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
360 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
361 chip->spdif_pcm_bits = chip->spdif_bits;
362
363 if (!(oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2))
364 oxygen_set_bits8(chip, OXYGEN_MISC,
365 OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
366
367 i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
368 chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
369 chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
370
371 oxygen_write8_masked(chip, OXYGEN_FUNCTION,
372 OXYGEN_FUNCTION_RESET_CODEC |
373 chip->model.function_flags,
374 OXYGEN_FUNCTION_RESET_CODEC |
375 OXYGEN_FUNCTION_2WIRE_SPI_MASK |
376 OXYGEN_FUNCTION_ENABLE_SPI_4_5);
377 oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
378 oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
379 oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
380 OXYGEN_PLAY_CHANNELS_2 |
381 OXYGEN_DMA_A_BURST_8 |
382 OXYGEN_DMA_MULTICH_BURST_8);
383 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
384 oxygen_write8_masked(chip, OXYGEN_MISC,
385 chip->model.misc_flags,
386 OXYGEN_MISC_WRITE_PCI_SUBID |
387 OXYGEN_MISC_REC_C_FROM_SPDIF |
388 OXYGEN_MISC_REC_B_FROM_AC97 |
389 OXYGEN_MISC_REC_A_FROM_MULTICH |
390 OXYGEN_MISC_MIDI);
391 oxygen_write8(chip, OXYGEN_REC_FORMAT,
392 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
393 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
394 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
395 oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
396 (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
397 (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
398 oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
399 oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
400 OXYGEN_RATE_48000 |
401 chip->model.dac_i2s_format |
402 OXYGEN_I2S_MCLK(chip->model.dac_mclks) |
403 OXYGEN_I2S_BITS_16 |
404 OXYGEN_I2S_MASTER |
405 OXYGEN_I2S_BCLK_64);
406 if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
407 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
408 OXYGEN_RATE_48000 |
409 chip->model.adc_i2s_format |
410 OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
411 OXYGEN_I2S_BITS_16 |
412 OXYGEN_I2S_MASTER |
413 OXYGEN_I2S_BCLK_64);
414 else
415 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
416 OXYGEN_I2S_MASTER |
417 OXYGEN_I2S_MUTE_MCLK);
418 if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 |
419 CAPTURE_2_FROM_I2S_2))
420 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
421 OXYGEN_RATE_48000 |
422 chip->model.adc_i2s_format |
423 OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
424 OXYGEN_I2S_BITS_16 |
425 OXYGEN_I2S_MASTER |
426 OXYGEN_I2S_BCLK_64);
427 else
428 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
429 OXYGEN_I2S_MASTER |
430 OXYGEN_I2S_MUTE_MCLK);
431 if (chip->model.device_config & CAPTURE_3_FROM_I2S_3)
432 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
433 OXYGEN_RATE_48000 |
434 chip->model.adc_i2s_format |
435 OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
436 OXYGEN_I2S_BITS_16 |
437 OXYGEN_I2S_MASTER |
438 OXYGEN_I2S_BCLK_64);
439 else
440 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
441 OXYGEN_I2S_MASTER |
442 OXYGEN_I2S_MUTE_MCLK);
443 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
444 OXYGEN_SPDIF_OUT_ENABLE |
445 OXYGEN_SPDIF_LOOPBACK);
446 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
447 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
448 OXYGEN_SPDIF_SENSE_MASK |
449 OXYGEN_SPDIF_LOCK_MASK |
450 OXYGEN_SPDIF_RATE_MASK |
451 OXYGEN_SPDIF_LOCK_PAR |
452 OXYGEN_SPDIF_IN_CLOCK_96,
453 OXYGEN_SPDIF_SENSE_MASK |
454 OXYGEN_SPDIF_LOCK_MASK |
455 OXYGEN_SPDIF_RATE_MASK |
456 OXYGEN_SPDIF_SENSE_PAR |
457 OXYGEN_SPDIF_LOCK_PAR |
458 OXYGEN_SPDIF_IN_CLOCK_MASK);
459 else
460 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
461 OXYGEN_SPDIF_SENSE_MASK |
462 OXYGEN_SPDIF_LOCK_MASK |
463 OXYGEN_SPDIF_RATE_MASK);
464 oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
465 oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS,
466 OXYGEN_2WIRE_LENGTH_8 |
467 OXYGEN_2WIRE_INTERRUPT_MASK |
468 OXYGEN_2WIRE_SPEED_STANDARD);
469 oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
470 oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
471 oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
472 oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
473 OXYGEN_PLAY_MULTICH_I2S_DAC |
474 OXYGEN_PLAY_SPDIF_SPDIF |
475 (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
476 (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
477 (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
478 (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
479 oxygen_write8(chip, OXYGEN_REC_ROUTING,
480 OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
481 OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
482 OXYGEN_REC_C_ROUTE_SPDIF);
483 oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
484 oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
485 (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
486 (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
487 (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
488 (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
489
490 if (chip->has_ac97_0 | chip->has_ac97_1)
491 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK,
492 OXYGEN_AC97_INT_READ_DONE |
493 OXYGEN_AC97_INT_WRITE_DONE);
494 else
495 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
496 oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
497 oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
498 if (!(chip->has_ac97_0 | chip->has_ac97_1))
499 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
500 OXYGEN_AC97_CLOCK_DISABLE);
501 if (!chip->has_ac97_0) {
502 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
503 OXYGEN_AC97_NO_CODEC_0);
504 } else {
505 oxygen_write_ac97(chip, 0, AC97_RESET, 0);
506 msleep(1);
507 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
508 CM9780_GPIO0IO | CM9780_GPIO1IO);
509 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
510 CM9780_BSTSEL | CM9780_STRO_MIC |
511 CM9780_MIX2FR | CM9780_PCBSW);
512 oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
513 CM9780_RSOE | CM9780_CBOE |
514 CM9780_SSOE | CM9780_FROE |
515 CM9780_MIC2MIC | CM9780_LI2LI);
516 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
517 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
518 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
519 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
520 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
521 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
522 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
523 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
524 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
525 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
526 oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS,
527 CM9780_GPO0);
528 /* power down unused ADCs and DACs */
529 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
530 AC97_PD_PR0 | AC97_PD_PR1);
531 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
532 AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
533 }
534 if (chip->has_ac97_1) {
535 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
536 OXYGEN_AC97_CODEC1_SLOT3 |
537 OXYGEN_AC97_CODEC1_SLOT4);
538 oxygen_write_ac97(chip, 1, AC97_RESET, 0);
539 msleep(1);
540 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
541 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
542 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
543 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
544 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
545 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
546 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
547 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
548 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
549 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
550 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000);
551 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
552 }
553 }
554
oxygen_shutdown(struct oxygen * chip)555 static void oxygen_shutdown(struct oxygen *chip)
556 {
557 guard(spinlock_irq)(&chip->reg_lock);
558 chip->interrupt_mask = 0;
559 chip->pcm_running = 0;
560 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
561 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
562 }
563
oxygen_card_free(struct snd_card * card)564 static void oxygen_card_free(struct snd_card *card)
565 {
566 struct oxygen *chip = card->private_data;
567
568 oxygen_shutdown(chip);
569 flush_work(&chip->spdif_input_bits_work);
570 flush_work(&chip->gpio_work);
571 chip->model.cleanup(chip);
572 mutex_destroy(&chip->mutex);
573 }
574
__oxygen_pci_probe(struct pci_dev * pci,int index,char * id,struct module * owner,const struct pci_device_id * ids,int (* get_model)(struct oxygen * chip,const struct pci_device_id * id))575 static int __oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
576 struct module *owner,
577 const struct pci_device_id *ids,
578 int (*get_model)(struct oxygen *chip,
579 const struct pci_device_id *id
580 )
581 )
582 {
583 struct snd_card *card;
584 struct oxygen *chip;
585 const struct pci_device_id *pci_id;
586 int err;
587
588 err = snd_devm_card_new(&pci->dev, index, id, owner,
589 sizeof(*chip), &card);
590 if (err < 0)
591 return err;
592
593 chip = card->private_data;
594 chip->card = card;
595 chip->pci = pci;
596 chip->irq = -1;
597 spin_lock_init(&chip->reg_lock);
598 mutex_init(&chip->mutex);
599 INIT_WORK(&chip->spdif_input_bits_work,
600 oxygen_spdif_input_bits_changed);
601 INIT_WORK(&chip->gpio_work, oxygen_gpio_changed);
602 init_waitqueue_head(&chip->ac97_waitqueue);
603
604 err = pcim_enable_device(pci);
605 if (err < 0)
606 return err;
607
608 err = pcim_request_all_regions(pci, DRIVER);
609 if (err < 0) {
610 dev_err(card->dev, "cannot reserve PCI resources\n");
611 return err;
612 }
613
614 if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
615 pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) {
616 dev_err(card->dev, "invalid PCI I/O range\n");
617 return -ENXIO;
618 }
619 chip->addr = pci_resource_start(pci, 0);
620
621 pci_id = oxygen_search_pci_id(chip, ids);
622 if (!pci_id)
623 return -ENODEV;
624
625 oxygen_restore_eeprom(chip, pci_id);
626 err = get_model(chip, pci_id);
627 if (err < 0)
628 return err;
629
630 if (chip->model.model_data_size) {
631 chip->model_data = devm_kzalloc(&pci->dev,
632 chip->model.model_data_size,
633 GFP_KERNEL);
634 if (!chip->model_data)
635 return -ENOMEM;
636 }
637
638 pci_set_master(pci);
639 card->private_free = oxygen_card_free;
640
641 configure_pcie_bridge(pci);
642 oxygen_init(chip);
643 chip->model.init(chip);
644
645 err = devm_request_irq(&pci->dev, pci->irq, oxygen_interrupt,
646 IRQF_SHARED, KBUILD_MODNAME, chip);
647 if (err < 0) {
648 dev_err(card->dev, "cannot grab interrupt %d\n", pci->irq);
649 return err;
650 }
651 chip->irq = pci->irq;
652 card->sync_irq = chip->irq;
653
654 strscpy(card->driver, chip->model.chip);
655 strscpy(card->shortname, chip->model.shortname);
656 sprintf(card->longname, "%s at %#lx, irq %i",
657 chip->model.longname, chip->addr, chip->irq);
658 strscpy(card->mixername, chip->model.chip);
659 snd_component_add(card, chip->model.chip);
660
661 err = oxygen_pcm_init(chip);
662 if (err < 0)
663 return err;
664
665 err = oxygen_mixer_init(chip);
666 if (err < 0)
667 return err;
668
669 if (chip->model.device_config & (MIDI_OUTPUT | MIDI_INPUT)) {
670 unsigned int info_flags =
671 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK;
672 if (chip->model.device_config & MIDI_OUTPUT)
673 info_flags |= MPU401_INFO_OUTPUT;
674 if (chip->model.device_config & MIDI_INPUT)
675 info_flags |= MPU401_INFO_INPUT;
676 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
677 chip->addr + OXYGEN_MPU401,
678 info_flags, -1, &chip->midi);
679 if (err < 0)
680 return err;
681 }
682
683 oxygen_proc_init(chip);
684
685 scoped_guard(spinlock_irq, &chip->reg_lock) {
686 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
687 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
688 if (chip->has_ac97_0 | chip->has_ac97_1)
689 chip->interrupt_mask |= OXYGEN_INT_AC97;
690 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
691 }
692
693 err = snd_card_register(card);
694 if (err < 0)
695 return err;
696
697 pci_set_drvdata(pci, card);
698 return 0;
699 }
700
oxygen_pci_probe(struct pci_dev * pci,int index,char * id,struct module * owner,const struct pci_device_id * ids,int (* get_model)(struct oxygen * chip,const struct pci_device_id * id))701 int oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
702 struct module *owner,
703 const struct pci_device_id *ids,
704 int (*get_model)(struct oxygen *chip,
705 const struct pci_device_id *id))
706 {
707 return snd_card_free_on_error(&pci->dev,
708 __oxygen_pci_probe(pci, index, id, owner, ids, get_model));
709 }
710 EXPORT_SYMBOL(oxygen_pci_probe);
711
oxygen_pci_suspend(struct device * dev)712 static int oxygen_pci_suspend(struct device *dev)
713 {
714 struct snd_card *card = dev_get_drvdata(dev);
715 struct oxygen *chip = card->private_data;
716 unsigned int saved_interrupt_mask;
717
718 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
719
720 if (chip->model.suspend)
721 chip->model.suspend(chip);
722
723 scoped_guard(spinlock_irq, &chip->reg_lock) {
724 saved_interrupt_mask = chip->interrupt_mask;
725 chip->interrupt_mask = 0;
726 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
727 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
728 }
729
730 flush_work(&chip->spdif_input_bits_work);
731 flush_work(&chip->gpio_work);
732 chip->interrupt_mask = saved_interrupt_mask;
733 return 0;
734 }
735
736 static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = {
737 0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff,
738 0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000
739 };
740 static const u32 ac97_registers_to_restore[2][0x40 / 32] = {
741 { 0x18284fa2, 0x03060000 },
742 { 0x00007fa6, 0x00200000 }
743 };
744
is_bit_set(const u32 * bitmap,unsigned int bit)745 static inline int is_bit_set(const u32 *bitmap, unsigned int bit)
746 {
747 return bitmap[bit / 32] & (1 << (bit & 31));
748 }
749
oxygen_restore_ac97(struct oxygen * chip,unsigned int codec)750 static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec)
751 {
752 unsigned int i;
753
754 oxygen_write_ac97(chip, codec, AC97_RESET, 0);
755 msleep(1);
756 for (i = 1; i < 0x40; ++i)
757 if (is_bit_set(ac97_registers_to_restore[codec], i))
758 oxygen_write_ac97(chip, codec, i * 2,
759 chip->saved_ac97_registers[codec][i]);
760 }
761
oxygen_pci_resume(struct device * dev)762 static int oxygen_pci_resume(struct device *dev)
763 {
764 struct snd_card *card = dev_get_drvdata(dev);
765 struct oxygen *chip = card->private_data;
766 unsigned int i;
767
768 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
769 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
770 for (i = 0; i < OXYGEN_IO_SIZE; ++i)
771 if (is_bit_set(registers_to_restore, i))
772 oxygen_write8(chip, i, chip->saved_registers._8[i]);
773 if (chip->has_ac97_0)
774 oxygen_restore_ac97(chip, 0);
775 if (chip->has_ac97_1)
776 oxygen_restore_ac97(chip, 1);
777
778 if (chip->model.resume)
779 chip->model.resume(chip);
780
781 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
782
783 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
784 return 0;
785 }
786
787 EXPORT_SIMPLE_DEV_PM_OPS(oxygen_pci_pm, oxygen_pci_suspend, oxygen_pci_resume);
788
oxygen_pci_shutdown(struct pci_dev * pci)789 void oxygen_pci_shutdown(struct pci_dev *pci)
790 {
791 struct snd_card *card = pci_get_drvdata(pci);
792 struct oxygen *chip = card->private_data;
793
794 oxygen_shutdown(chip);
795 chip->model.cleanup(chip);
796 }
797 EXPORT_SYMBOL(oxygen_pci_shutdown);
798