1 /*
2  * drivers/mmc/host/omap_hsmmc.c
3  *
4  * Driver for OMAP2430/3430 MMC controller.
5  *
6  * Copyright (C) 2007 Texas Instruments.
7  *
8  * Authors:
9  *	Syed Mohammed Khasim	<x0khasim@ti.com>
10  *	Madhusudhan		<madhu.cr@ti.com>
11  *	Mohit Jalori		<mjalori@ti.com>
12  *
13  * This file is licensed under the terms of the GNU General Public License
14  * version 2. This program is licensed "as is" without any warranty of any
15  * kind, whether express or implied.
16  */
17 
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/timer.h>
28 #include <linux/clk.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/core.h>
31 #include <linux/mmc/mmc.h>
32 #include <linux/io.h>
33 #include <linux/semaphore.h>
34 #include <linux/gpio.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/pm_runtime.h>
37 #include <plat/dma.h>
38 #include <mach/hardware.h>
39 #include <plat/board.h>
40 #include <plat/mmc.h>
41 #include <plat/cpu.h>
42 
43 /* OMAP HSMMC Host Controller Registers */
44 #define OMAP_HSMMC_SYSCONFIG	0x0010
45 #define OMAP_HSMMC_SYSSTATUS	0x0014
46 #define OMAP_HSMMC_CON		0x002C
47 #define OMAP_HSMMC_BLK		0x0104
48 #define OMAP_HSMMC_ARG		0x0108
49 #define OMAP_HSMMC_CMD		0x010C
50 #define OMAP_HSMMC_RSP10	0x0110
51 #define OMAP_HSMMC_RSP32	0x0114
52 #define OMAP_HSMMC_RSP54	0x0118
53 #define OMAP_HSMMC_RSP76	0x011C
54 #define OMAP_HSMMC_DATA		0x0120
55 #define OMAP_HSMMC_HCTL		0x0128
56 #define OMAP_HSMMC_SYSCTL	0x012C
57 #define OMAP_HSMMC_STAT		0x0130
58 #define OMAP_HSMMC_IE		0x0134
59 #define OMAP_HSMMC_ISE		0x0138
60 #define OMAP_HSMMC_CAPA		0x0140
61 
62 #define VS18			(1 << 26)
63 #define VS30			(1 << 25)
64 #define SDVS18			(0x5 << 9)
65 #define SDVS30			(0x6 << 9)
66 #define SDVS33			(0x7 << 9)
67 #define SDVS_MASK		0x00000E00
68 #define SDVSCLR			0xFFFFF1FF
69 #define SDVSDET			0x00000400
70 #define AUTOIDLE		0x1
71 #define SDBP			(1 << 8)
72 #define DTO			0xe
73 #define ICE			0x1
74 #define ICS			0x2
75 #define CEN			(1 << 2)
76 #define CLKD_MASK		0x0000FFC0
77 #define CLKD_SHIFT		6
78 #define DTO_MASK		0x000F0000
79 #define DTO_SHIFT		16
80 #define INT_EN_MASK		0x307F0033
81 #define BWR_ENABLE		(1 << 4)
82 #define BRR_ENABLE		(1 << 5)
83 #define DTO_ENABLE		(1 << 20)
84 #define INIT_STREAM		(1 << 1)
85 #define DP_SELECT		(1 << 21)
86 #define DDIR			(1 << 4)
87 #define DMA_EN			0x1
88 #define MSBS			(1 << 5)
89 #define BCE			(1 << 1)
90 #define FOUR_BIT		(1 << 1)
91 #define DW8			(1 << 5)
92 #define CC			0x1
93 #define TC			0x02
94 #define OD			0x1
95 #define ERR			(1 << 15)
96 #define CMD_TIMEOUT		(1 << 16)
97 #define DATA_TIMEOUT		(1 << 20)
98 #define CMD_CRC			(1 << 17)
99 #define DATA_CRC		(1 << 21)
100 #define CARD_ERR		(1 << 28)
101 #define STAT_CLEAR		0xFFFFFFFF
102 #define INIT_STREAM_CMD		0x00000000
103 #define DUAL_VOLT_OCR_BIT	7
104 #define SRC			(1 << 25)
105 #define SRD			(1 << 26)
106 #define SOFTRESET		(1 << 1)
107 #define RESETDONE		(1 << 0)
108 
109 /*
110  * FIXME: Most likely all the data using these _DEVID defines should come
111  * from the platform_data, or implemented in controller and slot specific
112  * functions.
113  */
114 #define OMAP_MMC1_DEVID		0
115 #define OMAP_MMC2_DEVID		1
116 #define OMAP_MMC3_DEVID		2
117 #define OMAP_MMC4_DEVID		3
118 #define OMAP_MMC5_DEVID		4
119 
120 #define MMC_AUTOSUSPEND_DELAY	100
121 #define MMC_TIMEOUT_MS		20
122 #define OMAP_MMC_MIN_CLOCK	400000
123 #define OMAP_MMC_MAX_CLOCK	52000000
124 #define DRIVER_NAME		"omap_hsmmc"
125 
126 /*
127  * One controller can have multiple slots, like on some omap boards using
128  * omap.c controller driver. Luckily this is not currently done on any known
129  * omap_hsmmc.c device.
130  */
131 #define mmc_slot(host)		(host->pdata->slots[host->slot_id])
132 
133 /*
134  * MMC Host controller read/write API's
135  */
136 #define OMAP_HSMMC_READ(base, reg)	\
137 	__raw_readl((base) + OMAP_HSMMC_##reg)
138 
139 #define OMAP_HSMMC_WRITE(base, reg, val) \
140 	__raw_writel((val), (base) + OMAP_HSMMC_##reg)
141 
142 struct omap_hsmmc_next {
143 	unsigned int	dma_len;
144 	s32		cookie;
145 };
146 
147 struct omap_hsmmc_host {
148 	struct	device		*dev;
149 	struct	mmc_host	*mmc;
150 	struct	mmc_request	*mrq;
151 	struct	mmc_command	*cmd;
152 	struct	mmc_data	*data;
153 	struct	clk		*fclk;
154 	struct	clk		*dbclk;
155 	/*
156 	 * vcc == configured supply
157 	 * vcc_aux == optional
158 	 *   -	MMC1, supply for DAT4..DAT7
159 	 *   -	MMC2/MMC2, external level shifter voltage supply, for
160 	 *	chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
161 	 */
162 	struct	regulator	*vcc;
163 	struct	regulator	*vcc_aux;
164 	void	__iomem		*base;
165 	resource_size_t		mapbase;
166 	spinlock_t		irq_lock; /* Prevent races with irq handler */
167 	unsigned int		id;
168 	unsigned int		dma_len;
169 	unsigned int		dma_sg_idx;
170 	unsigned char		bus_mode;
171 	unsigned char		power_mode;
172 	u32			*buffer;
173 	u32			bytesleft;
174 	int			suspended;
175 	int			irq;
176 	int			use_dma, dma_ch;
177 	int			dma_line_tx, dma_line_rx;
178 	int			slot_id;
179 	int			got_dbclk;
180 	int			response_busy;
181 	int			context_loss;
182 	int			dpm_state;
183 	int			vdd;
184 	int			protect_card;
185 	int			reqs_blocked;
186 	int			use_reg;
187 	int			req_in_progress;
188 	struct omap_hsmmc_next	next_data;
189 
190 	struct	omap_mmc_platform_data	*pdata;
191 };
192 
omap_hsmmc_card_detect(struct device * dev,int slot)193 static int omap_hsmmc_card_detect(struct device *dev, int slot)
194 {
195 	struct omap_mmc_platform_data *mmc = dev->platform_data;
196 
197 	/* NOTE: assumes card detect signal is active-low */
198 	return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
199 }
200 
omap_hsmmc_get_wp(struct device * dev,int slot)201 static int omap_hsmmc_get_wp(struct device *dev, int slot)
202 {
203 	struct omap_mmc_platform_data *mmc = dev->platform_data;
204 
205 	/* NOTE: assumes write protect signal is active-high */
206 	return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
207 }
208 
omap_hsmmc_get_cover_state(struct device * dev,int slot)209 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
210 {
211 	struct omap_mmc_platform_data *mmc = dev->platform_data;
212 
213 	/* NOTE: assumes card detect signal is active-low */
214 	return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
215 }
216 
217 #ifdef CONFIG_PM
218 
omap_hsmmc_suspend_cdirq(struct device * dev,int slot)219 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
220 {
221 	struct omap_mmc_platform_data *mmc = dev->platform_data;
222 
223 	disable_irq(mmc->slots[0].card_detect_irq);
224 	return 0;
225 }
226 
omap_hsmmc_resume_cdirq(struct device * dev,int slot)227 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
228 {
229 	struct omap_mmc_platform_data *mmc = dev->platform_data;
230 
231 	enable_irq(mmc->slots[0].card_detect_irq);
232 	return 0;
233 }
234 
235 #else
236 
237 #define omap_hsmmc_suspend_cdirq	NULL
238 #define omap_hsmmc_resume_cdirq		NULL
239 
240 #endif
241 
242 #ifdef CONFIG_REGULATOR
243 
omap_hsmmc_1_set_power(struct device * dev,int slot,int power_on,int vdd)244 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
245 				  int vdd)
246 {
247 	struct omap_hsmmc_host *host =
248 		platform_get_drvdata(to_platform_device(dev));
249 	int ret;
250 
251 	if (mmc_slot(host).before_set_reg)
252 		mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
253 
254 	if (power_on)
255 		ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
256 	else
257 		ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
258 
259 	if (mmc_slot(host).after_set_reg)
260 		mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
261 
262 	return ret;
263 }
264 
omap_hsmmc_235_set_power(struct device * dev,int slot,int power_on,int vdd)265 static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
266 				   int vdd)
267 {
268 	struct omap_hsmmc_host *host =
269 		platform_get_drvdata(to_platform_device(dev));
270 	int ret = 0;
271 
272 	/*
273 	 * If we don't see a Vcc regulator, assume it's a fixed
274 	 * voltage always-on regulator.
275 	 */
276 	if (!host->vcc)
277 		return 0;
278 
279 	if (mmc_slot(host).before_set_reg)
280 		mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
281 
282 	/*
283 	 * Assume Vcc regulator is used only to power the card ... OMAP
284 	 * VDDS is used to power the pins, optionally with a transceiver to
285 	 * support cards using voltages other than VDDS (1.8V nominal).  When a
286 	 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
287 	 *
288 	 * In some cases this regulator won't support enable/disable;
289 	 * e.g. it's a fixed rail for a WLAN chip.
290 	 *
291 	 * In other cases vcc_aux switches interface power.  Example, for
292 	 * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
293 	 * chips/cards need an interface voltage rail too.
294 	 */
295 	if (power_on) {
296 		ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
297 		/* Enable interface voltage rail, if needed */
298 		if (ret == 0 && host->vcc_aux) {
299 			ret = regulator_enable(host->vcc_aux);
300 			if (ret < 0)
301 				ret = mmc_regulator_set_ocr(host->mmc,
302 							host->vcc, 0);
303 		}
304 	} else {
305 		/* Shut down the rail */
306 		if (host->vcc_aux)
307 			ret = regulator_disable(host->vcc_aux);
308 		if (!ret) {
309 			/* Then proceed to shut down the local regulator */
310 			ret = mmc_regulator_set_ocr(host->mmc,
311 						host->vcc, 0);
312 		}
313 	}
314 
315 	if (mmc_slot(host).after_set_reg)
316 		mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
317 
318 	return ret;
319 }
320 
omap_hsmmc_4_set_power(struct device * dev,int slot,int power_on,int vdd)321 static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
322 					int vdd)
323 {
324 	return 0;
325 }
326 
omap_hsmmc_1_set_sleep(struct device * dev,int slot,int sleep,int vdd,int cardsleep)327 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
328 				  int vdd, int cardsleep)
329 {
330 	struct omap_hsmmc_host *host =
331 		platform_get_drvdata(to_platform_device(dev));
332 	int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
333 
334 	return regulator_set_mode(host->vcc, mode);
335 }
336 
omap_hsmmc_235_set_sleep(struct device * dev,int slot,int sleep,int vdd,int cardsleep)337 static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
338 				   int vdd, int cardsleep)
339 {
340 	struct omap_hsmmc_host *host =
341 		platform_get_drvdata(to_platform_device(dev));
342 	int err, mode;
343 
344 	/*
345 	 * If we don't see a Vcc regulator, assume it's a fixed
346 	 * voltage always-on regulator.
347 	 */
348 	if (!host->vcc)
349 		return 0;
350 
351 	mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
352 
353 	if (!host->vcc_aux)
354 		return regulator_set_mode(host->vcc, mode);
355 
356 	if (cardsleep) {
357 		/* VCC can be turned off if card is asleep */
358 		if (sleep)
359 			err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
360 		else
361 			err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
362 	} else
363 		err = regulator_set_mode(host->vcc, mode);
364 	if (err)
365 		return err;
366 
367 	if (!mmc_slot(host).vcc_aux_disable_is_sleep)
368 		return regulator_set_mode(host->vcc_aux, mode);
369 
370 	if (sleep)
371 		return regulator_disable(host->vcc_aux);
372 	else
373 		return regulator_enable(host->vcc_aux);
374 }
375 
omap_hsmmc_4_set_sleep(struct device * dev,int slot,int sleep,int vdd,int cardsleep)376 static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
377 					int vdd, int cardsleep)
378 {
379 	return 0;
380 }
381 
omap_hsmmc_reg_get(struct omap_hsmmc_host * host)382 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
383 {
384 	struct regulator *reg;
385 	int ret = 0;
386 	int ocr_value = 0;
387 
388 	switch (host->id) {
389 	case OMAP_MMC1_DEVID:
390 		/* On-chip level shifting via PBIAS0/PBIAS1 */
391 		mmc_slot(host).set_power = omap_hsmmc_1_set_power;
392 		mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
393 		break;
394 	case OMAP_MMC2_DEVID:
395 	case OMAP_MMC3_DEVID:
396 	case OMAP_MMC5_DEVID:
397 		/* Off-chip level shifting, or none */
398 		mmc_slot(host).set_power = omap_hsmmc_235_set_power;
399 		mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
400 		break;
401 	case OMAP_MMC4_DEVID:
402 		mmc_slot(host).set_power = omap_hsmmc_4_set_power;
403 		mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
404 	default:
405 		pr_err("MMC%d configuration not supported!\n", host->id);
406 		return -EINVAL;
407 	}
408 
409 	reg = regulator_get(host->dev, "vmmc");
410 	if (IS_ERR(reg)) {
411 		dev_dbg(host->dev, "vmmc regulator missing\n");
412 		/*
413 		* HACK: until fixed.c regulator is usable,
414 		* we don't require a main regulator
415 		* for MMC2 or MMC3
416 		*/
417 		if (host->id == OMAP_MMC1_DEVID) {
418 			ret = PTR_ERR(reg);
419 			goto err;
420 		}
421 	} else {
422 		host->vcc = reg;
423 		ocr_value = mmc_regulator_get_ocrmask(reg);
424 		if (!mmc_slot(host).ocr_mask) {
425 			mmc_slot(host).ocr_mask = ocr_value;
426 		} else {
427 			if (!(mmc_slot(host).ocr_mask & ocr_value)) {
428 				pr_err("MMC%d ocrmask %x is not supported\n",
429 					host->id, mmc_slot(host).ocr_mask);
430 				mmc_slot(host).ocr_mask = 0;
431 				return -EINVAL;
432 			}
433 		}
434 
435 		/* Allow an aux regulator */
436 		reg = regulator_get(host->dev, "vmmc_aux");
437 		host->vcc_aux = IS_ERR(reg) ? NULL : reg;
438 
439 		/* For eMMC do not power off when not in sleep state */
440 		if (mmc_slot(host).no_regulator_off_init)
441 			return 0;
442 		/*
443 		* UGLY HACK:  workaround regulator framework bugs.
444 		* When the bootloader leaves a supply active, it's
445 		* initialized with zero usecount ... and we can't
446 		* disable it without first enabling it.  Until the
447 		* framework is fixed, we need a workaround like this
448 		* (which is safe for MMC, but not in general).
449 		*/
450 		if (regulator_is_enabled(host->vcc) > 0 ||
451 		    (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
452 			int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
453 
454 			mmc_slot(host).set_power(host->dev, host->slot_id,
455 						 1, vdd);
456 			mmc_slot(host).set_power(host->dev, host->slot_id,
457 						 0, 0);
458 		}
459 	}
460 
461 	return 0;
462 
463 err:
464 	mmc_slot(host).set_power = NULL;
465 	mmc_slot(host).set_sleep = NULL;
466 	return ret;
467 }
468 
omap_hsmmc_reg_put(struct omap_hsmmc_host * host)469 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
470 {
471 	regulator_put(host->vcc);
472 	regulator_put(host->vcc_aux);
473 	mmc_slot(host).set_power = NULL;
474 	mmc_slot(host).set_sleep = NULL;
475 }
476 
omap_hsmmc_have_reg(void)477 static inline int omap_hsmmc_have_reg(void)
478 {
479 	return 1;
480 }
481 
482 #else
483 
omap_hsmmc_reg_get(struct omap_hsmmc_host * host)484 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
485 {
486 	return -EINVAL;
487 }
488 
omap_hsmmc_reg_put(struct omap_hsmmc_host * host)489 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
490 {
491 }
492 
omap_hsmmc_have_reg(void)493 static inline int omap_hsmmc_have_reg(void)
494 {
495 	return 0;
496 }
497 
498 #endif
499 
omap_hsmmc_gpio_init(struct omap_mmc_platform_data * pdata)500 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
501 {
502 	int ret;
503 
504 	if (gpio_is_valid(pdata->slots[0].switch_pin)) {
505 		if (pdata->slots[0].cover)
506 			pdata->slots[0].get_cover_state =
507 					omap_hsmmc_get_cover_state;
508 		else
509 			pdata->slots[0].card_detect = omap_hsmmc_card_detect;
510 		pdata->slots[0].card_detect_irq =
511 				gpio_to_irq(pdata->slots[0].switch_pin);
512 		ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
513 		if (ret)
514 			return ret;
515 		ret = gpio_direction_input(pdata->slots[0].switch_pin);
516 		if (ret)
517 			goto err_free_sp;
518 	} else
519 		pdata->slots[0].switch_pin = -EINVAL;
520 
521 	if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
522 		pdata->slots[0].get_ro = omap_hsmmc_get_wp;
523 		ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
524 		if (ret)
525 			goto err_free_cd;
526 		ret = gpio_direction_input(pdata->slots[0].gpio_wp);
527 		if (ret)
528 			goto err_free_wp;
529 	} else
530 		pdata->slots[0].gpio_wp = -EINVAL;
531 
532 	return 0;
533 
534 err_free_wp:
535 	gpio_free(pdata->slots[0].gpio_wp);
536 err_free_cd:
537 	if (gpio_is_valid(pdata->slots[0].switch_pin))
538 err_free_sp:
539 		gpio_free(pdata->slots[0].switch_pin);
540 	return ret;
541 }
542 
omap_hsmmc_gpio_free(struct omap_mmc_platform_data * pdata)543 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
544 {
545 	if (gpio_is_valid(pdata->slots[0].gpio_wp))
546 		gpio_free(pdata->slots[0].gpio_wp);
547 	if (gpio_is_valid(pdata->slots[0].switch_pin))
548 		gpio_free(pdata->slots[0].switch_pin);
549 }
550 
551 /*
552  * Start clock to the card
553  */
omap_hsmmc_start_clock(struct omap_hsmmc_host * host)554 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
555 {
556 	OMAP_HSMMC_WRITE(host->base, SYSCTL,
557 		OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
558 }
559 
560 /*
561  * Stop clock to the card
562  */
omap_hsmmc_stop_clock(struct omap_hsmmc_host * host)563 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
564 {
565 	OMAP_HSMMC_WRITE(host->base, SYSCTL,
566 		OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
567 	if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
568 		dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
569 }
570 
omap_hsmmc_enable_irq(struct omap_hsmmc_host * host,struct mmc_command * cmd)571 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
572 				  struct mmc_command *cmd)
573 {
574 	unsigned int irq_mask;
575 
576 	if (host->use_dma)
577 		irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
578 	else
579 		irq_mask = INT_EN_MASK;
580 
581 	/* Disable timeout for erases */
582 	if (cmd->opcode == MMC_ERASE)
583 		irq_mask &= ~DTO_ENABLE;
584 
585 	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
586 	OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
587 	OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
588 }
589 
omap_hsmmc_disable_irq(struct omap_hsmmc_host * host)590 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
591 {
592 	OMAP_HSMMC_WRITE(host->base, ISE, 0);
593 	OMAP_HSMMC_WRITE(host->base, IE, 0);
594 	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
595 }
596 
597 /* Calculate divisor for the given clock frequency */
calc_divisor(struct omap_hsmmc_host * host,struct mmc_ios * ios)598 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
599 {
600 	u16 dsor = 0;
601 
602 	if (ios->clock) {
603 		dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
604 		if (dsor > 250)
605 			dsor = 250;
606 	}
607 
608 	return dsor;
609 }
610 
omap_hsmmc_set_clock(struct omap_hsmmc_host * host)611 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
612 {
613 	struct mmc_ios *ios = &host->mmc->ios;
614 	unsigned long regval;
615 	unsigned long timeout;
616 
617 	dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
618 
619 	omap_hsmmc_stop_clock(host);
620 
621 	regval = OMAP_HSMMC_READ(host->base, SYSCTL);
622 	regval = regval & ~(CLKD_MASK | DTO_MASK);
623 	regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
624 	OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
625 	OMAP_HSMMC_WRITE(host->base, SYSCTL,
626 		OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
627 
628 	/* Wait till the ICS bit is set */
629 	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
630 	while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
631 		&& time_before(jiffies, timeout))
632 		cpu_relax();
633 
634 	omap_hsmmc_start_clock(host);
635 }
636 
omap_hsmmc_set_bus_width(struct omap_hsmmc_host * host)637 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
638 {
639 	struct mmc_ios *ios = &host->mmc->ios;
640 	u32 con;
641 
642 	con = OMAP_HSMMC_READ(host->base, CON);
643 	switch (ios->bus_width) {
644 	case MMC_BUS_WIDTH_8:
645 		OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
646 		break;
647 	case MMC_BUS_WIDTH_4:
648 		OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
649 		OMAP_HSMMC_WRITE(host->base, HCTL,
650 			OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
651 		break;
652 	case MMC_BUS_WIDTH_1:
653 		OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
654 		OMAP_HSMMC_WRITE(host->base, HCTL,
655 			OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
656 		break;
657 	}
658 }
659 
omap_hsmmc_set_bus_mode(struct omap_hsmmc_host * host)660 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
661 {
662 	struct mmc_ios *ios = &host->mmc->ios;
663 	u32 con;
664 
665 	con = OMAP_HSMMC_READ(host->base, CON);
666 	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
667 		OMAP_HSMMC_WRITE(host->base, CON, con | OD);
668 	else
669 		OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
670 }
671 
672 #ifdef CONFIG_PM
673 
674 /*
675  * Restore the MMC host context, if it was lost as result of a
676  * power state change.
677  */
omap_hsmmc_context_restore(struct omap_hsmmc_host * host)678 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
679 {
680 	struct mmc_ios *ios = &host->mmc->ios;
681 	struct omap_mmc_platform_data *pdata = host->pdata;
682 	int context_loss = 0;
683 	u32 hctl, capa;
684 	unsigned long timeout;
685 
686 	if (pdata->get_context_loss_count) {
687 		context_loss = pdata->get_context_loss_count(host->dev);
688 		if (context_loss < 0)
689 			return 1;
690 	}
691 
692 	dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
693 		context_loss == host->context_loss ? "not " : "");
694 	if (host->context_loss == context_loss)
695 		return 1;
696 
697 	/* Wait for hardware reset */
698 	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
699 	while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
700 		&& time_before(jiffies, timeout))
701 		;
702 
703 	/* Do software reset */
704 	OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
705 	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
706 	while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
707 		&& time_before(jiffies, timeout))
708 		;
709 
710 	OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
711 			OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
712 
713 	if (host->id == OMAP_MMC1_DEVID) {
714 		if (host->power_mode != MMC_POWER_OFF &&
715 		    (1 << ios->vdd) <= MMC_VDD_23_24)
716 			hctl = SDVS18;
717 		else
718 			hctl = SDVS30;
719 		capa = VS30 | VS18;
720 	} else {
721 		hctl = SDVS18;
722 		capa = VS18;
723 	}
724 
725 	OMAP_HSMMC_WRITE(host->base, HCTL,
726 			OMAP_HSMMC_READ(host->base, HCTL) | hctl);
727 
728 	OMAP_HSMMC_WRITE(host->base, CAPA,
729 			OMAP_HSMMC_READ(host->base, CAPA) | capa);
730 
731 	OMAP_HSMMC_WRITE(host->base, HCTL,
732 			OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
733 
734 	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
735 	while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
736 		&& time_before(jiffies, timeout))
737 		;
738 
739 	omap_hsmmc_disable_irq(host);
740 
741 	/* Do not initialize card-specific things if the power is off */
742 	if (host->power_mode == MMC_POWER_OFF)
743 		goto out;
744 
745 	omap_hsmmc_set_bus_width(host);
746 
747 	omap_hsmmc_set_clock(host);
748 
749 	omap_hsmmc_set_bus_mode(host);
750 
751 out:
752 	host->context_loss = context_loss;
753 
754 	dev_dbg(mmc_dev(host->mmc), "context is restored\n");
755 	return 0;
756 }
757 
758 /*
759  * Save the MMC host context (store the number of power state changes so far).
760  */
omap_hsmmc_context_save(struct omap_hsmmc_host * host)761 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
762 {
763 	struct omap_mmc_platform_data *pdata = host->pdata;
764 	int context_loss;
765 
766 	if (pdata->get_context_loss_count) {
767 		context_loss = pdata->get_context_loss_count(host->dev);
768 		if (context_loss < 0)
769 			return;
770 		host->context_loss = context_loss;
771 	}
772 }
773 
774 #else
775 
omap_hsmmc_context_restore(struct omap_hsmmc_host * host)776 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
777 {
778 	return 0;
779 }
780 
omap_hsmmc_context_save(struct omap_hsmmc_host * host)781 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
782 {
783 }
784 
785 #endif
786 
787 /*
788  * Send init stream sequence to card
789  * before sending IDLE command
790  */
send_init_stream(struct omap_hsmmc_host * host)791 static void send_init_stream(struct omap_hsmmc_host *host)
792 {
793 	int reg = 0;
794 	unsigned long timeout;
795 
796 	if (host->protect_card)
797 		return;
798 
799 	disable_irq(host->irq);
800 
801 	OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
802 	OMAP_HSMMC_WRITE(host->base, CON,
803 		OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
804 	OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
805 
806 	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
807 	while ((reg != CC) && time_before(jiffies, timeout))
808 		reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
809 
810 	OMAP_HSMMC_WRITE(host->base, CON,
811 		OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
812 
813 	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
814 	OMAP_HSMMC_READ(host->base, STAT);
815 
816 	enable_irq(host->irq);
817 }
818 
819 static inline
omap_hsmmc_cover_is_closed(struct omap_hsmmc_host * host)820 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
821 {
822 	int r = 1;
823 
824 	if (mmc_slot(host).get_cover_state)
825 		r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
826 	return r;
827 }
828 
829 static ssize_t
omap_hsmmc_show_cover_switch(struct device * dev,struct device_attribute * attr,char * buf)830 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
831 			   char *buf)
832 {
833 	struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
834 	struct omap_hsmmc_host *host = mmc_priv(mmc);
835 
836 	return sprintf(buf, "%s\n",
837 			omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
838 }
839 
840 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
841 
842 static ssize_t
omap_hsmmc_show_slot_name(struct device * dev,struct device_attribute * attr,char * buf)843 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
844 			char *buf)
845 {
846 	struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
847 	struct omap_hsmmc_host *host = mmc_priv(mmc);
848 
849 	return sprintf(buf, "%s\n", mmc_slot(host).name);
850 }
851 
852 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
853 
854 /*
855  * Configure the response type and send the cmd.
856  */
857 static void
omap_hsmmc_start_command(struct omap_hsmmc_host * host,struct mmc_command * cmd,struct mmc_data * data)858 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
859 	struct mmc_data *data)
860 {
861 	int cmdreg = 0, resptype = 0, cmdtype = 0;
862 
863 	dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
864 		mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
865 	host->cmd = cmd;
866 
867 	omap_hsmmc_enable_irq(host, cmd);
868 
869 	host->response_busy = 0;
870 	if (cmd->flags & MMC_RSP_PRESENT) {
871 		if (cmd->flags & MMC_RSP_136)
872 			resptype = 1;
873 		else if (cmd->flags & MMC_RSP_BUSY) {
874 			resptype = 3;
875 			host->response_busy = 1;
876 		} else
877 			resptype = 2;
878 	}
879 
880 	/*
881 	 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
882 	 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
883 	 * a val of 0x3, rest 0x0.
884 	 */
885 	if (cmd == host->mrq->stop)
886 		cmdtype = 0x3;
887 
888 	cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
889 
890 	if (data) {
891 		cmdreg |= DP_SELECT | MSBS | BCE;
892 		if (data->flags & MMC_DATA_READ)
893 			cmdreg |= DDIR;
894 		else
895 			cmdreg &= ~(DDIR);
896 	}
897 
898 	if (host->use_dma)
899 		cmdreg |= DMA_EN;
900 
901 	host->req_in_progress = 1;
902 
903 	OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
904 	OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
905 }
906 
907 static int
omap_hsmmc_get_dma_dir(struct omap_hsmmc_host * host,struct mmc_data * data)908 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
909 {
910 	if (data->flags & MMC_DATA_WRITE)
911 		return DMA_TO_DEVICE;
912 	else
913 		return DMA_FROM_DEVICE;
914 }
915 
omap_hsmmc_request_done(struct omap_hsmmc_host * host,struct mmc_request * mrq)916 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
917 {
918 	int dma_ch;
919 
920 	spin_lock(&host->irq_lock);
921 	host->req_in_progress = 0;
922 	dma_ch = host->dma_ch;
923 	spin_unlock(&host->irq_lock);
924 
925 	omap_hsmmc_disable_irq(host);
926 	/* Do not complete the request if DMA is still in progress */
927 	if (mrq->data && host->use_dma && dma_ch != -1)
928 		return;
929 	host->mrq = NULL;
930 	mmc_request_done(host->mmc, mrq);
931 }
932 
933 /*
934  * Notify the transfer complete to MMC core
935  */
936 static void
omap_hsmmc_xfer_done(struct omap_hsmmc_host * host,struct mmc_data * data)937 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
938 {
939 	if (!data) {
940 		struct mmc_request *mrq = host->mrq;
941 
942 		/* TC before CC from CMD6 - don't know why, but it happens */
943 		if (host->cmd && host->cmd->opcode == 6 &&
944 		    host->response_busy) {
945 			host->response_busy = 0;
946 			return;
947 		}
948 
949 		omap_hsmmc_request_done(host, mrq);
950 		return;
951 	}
952 
953 	host->data = NULL;
954 
955 	if (!data->error)
956 		data->bytes_xfered += data->blocks * (data->blksz);
957 	else
958 		data->bytes_xfered = 0;
959 
960 	if (!data->stop) {
961 		omap_hsmmc_request_done(host, data->mrq);
962 		return;
963 	}
964 	omap_hsmmc_start_command(host, data->stop, NULL);
965 }
966 
967 /*
968  * Notify the core about command completion
969  */
970 static void
omap_hsmmc_cmd_done(struct omap_hsmmc_host * host,struct mmc_command * cmd)971 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
972 {
973 	host->cmd = NULL;
974 
975 	if (cmd->flags & MMC_RSP_PRESENT) {
976 		if (cmd->flags & MMC_RSP_136) {
977 			/* response type 2 */
978 			cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
979 			cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
980 			cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
981 			cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
982 		} else {
983 			/* response types 1, 1b, 3, 4, 5, 6 */
984 			cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
985 		}
986 	}
987 	if ((host->data == NULL && !host->response_busy) || cmd->error)
988 		omap_hsmmc_request_done(host, cmd->mrq);
989 }
990 
991 /*
992  * DMA clean up for command errors
993  */
omap_hsmmc_dma_cleanup(struct omap_hsmmc_host * host,int errno)994 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
995 {
996 	int dma_ch;
997 
998 	host->data->error = errno;
999 
1000 	spin_lock(&host->irq_lock);
1001 	dma_ch = host->dma_ch;
1002 	host->dma_ch = -1;
1003 	spin_unlock(&host->irq_lock);
1004 
1005 	if (host->use_dma && dma_ch != -1) {
1006 		dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
1007 			host->data->sg_len,
1008 			omap_hsmmc_get_dma_dir(host, host->data));
1009 		omap_free_dma(dma_ch);
1010 		host->data->host_cookie = 0;
1011 	}
1012 	host->data = NULL;
1013 }
1014 
1015 /*
1016  * Readable error output
1017  */
1018 #ifdef CONFIG_MMC_DEBUG
omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host * host,u32 status)1019 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1020 {
1021 	/* --- means reserved bit without definition at documentation */
1022 	static const char *omap_hsmmc_status_bits[] = {
1023 		"CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1024 		"CIRQ",	"OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1025 		"CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1026 		"ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1027 	};
1028 	char res[256];
1029 	char *buf = res;
1030 	int len, i;
1031 
1032 	len = sprintf(buf, "MMC IRQ 0x%x :", status);
1033 	buf += len;
1034 
1035 	for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1036 		if (status & (1 << i)) {
1037 			len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1038 			buf += len;
1039 		}
1040 
1041 	dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1042 }
1043 #else
omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host * host,u32 status)1044 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1045 					     u32 status)
1046 {
1047 }
1048 #endif  /* CONFIG_MMC_DEBUG */
1049 
1050 /*
1051  * MMC controller internal state machines reset
1052  *
1053  * Used to reset command or data internal state machines, using respectively
1054  *  SRC or SRD bit of SYSCTL register
1055  * Can be called from interrupt context
1056  */
omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host * host,unsigned long bit)1057 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1058 						   unsigned long bit)
1059 {
1060 	unsigned long i = 0;
1061 	unsigned long limit = (loops_per_jiffy *
1062 				msecs_to_jiffies(MMC_TIMEOUT_MS));
1063 
1064 	OMAP_HSMMC_WRITE(host->base, SYSCTL,
1065 			 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1066 
1067 	/*
1068 	 * OMAP4 ES2 and greater has an updated reset logic.
1069 	 * Monitor a 0->1 transition first
1070 	 */
1071 	if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1072 		while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1073 					&& (i++ < limit))
1074 			cpu_relax();
1075 	}
1076 	i = 0;
1077 
1078 	while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1079 		(i++ < limit))
1080 		cpu_relax();
1081 
1082 	if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1083 		dev_err(mmc_dev(host->mmc),
1084 			"Timeout waiting on controller reset in %s\n",
1085 			__func__);
1086 }
1087 
omap_hsmmc_do_irq(struct omap_hsmmc_host * host,int status)1088 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1089 {
1090 	struct mmc_data *data;
1091 	int end_cmd = 0, end_trans = 0;
1092 
1093 	if (!host->req_in_progress) {
1094 		do {
1095 			OMAP_HSMMC_WRITE(host->base, STAT, status);
1096 			/* Flush posted write */
1097 			status = OMAP_HSMMC_READ(host->base, STAT);
1098 		} while (status & INT_EN_MASK);
1099 		return;
1100 	}
1101 
1102 	data = host->data;
1103 	dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1104 
1105 	if (status & ERR) {
1106 		omap_hsmmc_dbg_report_irq(host, status);
1107 		if ((status & CMD_TIMEOUT) ||
1108 			(status & CMD_CRC)) {
1109 			if (host->cmd) {
1110 				if (status & CMD_TIMEOUT) {
1111 					omap_hsmmc_reset_controller_fsm(host,
1112 									SRC);
1113 					host->cmd->error = -ETIMEDOUT;
1114 				} else {
1115 					host->cmd->error = -EILSEQ;
1116 				}
1117 				end_cmd = 1;
1118 			}
1119 			if (host->data || host->response_busy) {
1120 				if (host->data)
1121 					omap_hsmmc_dma_cleanup(host,
1122 								-ETIMEDOUT);
1123 				host->response_busy = 0;
1124 				omap_hsmmc_reset_controller_fsm(host, SRD);
1125 			}
1126 		}
1127 		if ((status & DATA_TIMEOUT) ||
1128 			(status & DATA_CRC)) {
1129 			if (host->data || host->response_busy) {
1130 				int err = (status & DATA_TIMEOUT) ?
1131 						-ETIMEDOUT : -EILSEQ;
1132 
1133 				if (host->data)
1134 					omap_hsmmc_dma_cleanup(host, err);
1135 				else
1136 					host->mrq->cmd->error = err;
1137 				host->response_busy = 0;
1138 				omap_hsmmc_reset_controller_fsm(host, SRD);
1139 				end_trans = 1;
1140 			}
1141 		}
1142 		if (status & CARD_ERR) {
1143 			dev_dbg(mmc_dev(host->mmc),
1144 				"Ignoring card err CMD%d\n", host->cmd->opcode);
1145 			if (host->cmd)
1146 				end_cmd = 1;
1147 			if (host->data)
1148 				end_trans = 1;
1149 		}
1150 	}
1151 
1152 	OMAP_HSMMC_WRITE(host->base, STAT, status);
1153 
1154 	if (end_cmd || ((status & CC) && host->cmd))
1155 		omap_hsmmc_cmd_done(host, host->cmd);
1156 	if ((end_trans || (status & TC)) && host->mrq)
1157 		omap_hsmmc_xfer_done(host, data);
1158 }
1159 
1160 /*
1161  * MMC controller IRQ handler
1162  */
omap_hsmmc_irq(int irq,void * dev_id)1163 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1164 {
1165 	struct omap_hsmmc_host *host = dev_id;
1166 	int status;
1167 
1168 	status = OMAP_HSMMC_READ(host->base, STAT);
1169 	do {
1170 		omap_hsmmc_do_irq(host, status);
1171 		/* Flush posted write */
1172 		status = OMAP_HSMMC_READ(host->base, STAT);
1173 	} while (status & INT_EN_MASK);
1174 
1175 	return IRQ_HANDLED;
1176 }
1177 
set_sd_bus_power(struct omap_hsmmc_host * host)1178 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1179 {
1180 	unsigned long i;
1181 
1182 	OMAP_HSMMC_WRITE(host->base, HCTL,
1183 			 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1184 	for (i = 0; i < loops_per_jiffy; i++) {
1185 		if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1186 			break;
1187 		cpu_relax();
1188 	}
1189 }
1190 
1191 /*
1192  * Switch MMC interface voltage ... only relevant for MMC1.
1193  *
1194  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1195  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1196  * Some chips, like eMMC ones, use internal transceivers.
1197  */
omap_hsmmc_switch_opcond(struct omap_hsmmc_host * host,int vdd)1198 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1199 {
1200 	u32 reg_val = 0;
1201 	int ret;
1202 
1203 	/* Disable the clocks */
1204 	pm_runtime_put_sync(host->dev);
1205 	if (host->got_dbclk)
1206 		clk_disable(host->dbclk);
1207 
1208 	/* Turn the power off */
1209 	ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1210 
1211 	/* Turn the power ON with given VDD 1.8 or 3.0v */
1212 	if (!ret)
1213 		ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1214 					       vdd);
1215 	pm_runtime_get_sync(host->dev);
1216 	if (host->got_dbclk)
1217 		clk_enable(host->dbclk);
1218 
1219 	if (ret != 0)
1220 		goto err;
1221 
1222 	OMAP_HSMMC_WRITE(host->base, HCTL,
1223 		OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1224 	reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1225 
1226 	/*
1227 	 * If a MMC dual voltage card is detected, the set_ios fn calls
1228 	 * this fn with VDD bit set for 1.8V. Upon card removal from the
1229 	 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1230 	 *
1231 	 * Cope with a bit of slop in the range ... per data sheets:
1232 	 *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1233 	 *    but recommended values are 1.71V to 1.89V
1234 	 *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1235 	 *    but recommended values are 2.7V to 3.3V
1236 	 *
1237 	 * Board setup code shouldn't permit anything very out-of-range.
1238 	 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1239 	 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1240 	 */
1241 	if ((1 << vdd) <= MMC_VDD_23_24)
1242 		reg_val |= SDVS18;
1243 	else
1244 		reg_val |= SDVS30;
1245 
1246 	OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1247 	set_sd_bus_power(host);
1248 
1249 	return 0;
1250 err:
1251 	dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1252 	return ret;
1253 }
1254 
1255 /* Protect the card while the cover is open */
omap_hsmmc_protect_card(struct omap_hsmmc_host * host)1256 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1257 {
1258 	if (!mmc_slot(host).get_cover_state)
1259 		return;
1260 
1261 	host->reqs_blocked = 0;
1262 	if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1263 		if (host->protect_card) {
1264 			pr_info("%s: cover is closed, "
1265 					 "card is now accessible\n",
1266 					 mmc_hostname(host->mmc));
1267 			host->protect_card = 0;
1268 		}
1269 	} else {
1270 		if (!host->protect_card) {
1271 			pr_info("%s: cover is open, "
1272 					 "card is now inaccessible\n",
1273 					 mmc_hostname(host->mmc));
1274 			host->protect_card = 1;
1275 		}
1276 	}
1277 }
1278 
1279 /*
1280  * irq handler to notify the core about card insertion/removal
1281  */
omap_hsmmc_detect(int irq,void * dev_id)1282 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1283 {
1284 	struct omap_hsmmc_host *host = dev_id;
1285 	struct omap_mmc_slot_data *slot = &mmc_slot(host);
1286 	int carddetect;
1287 
1288 	if (host->suspended)
1289 		return IRQ_HANDLED;
1290 
1291 	sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1292 
1293 	if (slot->card_detect)
1294 		carddetect = slot->card_detect(host->dev, host->slot_id);
1295 	else {
1296 		omap_hsmmc_protect_card(host);
1297 		carddetect = -ENOSYS;
1298 	}
1299 
1300 	if (carddetect)
1301 		mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1302 	else
1303 		mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1304 	return IRQ_HANDLED;
1305 }
1306 
omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host * host,struct mmc_data * data)1307 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1308 				     struct mmc_data *data)
1309 {
1310 	int sync_dev;
1311 
1312 	if (data->flags & MMC_DATA_WRITE)
1313 		sync_dev = host->dma_line_tx;
1314 	else
1315 		sync_dev = host->dma_line_rx;
1316 	return sync_dev;
1317 }
1318 
omap_hsmmc_config_dma_params(struct omap_hsmmc_host * host,struct mmc_data * data,struct scatterlist * sgl)1319 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1320 				       struct mmc_data *data,
1321 				       struct scatterlist *sgl)
1322 {
1323 	int blksz, nblk, dma_ch;
1324 
1325 	dma_ch = host->dma_ch;
1326 	if (data->flags & MMC_DATA_WRITE) {
1327 		omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1328 			(host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1329 		omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1330 			sg_dma_address(sgl), 0, 0);
1331 	} else {
1332 		omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1333 			(host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1334 		omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1335 			sg_dma_address(sgl), 0, 0);
1336 	}
1337 
1338 	blksz = host->data->blksz;
1339 	nblk = sg_dma_len(sgl) / blksz;
1340 
1341 	omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1342 			blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1343 			omap_hsmmc_get_dma_sync_dev(host, data),
1344 			!(data->flags & MMC_DATA_WRITE));
1345 
1346 	omap_start_dma(dma_ch);
1347 }
1348 
1349 /*
1350  * DMA call back function
1351  */
omap_hsmmc_dma_cb(int lch,u16 ch_status,void * cb_data)1352 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1353 {
1354 	struct omap_hsmmc_host *host = cb_data;
1355 	struct mmc_data *data;
1356 	int dma_ch, req_in_progress;
1357 
1358 	if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1359 		dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1360 			ch_status);
1361 		return;
1362 	}
1363 
1364 	spin_lock(&host->irq_lock);
1365 	if (host->dma_ch < 0) {
1366 		spin_unlock(&host->irq_lock);
1367 		return;
1368 	}
1369 
1370 	data = host->mrq->data;
1371 	host->dma_sg_idx++;
1372 	if (host->dma_sg_idx < host->dma_len) {
1373 		/* Fire up the next transfer. */
1374 		omap_hsmmc_config_dma_params(host, data,
1375 					   data->sg + host->dma_sg_idx);
1376 		spin_unlock(&host->irq_lock);
1377 		return;
1378 	}
1379 
1380 	if (!data->host_cookie)
1381 		dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1382 			     omap_hsmmc_get_dma_dir(host, data));
1383 
1384 	req_in_progress = host->req_in_progress;
1385 	dma_ch = host->dma_ch;
1386 	host->dma_ch = -1;
1387 	spin_unlock(&host->irq_lock);
1388 
1389 	omap_free_dma(dma_ch);
1390 
1391 	/* If DMA has finished after TC, complete the request */
1392 	if (!req_in_progress) {
1393 		struct mmc_request *mrq = host->mrq;
1394 
1395 		host->mrq = NULL;
1396 		mmc_request_done(host->mmc, mrq);
1397 	}
1398 }
1399 
omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host * host,struct mmc_data * data,struct omap_hsmmc_next * next)1400 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1401 				       struct mmc_data *data,
1402 				       struct omap_hsmmc_next *next)
1403 {
1404 	int dma_len;
1405 
1406 	if (!next && data->host_cookie &&
1407 	    data->host_cookie != host->next_data.cookie) {
1408 		pr_warning("[%s] invalid cookie: data->host_cookie %d"
1409 		       " host->next_data.cookie %d\n",
1410 		       __func__, data->host_cookie, host->next_data.cookie);
1411 		data->host_cookie = 0;
1412 	}
1413 
1414 	/* Check if next job is already prepared */
1415 	if (next ||
1416 	    (!next && data->host_cookie != host->next_data.cookie)) {
1417 		dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1418 				     data->sg_len,
1419 				     omap_hsmmc_get_dma_dir(host, data));
1420 
1421 	} else {
1422 		dma_len = host->next_data.dma_len;
1423 		host->next_data.dma_len = 0;
1424 	}
1425 
1426 
1427 	if (dma_len == 0)
1428 		return -EINVAL;
1429 
1430 	if (next) {
1431 		next->dma_len = dma_len;
1432 		data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1433 	} else
1434 		host->dma_len = dma_len;
1435 
1436 	return 0;
1437 }
1438 
1439 /*
1440  * Routine to configure and start DMA for the MMC card
1441  */
omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host * host,struct mmc_request * req)1442 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1443 					struct mmc_request *req)
1444 {
1445 	int dma_ch = 0, ret = 0, i;
1446 	struct mmc_data *data = req->data;
1447 
1448 	/* Sanity check: all the SG entries must be aligned by block size. */
1449 	for (i = 0; i < data->sg_len; i++) {
1450 		struct scatterlist *sgl;
1451 
1452 		sgl = data->sg + i;
1453 		if (sgl->length % data->blksz)
1454 			return -EINVAL;
1455 	}
1456 	if ((data->blksz % 4) != 0)
1457 		/* REVISIT: The MMC buffer increments only when MSB is written.
1458 		 * Return error for blksz which is non multiple of four.
1459 		 */
1460 		return -EINVAL;
1461 
1462 	BUG_ON(host->dma_ch != -1);
1463 
1464 	ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1465 			       "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1466 	if (ret != 0) {
1467 		dev_err(mmc_dev(host->mmc),
1468 			"%s: omap_request_dma() failed with %d\n",
1469 			mmc_hostname(host->mmc), ret);
1470 		return ret;
1471 	}
1472 	ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1473 	if (ret)
1474 		return ret;
1475 
1476 	host->dma_ch = dma_ch;
1477 	host->dma_sg_idx = 0;
1478 
1479 	omap_hsmmc_config_dma_params(host, data, data->sg);
1480 
1481 	return 0;
1482 }
1483 
set_data_timeout(struct omap_hsmmc_host * host,unsigned int timeout_ns,unsigned int timeout_clks)1484 static void set_data_timeout(struct omap_hsmmc_host *host,
1485 			     unsigned int timeout_ns,
1486 			     unsigned int timeout_clks)
1487 {
1488 	unsigned int timeout, cycle_ns;
1489 	uint32_t reg, clkd, dto = 0;
1490 
1491 	reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1492 	clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1493 	if (clkd == 0)
1494 		clkd = 1;
1495 
1496 	cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1497 	timeout = timeout_ns / cycle_ns;
1498 	timeout += timeout_clks;
1499 	if (timeout) {
1500 		while ((timeout & 0x80000000) == 0) {
1501 			dto += 1;
1502 			timeout <<= 1;
1503 		}
1504 		dto = 31 - dto;
1505 		timeout <<= 1;
1506 		if (timeout && dto)
1507 			dto += 1;
1508 		if (dto >= 13)
1509 			dto -= 13;
1510 		else
1511 			dto = 0;
1512 		if (dto > 14)
1513 			dto = 14;
1514 	}
1515 
1516 	reg &= ~DTO_MASK;
1517 	reg |= dto << DTO_SHIFT;
1518 	OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1519 }
1520 
1521 /*
1522  * Configure block length for MMC/SD cards and initiate the transfer.
1523  */
1524 static int
omap_hsmmc_prepare_data(struct omap_hsmmc_host * host,struct mmc_request * req)1525 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1526 {
1527 	int ret;
1528 	host->data = req->data;
1529 
1530 	if (req->data == NULL) {
1531 		OMAP_HSMMC_WRITE(host->base, BLK, 0);
1532 		/*
1533 		 * Set an arbitrary 100ms data timeout for commands with
1534 		 * busy signal.
1535 		 */
1536 		if (req->cmd->flags & MMC_RSP_BUSY)
1537 			set_data_timeout(host, 100000000U, 0);
1538 		return 0;
1539 	}
1540 
1541 	OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1542 					| (req->data->blocks << 16));
1543 	set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1544 
1545 	if (host->use_dma) {
1546 		ret = omap_hsmmc_start_dma_transfer(host, req);
1547 		if (ret != 0) {
1548 			dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1549 			return ret;
1550 		}
1551 	}
1552 	return 0;
1553 }
1554 
omap_hsmmc_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)1555 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1556 				int err)
1557 {
1558 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1559 	struct mmc_data *data = mrq->data;
1560 
1561 	if (host->use_dma) {
1562 		if (data->host_cookie)
1563 			dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1564 				     data->sg_len,
1565 				     omap_hsmmc_get_dma_dir(host, data));
1566 		data->host_cookie = 0;
1567 	}
1568 }
1569 
omap_hsmmc_pre_req(struct mmc_host * mmc,struct mmc_request * mrq,bool is_first_req)1570 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1571 			       bool is_first_req)
1572 {
1573 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1574 
1575 	if (mrq->data->host_cookie) {
1576 		mrq->data->host_cookie = 0;
1577 		return ;
1578 	}
1579 
1580 	if (host->use_dma)
1581 		if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1582 						&host->next_data))
1583 			mrq->data->host_cookie = 0;
1584 }
1585 
1586 /*
1587  * Request function. for read/write operation
1588  */
omap_hsmmc_request(struct mmc_host * mmc,struct mmc_request * req)1589 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1590 {
1591 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1592 	int err;
1593 
1594 	BUG_ON(host->req_in_progress);
1595 	BUG_ON(host->dma_ch != -1);
1596 	if (host->protect_card) {
1597 		if (host->reqs_blocked < 3) {
1598 			/*
1599 			 * Ensure the controller is left in a consistent
1600 			 * state by resetting the command and data state
1601 			 * machines.
1602 			 */
1603 			omap_hsmmc_reset_controller_fsm(host, SRD);
1604 			omap_hsmmc_reset_controller_fsm(host, SRC);
1605 			host->reqs_blocked += 1;
1606 		}
1607 		req->cmd->error = -EBADF;
1608 		if (req->data)
1609 			req->data->error = -EBADF;
1610 		req->cmd->retries = 0;
1611 		mmc_request_done(mmc, req);
1612 		return;
1613 	} else if (host->reqs_blocked)
1614 		host->reqs_blocked = 0;
1615 	WARN_ON(host->mrq != NULL);
1616 	host->mrq = req;
1617 	err = omap_hsmmc_prepare_data(host, req);
1618 	if (err) {
1619 		req->cmd->error = err;
1620 		if (req->data)
1621 			req->data->error = err;
1622 		host->mrq = NULL;
1623 		mmc_request_done(mmc, req);
1624 		return;
1625 	}
1626 
1627 	omap_hsmmc_start_command(host, req->cmd, req->data);
1628 }
1629 
1630 /* Routine to configure clock values. Exposed API to core */
omap_hsmmc_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1631 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1632 {
1633 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1634 	int do_send_init_stream = 0;
1635 
1636 	pm_runtime_get_sync(host->dev);
1637 
1638 	if (ios->power_mode != host->power_mode) {
1639 		switch (ios->power_mode) {
1640 		case MMC_POWER_OFF:
1641 			mmc_slot(host).set_power(host->dev, host->slot_id,
1642 						 0, 0);
1643 			host->vdd = 0;
1644 			break;
1645 		case MMC_POWER_UP:
1646 			mmc_slot(host).set_power(host->dev, host->slot_id,
1647 						 1, ios->vdd);
1648 			host->vdd = ios->vdd;
1649 			break;
1650 		case MMC_POWER_ON:
1651 			do_send_init_stream = 1;
1652 			break;
1653 		}
1654 		host->power_mode = ios->power_mode;
1655 	}
1656 
1657 	/* FIXME: set registers based only on changes to ios */
1658 
1659 	omap_hsmmc_set_bus_width(host);
1660 
1661 	if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1662 		/* Only MMC1 can interface at 3V without some flavor
1663 		 * of external transceiver; but they all handle 1.8V.
1664 		 */
1665 		if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1666 			(ios->vdd == DUAL_VOLT_OCR_BIT)) {
1667 				/*
1668 				 * The mmc_select_voltage fn of the core does
1669 				 * not seem to set the power_mode to
1670 				 * MMC_POWER_UP upon recalculating the voltage.
1671 				 * vdd 1.8v.
1672 				 */
1673 			if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1674 				dev_dbg(mmc_dev(host->mmc),
1675 						"Switch operation failed\n");
1676 		}
1677 	}
1678 
1679 	omap_hsmmc_set_clock(host);
1680 
1681 	if (do_send_init_stream)
1682 		send_init_stream(host);
1683 
1684 	omap_hsmmc_set_bus_mode(host);
1685 
1686 	pm_runtime_put_autosuspend(host->dev);
1687 }
1688 
omap_hsmmc_get_cd(struct mmc_host * mmc)1689 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1690 {
1691 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1692 
1693 	if (!mmc_slot(host).card_detect)
1694 		return -ENOSYS;
1695 	return mmc_slot(host).card_detect(host->dev, host->slot_id);
1696 }
1697 
omap_hsmmc_get_ro(struct mmc_host * mmc)1698 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1699 {
1700 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1701 
1702 	if (!mmc_slot(host).get_ro)
1703 		return -ENOSYS;
1704 	return mmc_slot(host).get_ro(host->dev, 0);
1705 }
1706 
omap_hsmmc_init_card(struct mmc_host * mmc,struct mmc_card * card)1707 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1708 {
1709 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1710 
1711 	if (mmc_slot(host).init_card)
1712 		mmc_slot(host).init_card(card);
1713 }
1714 
omap_hsmmc_conf_bus_power(struct omap_hsmmc_host * host)1715 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1716 {
1717 	u32 hctl, capa, value;
1718 
1719 	/* Only MMC1 supports 3.0V */
1720 	if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1721 		hctl = SDVS30;
1722 		capa = VS30 | VS18;
1723 	} else {
1724 		hctl = SDVS18;
1725 		capa = VS18;
1726 	}
1727 
1728 	value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1729 	OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1730 
1731 	value = OMAP_HSMMC_READ(host->base, CAPA);
1732 	OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1733 
1734 	/* Set the controller to AUTO IDLE mode */
1735 	value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1736 	OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1737 
1738 	/* Set SD bus power bit */
1739 	set_sd_bus_power(host);
1740 }
1741 
omap_hsmmc_enable_fclk(struct mmc_host * mmc)1742 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1743 {
1744 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1745 
1746 	pm_runtime_get_sync(host->dev);
1747 
1748 	return 0;
1749 }
1750 
omap_hsmmc_disable_fclk(struct mmc_host * mmc,int lazy)1751 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1752 {
1753 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1754 
1755 	pm_runtime_mark_last_busy(host->dev);
1756 	pm_runtime_put_autosuspend(host->dev);
1757 
1758 	return 0;
1759 }
1760 
1761 static const struct mmc_host_ops omap_hsmmc_ops = {
1762 	.enable = omap_hsmmc_enable_fclk,
1763 	.disable = omap_hsmmc_disable_fclk,
1764 	.post_req = omap_hsmmc_post_req,
1765 	.pre_req = omap_hsmmc_pre_req,
1766 	.request = omap_hsmmc_request,
1767 	.set_ios = omap_hsmmc_set_ios,
1768 	.get_cd = omap_hsmmc_get_cd,
1769 	.get_ro = omap_hsmmc_get_ro,
1770 	.init_card = omap_hsmmc_init_card,
1771 	/* NYET -- enable_sdio_irq */
1772 };
1773 
1774 #ifdef CONFIG_DEBUG_FS
1775 
omap_hsmmc_regs_show(struct seq_file * s,void * data)1776 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1777 {
1778 	struct mmc_host *mmc = s->private;
1779 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1780 	int context_loss = 0;
1781 
1782 	if (host->pdata->get_context_loss_count)
1783 		context_loss = host->pdata->get_context_loss_count(host->dev);
1784 
1785 	seq_printf(s, "mmc%d:\n"
1786 			" enabled:\t%d\n"
1787 			" dpm_state:\t%d\n"
1788 			" nesting_cnt:\t%d\n"
1789 			" ctx_loss:\t%d:%d\n"
1790 			"\nregs:\n",
1791 			mmc->index, mmc->enabled ? 1 : 0,
1792 			host->dpm_state, mmc->nesting_cnt,
1793 			host->context_loss, context_loss);
1794 
1795 	if (host->suspended) {
1796 		seq_printf(s, "host suspended, can't read registers\n");
1797 		return 0;
1798 	}
1799 
1800 	pm_runtime_get_sync(host->dev);
1801 
1802 	seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1803 			OMAP_HSMMC_READ(host->base, SYSCONFIG));
1804 	seq_printf(s, "CON:\t\t0x%08x\n",
1805 			OMAP_HSMMC_READ(host->base, CON));
1806 	seq_printf(s, "HCTL:\t\t0x%08x\n",
1807 			OMAP_HSMMC_READ(host->base, HCTL));
1808 	seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1809 			OMAP_HSMMC_READ(host->base, SYSCTL));
1810 	seq_printf(s, "IE:\t\t0x%08x\n",
1811 			OMAP_HSMMC_READ(host->base, IE));
1812 	seq_printf(s, "ISE:\t\t0x%08x\n",
1813 			OMAP_HSMMC_READ(host->base, ISE));
1814 	seq_printf(s, "CAPA:\t\t0x%08x\n",
1815 			OMAP_HSMMC_READ(host->base, CAPA));
1816 
1817 	pm_runtime_mark_last_busy(host->dev);
1818 	pm_runtime_put_autosuspend(host->dev);
1819 
1820 	return 0;
1821 }
1822 
omap_hsmmc_regs_open(struct inode * inode,struct file * file)1823 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1824 {
1825 	return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1826 }
1827 
1828 static const struct file_operations mmc_regs_fops = {
1829 	.open           = omap_hsmmc_regs_open,
1830 	.read           = seq_read,
1831 	.llseek         = seq_lseek,
1832 	.release        = single_release,
1833 };
1834 
omap_hsmmc_debugfs(struct mmc_host * mmc)1835 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1836 {
1837 	if (mmc->debugfs_root)
1838 		debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1839 			mmc, &mmc_regs_fops);
1840 }
1841 
1842 #else
1843 
omap_hsmmc_debugfs(struct mmc_host * mmc)1844 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1845 {
1846 }
1847 
1848 #endif
1849 
omap_hsmmc_probe(struct platform_device * pdev)1850 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1851 {
1852 	struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1853 	struct mmc_host *mmc;
1854 	struct omap_hsmmc_host *host = NULL;
1855 	struct resource *res;
1856 	int ret, irq;
1857 
1858 	if (pdata == NULL) {
1859 		dev_err(&pdev->dev, "Platform Data is missing\n");
1860 		return -ENXIO;
1861 	}
1862 
1863 	if (pdata->nr_slots == 0) {
1864 		dev_err(&pdev->dev, "No Slots\n");
1865 		return -ENXIO;
1866 	}
1867 
1868 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1869 	irq = platform_get_irq(pdev, 0);
1870 	if (res == NULL || irq < 0)
1871 		return -ENXIO;
1872 
1873 	res->start += pdata->reg_offset;
1874 	res->end += pdata->reg_offset;
1875 	res = request_mem_region(res->start, resource_size(res), pdev->name);
1876 	if (res == NULL)
1877 		return -EBUSY;
1878 
1879 	ret = omap_hsmmc_gpio_init(pdata);
1880 	if (ret)
1881 		goto err;
1882 
1883 	mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1884 	if (!mmc) {
1885 		ret = -ENOMEM;
1886 		goto err_alloc;
1887 	}
1888 
1889 	host		= mmc_priv(mmc);
1890 	host->mmc	= mmc;
1891 	host->pdata	= pdata;
1892 	host->dev	= &pdev->dev;
1893 	host->use_dma	= 1;
1894 	host->dev->dma_mask = &pdata->dma_mask;
1895 	host->dma_ch	= -1;
1896 	host->irq	= irq;
1897 	host->id	= pdev->id;
1898 	host->slot_id	= 0;
1899 	host->mapbase	= res->start;
1900 	host->base	= ioremap(host->mapbase, SZ_4K);
1901 	host->power_mode = MMC_POWER_OFF;
1902 	host->next_data.cookie = 1;
1903 
1904 	platform_set_drvdata(pdev, host);
1905 
1906 	mmc->ops	= &omap_hsmmc_ops;
1907 
1908 	/*
1909 	 * If regulator_disable can only put vcc_aux to sleep then there is
1910 	 * no off state.
1911 	 */
1912 	if (mmc_slot(host).vcc_aux_disable_is_sleep)
1913 		mmc_slot(host).no_off = 1;
1914 
1915 	mmc->f_min	= OMAP_MMC_MIN_CLOCK;
1916 	mmc->f_max	= OMAP_MMC_MAX_CLOCK;
1917 
1918 	spin_lock_init(&host->irq_lock);
1919 
1920 	host->fclk = clk_get(&pdev->dev, "fck");
1921 	if (IS_ERR(host->fclk)) {
1922 		ret = PTR_ERR(host->fclk);
1923 		host->fclk = NULL;
1924 		goto err1;
1925 	}
1926 
1927 	omap_hsmmc_context_save(host);
1928 
1929 	mmc->caps |= MMC_CAP_DISABLE;
1930 	if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1931 		dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1932 		mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1933 	}
1934 
1935 	pm_runtime_enable(host->dev);
1936 	pm_runtime_get_sync(host->dev);
1937 	pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1938 	pm_runtime_use_autosuspend(host->dev);
1939 
1940 	if (cpu_is_omap2430()) {
1941 		host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1942 		/*
1943 		 * MMC can still work without debounce clock.
1944 		 */
1945 		if (IS_ERR(host->dbclk))
1946 			dev_warn(mmc_dev(host->mmc),
1947 				"Failed to get debounce clock\n");
1948 		else
1949 			host->got_dbclk = 1;
1950 
1951 		if (host->got_dbclk)
1952 			if (clk_enable(host->dbclk) != 0)
1953 				dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1954 							" clk failed\n");
1955 	}
1956 
1957 	/* Since we do only SG emulation, we can have as many segs
1958 	 * as we want. */
1959 	mmc->max_segs = 1024;
1960 
1961 	mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1962 	mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1963 	mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1964 	mmc->max_seg_size = mmc->max_req_size;
1965 
1966 	mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1967 		     MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1968 
1969 	mmc->caps |= mmc_slot(host).caps;
1970 	if (mmc->caps & MMC_CAP_8_BIT_DATA)
1971 		mmc->caps |= MMC_CAP_4_BIT_DATA;
1972 
1973 	if (mmc_slot(host).nonremovable)
1974 		mmc->caps |= MMC_CAP_NONREMOVABLE;
1975 
1976 	mmc->pm_caps = mmc_slot(host).pm_caps;
1977 
1978 	omap_hsmmc_conf_bus_power(host);
1979 
1980 	/* Select DMA lines */
1981 	switch (host->id) {
1982 	case OMAP_MMC1_DEVID:
1983 		host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1984 		host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1985 		break;
1986 	case OMAP_MMC2_DEVID:
1987 		host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1988 		host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1989 		break;
1990 	case OMAP_MMC3_DEVID:
1991 		host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
1992 		host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
1993 		break;
1994 	case OMAP_MMC4_DEVID:
1995 		host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
1996 		host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
1997 		break;
1998 	case OMAP_MMC5_DEVID:
1999 		host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2000 		host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2001 		break;
2002 	default:
2003 		dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2004 		goto err_irq;
2005 	}
2006 
2007 	/* Request IRQ for MMC operations */
2008 	ret = request_irq(host->irq, omap_hsmmc_irq, 0,
2009 			mmc_hostname(mmc), host);
2010 	if (ret) {
2011 		dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2012 		goto err_irq;
2013 	}
2014 
2015 	if (pdata->init != NULL) {
2016 		if (pdata->init(&pdev->dev) != 0) {
2017 			dev_dbg(mmc_dev(host->mmc),
2018 				"Unable to configure MMC IRQs\n");
2019 			goto err_irq_cd_init;
2020 		}
2021 	}
2022 
2023 	if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2024 		ret = omap_hsmmc_reg_get(host);
2025 		if (ret)
2026 			goto err_reg;
2027 		host->use_reg = 1;
2028 	}
2029 
2030 	mmc->ocr_avail = mmc_slot(host).ocr_mask;
2031 
2032 	/* Request IRQ for card detect */
2033 	if ((mmc_slot(host).card_detect_irq)) {
2034 		ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
2035 					   NULL,
2036 					   omap_hsmmc_detect,
2037 					   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
2038 					   mmc_hostname(mmc), host);
2039 		if (ret) {
2040 			dev_dbg(mmc_dev(host->mmc),
2041 				"Unable to grab MMC CD IRQ\n");
2042 			goto err_irq_cd;
2043 		}
2044 		pdata->suspend = omap_hsmmc_suspend_cdirq;
2045 		pdata->resume = omap_hsmmc_resume_cdirq;
2046 	}
2047 
2048 	omap_hsmmc_disable_irq(host);
2049 
2050 	omap_hsmmc_protect_card(host);
2051 
2052 	mmc_add_host(mmc);
2053 
2054 	if (mmc_slot(host).name != NULL) {
2055 		ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2056 		if (ret < 0)
2057 			goto err_slot_name;
2058 	}
2059 	if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2060 		ret = device_create_file(&mmc->class_dev,
2061 					&dev_attr_cover_switch);
2062 		if (ret < 0)
2063 			goto err_slot_name;
2064 	}
2065 
2066 	omap_hsmmc_debugfs(mmc);
2067 	pm_runtime_mark_last_busy(host->dev);
2068 	pm_runtime_put_autosuspend(host->dev);
2069 
2070 	return 0;
2071 
2072 err_slot_name:
2073 	mmc_remove_host(mmc);
2074 	free_irq(mmc_slot(host).card_detect_irq, host);
2075 err_irq_cd:
2076 	if (host->use_reg)
2077 		omap_hsmmc_reg_put(host);
2078 err_reg:
2079 	if (host->pdata->cleanup)
2080 		host->pdata->cleanup(&pdev->dev);
2081 err_irq_cd_init:
2082 	free_irq(host->irq, host);
2083 err_irq:
2084 	pm_runtime_mark_last_busy(host->dev);
2085 	pm_runtime_put_autosuspend(host->dev);
2086 	clk_put(host->fclk);
2087 	if (host->got_dbclk) {
2088 		clk_disable(host->dbclk);
2089 		clk_put(host->dbclk);
2090 	}
2091 err1:
2092 	iounmap(host->base);
2093 	platform_set_drvdata(pdev, NULL);
2094 	mmc_free_host(mmc);
2095 err_alloc:
2096 	omap_hsmmc_gpio_free(pdata);
2097 err:
2098 	release_mem_region(res->start, resource_size(res));
2099 	return ret;
2100 }
2101 
omap_hsmmc_remove(struct platform_device * pdev)2102 static int omap_hsmmc_remove(struct platform_device *pdev)
2103 {
2104 	struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2105 	struct resource *res;
2106 
2107 	if (host) {
2108 		pm_runtime_get_sync(host->dev);
2109 		mmc_remove_host(host->mmc);
2110 		if (host->use_reg)
2111 			omap_hsmmc_reg_put(host);
2112 		if (host->pdata->cleanup)
2113 			host->pdata->cleanup(&pdev->dev);
2114 		free_irq(host->irq, host);
2115 		if (mmc_slot(host).card_detect_irq)
2116 			free_irq(mmc_slot(host).card_detect_irq, host);
2117 
2118 		pm_runtime_put_sync(host->dev);
2119 		pm_runtime_disable(host->dev);
2120 		clk_put(host->fclk);
2121 		if (host->got_dbclk) {
2122 			clk_disable(host->dbclk);
2123 			clk_put(host->dbclk);
2124 		}
2125 
2126 		mmc_free_host(host->mmc);
2127 		iounmap(host->base);
2128 		omap_hsmmc_gpio_free(pdev->dev.platform_data);
2129 	}
2130 
2131 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2132 	if (res)
2133 		release_mem_region(res->start, resource_size(res));
2134 	platform_set_drvdata(pdev, NULL);
2135 
2136 	return 0;
2137 }
2138 
2139 #ifdef CONFIG_PM
omap_hsmmc_suspend(struct device * dev)2140 static int omap_hsmmc_suspend(struct device *dev)
2141 {
2142 	int ret = 0;
2143 	struct platform_device *pdev = to_platform_device(dev);
2144 	struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2145 
2146 	if (host && host->suspended)
2147 		return 0;
2148 
2149 	if (host) {
2150 		pm_runtime_get_sync(host->dev);
2151 		host->suspended = 1;
2152 		if (host->pdata->suspend) {
2153 			ret = host->pdata->suspend(&pdev->dev,
2154 							host->slot_id);
2155 			if (ret) {
2156 				dev_dbg(mmc_dev(host->mmc),
2157 					"Unable to handle MMC board"
2158 					" level suspend\n");
2159 				host->suspended = 0;
2160 				return ret;
2161 			}
2162 		}
2163 		ret = mmc_suspend_host(host->mmc);
2164 
2165 		if (ret) {
2166 			host->suspended = 0;
2167 			if (host->pdata->resume) {
2168 				ret = host->pdata->resume(&pdev->dev,
2169 							  host->slot_id);
2170 				if (ret)
2171 					dev_dbg(mmc_dev(host->mmc),
2172 						"Unmask interrupt failed\n");
2173 			}
2174 			goto err;
2175 		}
2176 
2177 		if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2178 			omap_hsmmc_disable_irq(host);
2179 			OMAP_HSMMC_WRITE(host->base, HCTL,
2180 				OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2181 		}
2182 		if (host->got_dbclk)
2183 			clk_disable(host->dbclk);
2184 
2185 	}
2186 err:
2187 	pm_runtime_put_sync(host->dev);
2188 	return ret;
2189 }
2190 
2191 /* Routine to resume the MMC device */
omap_hsmmc_resume(struct device * dev)2192 static int omap_hsmmc_resume(struct device *dev)
2193 {
2194 	int ret = 0;
2195 	struct platform_device *pdev = to_platform_device(dev);
2196 	struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2197 
2198 	if (host && !host->suspended)
2199 		return 0;
2200 
2201 	if (host) {
2202 		pm_runtime_get_sync(host->dev);
2203 
2204 		if (host->got_dbclk)
2205 			clk_enable(host->dbclk);
2206 
2207 		if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2208 			omap_hsmmc_conf_bus_power(host);
2209 
2210 		if (host->pdata->resume) {
2211 			ret = host->pdata->resume(&pdev->dev, host->slot_id);
2212 			if (ret)
2213 				dev_dbg(mmc_dev(host->mmc),
2214 					"Unmask interrupt failed\n");
2215 		}
2216 
2217 		omap_hsmmc_protect_card(host);
2218 
2219 		/* Notify the core to resume the host */
2220 		ret = mmc_resume_host(host->mmc);
2221 		if (ret == 0)
2222 			host->suspended = 0;
2223 
2224 		pm_runtime_mark_last_busy(host->dev);
2225 		pm_runtime_put_autosuspend(host->dev);
2226 	}
2227 
2228 	return ret;
2229 
2230 }
2231 
2232 #else
2233 #define omap_hsmmc_suspend	NULL
2234 #define omap_hsmmc_resume		NULL
2235 #endif
2236 
omap_hsmmc_runtime_suspend(struct device * dev)2237 static int omap_hsmmc_runtime_suspend(struct device *dev)
2238 {
2239 	struct omap_hsmmc_host *host;
2240 
2241 	host = platform_get_drvdata(to_platform_device(dev));
2242 	omap_hsmmc_context_save(host);
2243 	dev_dbg(mmc_dev(host->mmc), "disabled\n");
2244 
2245 	return 0;
2246 }
2247 
omap_hsmmc_runtime_resume(struct device * dev)2248 static int omap_hsmmc_runtime_resume(struct device *dev)
2249 {
2250 	struct omap_hsmmc_host *host;
2251 
2252 	host = platform_get_drvdata(to_platform_device(dev));
2253 	omap_hsmmc_context_restore(host);
2254 	dev_dbg(mmc_dev(host->mmc), "enabled\n");
2255 
2256 	return 0;
2257 }
2258 
2259 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2260 	.suspend	= omap_hsmmc_suspend,
2261 	.resume		= omap_hsmmc_resume,
2262 	.runtime_suspend = omap_hsmmc_runtime_suspend,
2263 	.runtime_resume = omap_hsmmc_runtime_resume,
2264 };
2265 
2266 static struct platform_driver omap_hsmmc_driver = {
2267 	.remove		= omap_hsmmc_remove,
2268 	.driver		= {
2269 		.name = DRIVER_NAME,
2270 		.owner = THIS_MODULE,
2271 		.pm = &omap_hsmmc_dev_pm_ops,
2272 	},
2273 };
2274 
omap_hsmmc_init(void)2275 static int __init omap_hsmmc_init(void)
2276 {
2277 	/* Register the MMC driver */
2278 	return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2279 }
2280 
omap_hsmmc_cleanup(void)2281 static void __exit omap_hsmmc_cleanup(void)
2282 {
2283 	/* Unregister MMC driver */
2284 	platform_driver_unregister(&omap_hsmmc_driver);
2285 }
2286 
2287 module_init(omap_hsmmc_init);
2288 module_exit(omap_hsmmc_cleanup);
2289 
2290 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2291 MODULE_LICENSE("GPL");
2292 MODULE_ALIAS("platform:" DRIVER_NAME);
2293 MODULE_AUTHOR("Texas Instruments Inc");
2294