1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6#include <dt-bindings/bus/ti-sysc.h>
7#include <dt-bindings/clock/omap4.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/pinctrl/omap.h>
11#include <dt-bindings/clock/omap4.h>
12
13/ {
14	compatible = "ti,omap4430", "ti,omap4";
15	interrupt-parent = <&wakeupgen>;
16	#address-cells = <1>;
17	#size-cells = <1>;
18	chosen { };
19
20	aliases {
21		i2c0 = &i2c1;
22		i2c1 = &i2c2;
23		i2c2 = &i2c3;
24		i2c3 = &i2c4;
25		serial0 = &uart1;
26		serial1 = &uart2;
27		serial2 = &uart3;
28		serial3 = &uart4;
29		rproc0 = &dsp;
30		rproc1 = &ipu;
31	};
32
33	cpus {
34		#address-cells = <1>;
35		#size-cells = <0>;
36
37		cpu@0 {
38			compatible = "arm,cortex-a9";
39			device_type = "cpu";
40			next-level-cache = <&L2>;
41			reg = <0x0>;
42
43			clocks = <&dpll_mpu_ck>;
44			clock-names = "cpu";
45
46			clock-latency = <300000>; /* From omap-cpufreq driver */
47		};
48		cpu@1 {
49			compatible = "arm,cortex-a9";
50			device_type = "cpu";
51			next-level-cache = <&L2>;
52			reg = <0x1>;
53		};
54	};
55
56	/*
57	 * Note that 4430 needs cross trigger interface (CTI) supported
58	 * before we can configure the interrupts. This means sampling
59	 * events are not supported for pmu. Note that 4460 does not use
60	 * CTI, see also 4460.dtsi.
61	 */
62	pmu {
63		compatible = "arm,cortex-a9-pmu";
64		ti,hwmods = "debugss";
65	};
66
67	gic: interrupt-controller@48241000 {
68		compatible = "arm,cortex-a9-gic";
69		interrupt-controller;
70		#interrupt-cells = <3>;
71		reg = <0x48241000 0x1000>,
72		      <0x48240100 0x0100>;
73		interrupt-parent = <&gic>;
74	};
75
76	L2: cache-controller@48242000 {
77		compatible = "arm,pl310-cache";
78		reg = <0x48242000 0x1000>;
79		cache-unified;
80		cache-level = <2>;
81	};
82
83	local-timer@48240600 {
84		compatible = "arm,cortex-a9-twd-timer";
85		clocks = <&mpu_periphclk>;
86		reg = <0x48240600 0x20>;
87		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
88		interrupt-parent = <&gic>;
89	};
90
91	wakeupgen: interrupt-controller@48281000 {
92		compatible = "ti,omap4-wugen-mpu";
93		interrupt-controller;
94		#interrupt-cells = <3>;
95		reg = <0x48281000 0x1000>;
96		interrupt-parent = <&gic>;
97	};
98
99	/*
100	 * The soc node represents the soc top level view. It is used for IPs
101	 * that are not memory mapped in the MPU view or for the MPU itself.
102	 */
103	soc {
104		compatible = "ti,omap-infra";
105		mpu {
106			compatible = "ti,omap4-mpu";
107			ti,hwmods = "mpu";
108			sram = <&ocmcram>;
109		};
110
111		iva {
112			compatible = "ti,ivahd";
113			ti,hwmods = "iva";
114		};
115	};
116
117	/*
118	 * XXX: Use a flat representation of the OMAP4 interconnect.
119	 * The real OMAP interconnect network is quite complex.
120	 * Since it will not bring real advantage to represent that in DT for
121	 * the moment, just use a fake OCP bus entry to represent the whole bus
122	 * hierarchy.
123	 */
124	ocp {
125		compatible = "ti,omap4-l3-noc", "simple-bus";
126		#address-cells = <1>;
127		#size-cells = <1>;
128		ranges;
129		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
130		reg = <0x44000000 0x1000>,
131		      <0x44800000 0x2000>,
132		      <0x45000000 0x1000>;
133		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
134			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
135
136		l4_wkup: interconnect@4a300000 {
137		};
138
139		l4_cfg: interconnect@4a000000 {
140		};
141
142		l4_per: interconnect@48000000 {
143		};
144
145		l4_abe: interconnect@40100000 {
146		};
147
148		ocmcram: sram@40304000 {
149			compatible = "mmio-sram";
150			reg = <0x40304000 0xa000>; /* 40k */
151		};
152
153		gpmc: gpmc@50000000 {
154			compatible = "ti,omap4430-gpmc";
155			reg = <0x50000000 0x1000>;
156			#address-cells = <2>;
157			#size-cells = <1>;
158			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
159			dmas = <&sdma 4>;
160			dma-names = "rxtx";
161			gpmc,num-cs = <8>;
162			gpmc,num-waitpins = <4>;
163			ti,hwmods = "gpmc";
164			ti,no-idle-on-init;
165			clocks = <&l3_div_ck>;
166			clock-names = "fck";
167			interrupt-controller;
168			#interrupt-cells = <2>;
169			gpio-controller;
170			#gpio-cells = <2>;
171		};
172
173		target-module@52000000 {
174			compatible = "ti,sysc-omap4", "ti,sysc";
175			ti,hwmods = "iss";
176			reg = <0x52000000 0x4>,
177			      <0x52000010 0x4>;
178			reg-names = "rev", "sysc";
179			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
180			ti,sysc-midle = <SYSC_IDLE_FORCE>,
181					<SYSC_IDLE_NO>,
182					<SYSC_IDLE_SMART>,
183					<SYSC_IDLE_SMART_WKUP>;
184			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
185					<SYSC_IDLE_NO>,
186					<SYSC_IDLE_SMART>,
187					<SYSC_IDLE_SMART_WKUP>;
188			ti,sysc-delay-us = <2>;
189			clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
190			clock-names = "fck";
191			#address-cells = <1>;
192			#size-cells = <1>;
193			ranges = <0 0x52000000 0x1000000>;
194
195			/* No child device binding, driver in staging */
196		};
197
198		target-module@55082000 {
199			compatible = "ti,sysc-omap2", "ti,sysc";
200			reg = <0x55082000 0x4>,
201			      <0x55082010 0x4>,
202			      <0x55082014 0x4>;
203			reg-names = "rev", "sysc", "syss";
204			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
205					<SYSC_IDLE_NO>,
206					<SYSC_IDLE_SMART>;
207			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
208					 SYSC_OMAP2_SOFTRESET |
209					 SYSC_OMAP2_AUTOIDLE)>;
210			clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
211			clock-names = "fck";
212			resets = <&prm_core 2>;
213			reset-names = "rstctrl";
214			ranges = <0x0 0x55082000 0x100>;
215			#size-cells = <1>;
216			#address-cells = <1>;
217
218			mmu_ipu: mmu@0 {
219				compatible = "ti,omap4-iommu";
220				reg = <0x0 0x100>;
221				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
222				#iommu-cells = <0>;
223				ti,iommu-bus-err-back;
224			};
225		};
226
227		target-module@4012c000 {
228			compatible = "ti,sysc-omap4", "ti,sysc";
229			reg = <0x4012c000 0x4>,
230			      <0x4012c010 0x4>;
231			reg-names = "rev", "sysc";
232			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
233			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
234					<SYSC_IDLE_NO>,
235					<SYSC_IDLE_SMART>,
236					<SYSC_IDLE_SMART_WKUP>;
237			clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
238			clock-names = "fck";
239			#address-cells = <1>;
240			#size-cells = <1>;
241			ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
242				 <0x4902c000 0x4902c000 0x1000>; /* L3 */
243
244			/* No child device binding or driver in mainline */
245		};
246
247		dmm@4e000000 {
248			compatible = "ti,omap4-dmm";
249			reg = <0x4e000000 0x800>;
250			interrupts = <0 113 0x4>;
251			ti,hwmods = "dmm";
252		};
253
254		emif1: emif@4c000000 {
255			compatible = "ti,emif-4d";
256			reg = <0x4c000000 0x100>;
257			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
258			ti,hwmods = "emif1";
259			ti,no-idle-on-init;
260			phy-type = <1>;
261			hw-caps-read-idle-ctrl;
262			hw-caps-ll-interface;
263			hw-caps-temp-alert;
264		};
265
266		emif2: emif@4d000000 {
267			compatible = "ti,emif-4d";
268			reg = <0x4d000000 0x100>;
269			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
270			ti,hwmods = "emif2";
271			ti,no-idle-on-init;
272			phy-type = <1>;
273			hw-caps-read-idle-ctrl;
274			hw-caps-ll-interface;
275			hw-caps-temp-alert;
276		};
277
278		dsp: dsp {
279			compatible = "ti,omap4-dsp";
280			ti,bootreg = <&scm_conf 0x304 0>;
281			iommus = <&mmu_dsp>;
282			resets = <&prm_tesla 0>;
283			clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
284			firmware-name = "omap4-dsp-fw.xe64T";
285			mboxes = <&mailbox &mbox_dsp>;
286			status = "disabled";
287		};
288
289		ipu: ipu@55020000 {
290			compatible = "ti,omap4-ipu";
291			reg = <0x55020000 0x10000>;
292			reg-names = "l2ram";
293			iommus = <&mmu_ipu>;
294			resets = <&prm_core 0>, <&prm_core 1>;
295			clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
296			firmware-name = "omap4-ipu-fw.xem3";
297			mboxes = <&mailbox &mbox_ipu>;
298			status = "disabled";
299		};
300
301		aes1_target: target-module@4b501000 {
302			compatible = "ti,sysc-omap2", "ti,sysc";
303			reg = <0x4b501080 0x4>,
304			      <0x4b501084 0x4>,
305			      <0x4b501088 0x4>;
306			reg-names = "rev", "sysc", "syss";
307			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
308					 SYSC_OMAP2_AUTOIDLE)>;
309			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
310					<SYSC_IDLE_NO>,
311					<SYSC_IDLE_SMART>,
312					<SYSC_IDLE_SMART_WKUP>;
313			ti,syss-mask = <1>;
314			/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
315			clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
316			clock-names = "fck";
317			#address-cells = <1>;
318			#size-cells = <1>;
319			ranges = <0x0 0x4b501000 0x1000>;
320
321			aes1: aes@0 {
322				compatible = "ti,omap4-aes";
323				reg = <0 0xa0>;
324				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
325				dmas = <&sdma 111>, <&sdma 110>;
326				dma-names = "tx", "rx";
327			};
328		};
329
330		aes2_target: target-module@4b701000 {
331			compatible = "ti,sysc-omap2", "ti,sysc";
332			reg = <0x4b701080 0x4>,
333			      <0x4b701084 0x4>,
334			      <0x4b701088 0x4>;
335			reg-names = "rev", "sysc", "syss";
336			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
337					 SYSC_OMAP2_AUTOIDLE)>;
338			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
339					<SYSC_IDLE_NO>,
340					<SYSC_IDLE_SMART>,
341					<SYSC_IDLE_SMART_WKUP>;
342			ti,syss-mask = <1>;
343			/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
344			clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
345			clock-names = "fck";
346			#address-cells = <1>;
347			#size-cells = <1>;
348			ranges = <0x0 0x4b701000 0x1000>;
349
350			aes2: aes@0 {
351				compatible = "ti,omap4-aes";
352				reg = <0 0xa0>;
353				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
354				dmas = <&sdma 114>, <&sdma 113>;
355				dma-names = "tx", "rx";
356			};
357		};
358
359		sham_target: target-module@4b100000 {
360			compatible = "ti,sysc-omap3-sham", "ti,sysc";
361			reg = <0x4b100100 0x4>,
362			      <0x4b100110 0x4>,
363			      <0x4b100114 0x4>;
364			reg-names = "rev", "sysc", "syss";
365			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
366					 SYSC_OMAP2_AUTOIDLE)>;
367			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
368					<SYSC_IDLE_NO>,
369					<SYSC_IDLE_SMART>;
370			ti,syss-mask = <1>;
371			/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
372			clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
373			clock-names = "fck";
374			#address-cells = <1>;
375			#size-cells = <1>;
376			ranges = <0x0 0x4b100000 0x1000>;
377
378			sham: sham@0 {
379				compatible = "ti,omap4-sham";
380				reg = <0 0x300>;
381				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
382				dmas = <&sdma 119>;
383				dma-names = "rx";
384			};
385		};
386
387		abb_mpu: regulator-abb-mpu {
388			compatible = "ti,abb-v2";
389			regulator-name = "abb_mpu";
390			#address-cells = <0>;
391			#size-cells = <0>;
392			ti,tranxdone-status-mask = <0x80>;
393			clocks = <&sys_clkin_ck>;
394			ti,settling-time = <50>;
395			ti,clock-cycles = <16>;
396
397			status = "disabled";
398		};
399
400		abb_iva: regulator-abb-iva {
401			compatible = "ti,abb-v2";
402			regulator-name = "abb_iva";
403			#address-cells = <0>;
404			#size-cells = <0>;
405			ti,tranxdone-status-mask = <0x80000000>;
406			clocks = <&sys_clkin_ck>;
407			ti,settling-time = <50>;
408			ti,clock-cycles = <16>;
409
410			status = "disabled";
411		};
412
413		sgx_module: target-module@56000000 {
414			compatible = "ti,sysc-omap4", "ti,sysc";
415			reg = <0x5600fe00 0x4>,
416			      <0x5600fe10 0x4>;
417			reg-names = "rev", "sysc";
418			ti,sysc-midle = <SYSC_IDLE_FORCE>,
419					<SYSC_IDLE_NO>,
420					<SYSC_IDLE_SMART>,
421					<SYSC_IDLE_SMART_WKUP>;
422			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
423					<SYSC_IDLE_NO>,
424					<SYSC_IDLE_SMART>,
425					<SYSC_IDLE_SMART_WKUP>;
426			clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
427			clock-names = "fck";
428			#address-cells = <1>;
429			#size-cells = <1>;
430			ranges = <0 0x56000000 0x2000000>;
431
432			/*
433			 * Closed source PowerVR driver, no child device
434			 * binding or driver in mainline
435			 */
436		};
437
438		/*
439		 * DSS is only using l3 mapping without l4 as noted in the TRM
440		 * "10.1.3 DSS Register Manual" for omap4460.
441		 */
442		target-module@58000000 {
443			compatible = "ti,sysc-omap2", "ti,sysc";
444			reg = <0x58000000 4>,
445			      <0x58000014 4>;
446			reg-names = "rev", "syss";
447			ti,syss-mask = <1>;
448			clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
449				 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
450				 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
451				 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
452			clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
453			#address-cells = <1>;
454			#size-cells = <1>;
455			ranges = <0 0x58000000 0x1000000>;
456
457			dss: dss@0 {
458				compatible = "ti,omap4-dss";
459				reg = <0 0x80>;
460				status = "disabled";
461				clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
462				clock-names = "fck";
463				#address-cells = <1>;
464				#size-cells = <1>;
465				ranges = <0 0 0x1000000>;
466
467				target-module@1000 {
468					compatible = "ti,sysc-omap2", "ti,sysc";
469					reg = <0x1000 0x4>,
470					      <0x1010 0x4>,
471					      <0x1014 0x4>;
472					reg-names = "rev", "sysc", "syss";
473					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
474							<SYSC_IDLE_NO>,
475							<SYSC_IDLE_SMART>;
476					ti,sysc-midle = <SYSC_IDLE_FORCE>,
477							<SYSC_IDLE_NO>,
478							<SYSC_IDLE_SMART>;
479					ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
480							 SYSC_OMAP2_ENAWAKEUP |
481							 SYSC_OMAP2_SOFTRESET |
482							 SYSC_OMAP2_AUTOIDLE)>;
483					ti,syss-mask = <1>;
484					clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
485						 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
486					clock-names = "fck", "sys_clk";
487					#address-cells = <1>;
488					#size-cells = <1>;
489					ranges = <0 0x1000 0x1000>;
490
491					dispc@0 {
492						compatible = "ti,omap4-dispc";
493						reg = <0 0x1000>;
494						interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
495						clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
496						clock-names = "fck";
497					};
498				};
499
500				target-module@2000 {
501					compatible = "ti,sysc-omap2", "ti,sysc";
502					reg = <0x2000 0x4>,
503					      <0x2010 0x4>,
504					      <0x2014 0x4>;
505					reg-names = "rev", "sysc", "syss";
506					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
507							<SYSC_IDLE_NO>,
508							<SYSC_IDLE_SMART>;
509					ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
510							 SYSC_OMAP2_AUTOIDLE)>;
511					ti,syss-mask = <1>;
512					clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
513						 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
514					clock-names = "fck", "sys_clk";
515					#address-cells = <1>;
516					#size-cells = <1>;
517					ranges = <0 0x2000 0x1000>;
518
519					rfbi: encoder@0  {
520						reg = <0 0x1000>;
521						status = "disabled";
522						clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
523						clock-names = "fck", "ick";
524					};
525				};
526
527				target-module@3000 {
528					compatible = "ti,sysc-omap2", "ti,sysc";
529					reg = <0x3000 0x4>;
530					reg-names = "rev";
531					clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
532					clock-names = "sys_clk";
533					#address-cells = <1>;
534					#size-cells = <1>;
535					ranges = <0 0x3000 0x1000>;
536
537					venc: encoder@0 {
538						compatible = "ti,omap4-venc";
539						reg = <0 0x1000>;
540						status = "disabled";
541						clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
542						clock-names = "fck";
543					};
544				};
545
546				target-module@4000 {
547					compatible = "ti,sysc-omap2", "ti,sysc";
548					reg = <0x4000 0x4>,
549					      <0x4010 0x4>,
550					      <0x4014 0x4>;
551					reg-names = "rev", "sysc", "syss";
552					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
553							<SYSC_IDLE_NO>,
554							<SYSC_IDLE_SMART>;
555					ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
556							 SYSC_OMAP2_ENAWAKEUP |
557							 SYSC_OMAP2_SOFTRESET |
558							 SYSC_OMAP2_AUTOIDLE)>;
559					ti,syss-mask = <1>;
560					#address-cells = <1>;
561					#size-cells = <1>;
562					ranges = <0 0x4000 0x1000>;
563
564					dsi1: encoder@0 {
565						compatible = "ti,omap4-dsi";
566						reg = <0 0x200>,
567						      <0x200 0x40>,
568						      <0x300 0x20>;
569						reg-names = "proto", "phy", "pll";
570						interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
571						status = "disabled";
572						clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
573							 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
574						clock-names = "fck", "sys_clk";
575
576						#address-cells = <1>;
577						#size-cells = <0>;
578					};
579				};
580
581				target-module@5000 {
582					compatible = "ti,sysc-omap2", "ti,sysc";
583					reg = <0x5000 0x4>,
584					      <0x5010 0x4>,
585					      <0x5014 0x4>;
586					reg-names = "rev", "sysc", "syss";
587					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
588							<SYSC_IDLE_NO>,
589							<SYSC_IDLE_SMART>;
590					ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
591							 SYSC_OMAP2_ENAWAKEUP |
592							 SYSC_OMAP2_SOFTRESET |
593							 SYSC_OMAP2_AUTOIDLE)>;
594					ti,syss-mask = <1>;
595					#address-cells = <1>;
596					#size-cells = <1>;
597					ranges = <0 0x5000 0x1000>;
598
599					dsi2: encoder@0 {
600						compatible = "ti,omap4-dsi";
601						reg = <0 0x200>,
602						      <0x200 0x40>,
603						      <0x300 0x20>;
604						reg-names = "proto", "phy", "pll";
605						interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
606						status = "disabled";
607						clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
608						         <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
609						clock-names = "fck", "sys_clk";
610
611						#address-cells = <1>;
612						#size-cells = <0>;
613					};
614				};
615
616				target-module@6000 {
617					compatible = "ti,sysc-omap4", "ti,sysc";
618					reg = <0x6000 0x4>,
619					      <0x6010 0x4>;
620					reg-names = "rev", "sysc";
621					/*
622					 * Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP
623					 * but HDMI audio will fail with them.
624					 */
625					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
626							<SYSC_IDLE_NO>;
627					ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
628					clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
629						 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
630					clock-names = "fck", "dss_clk";
631					#address-cells = <1>;
632					#size-cells = <1>;
633					ranges = <0 0x6000 0x2000>;
634
635					hdmi: encoder@0 {
636					compatible = "ti,omap4-hdmi";
637						reg = <0 0x200>,
638						      <0x200 0x100>,
639						      <0x300 0x100>,
640						      <0x400 0x1000>;
641						reg-names = "wp", "pll", "phy", "core";
642						interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
643						status = "disabled";
644						clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
645						         <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
646						clock-names = "fck", "sys_clk";
647						dmas = <&sdma 76>;
648						dma-names = "audio_tx";
649					};
650				};
651			};
652		};
653	};
654};
655
656#include "omap4-l4.dtsi"
657#include "omap4-l4-abe.dtsi"
658#include "omap44xx-clocks.dtsi"
659
660&prm {
661	prm_tesla: prm@400 {
662		compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
663		reg = <0x400 0x100>;
664		#reset-cells = <1>;
665	};
666
667	prm_abe: prm@500 {
668		compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
669		reg = <0x500 0x100>;
670		#power-domain-cells = <0>;
671	};
672
673	prm_core: prm@700 {
674		compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
675		reg = <0x700 0x100>;
676		#reset-cells = <1>;
677	};
678
679	prm_ivahd: prm@f00 {
680		compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
681		reg = <0xf00 0x100>;
682		#reset-cells = <1>;
683	};
684
685	prm_device: prm@1b00 {
686		compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
687		reg = <0x1b00 0x40>;
688		#reset-cells = <1>;
689	};
690};
691
692/* Preferred always-on timer for clockevent */
693&timer1_target {
694	ti,no-reset-on-init;
695	ti,no-idle;
696	timer@0 {
697		assigned-clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
698		assigned-clock-parents = <&sys_32k_ck>;
699	};
700};
701