1 /* SPDX-License-Identifier: GPL-2.0 */
2 #define CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE 512
3
4 #ifndef XKPHYS_TO_PHYS
5 # define XKPHYS_TO_PHYS(p) (p)
6 #endif
7
8 #define OCTEON_IRQ_WORKQ0 0
9 #define OCTEON_IRQ_RML 0
10 #define OCTEON_IRQ_TIMER1 0
11 #define OCTEON_IS_MODEL(x) 0
12 #define octeon_has_feature(x) 0
13 #define octeon_get_clock_rate() 0
14
15 #define CVMX_SYNCIOBDMA do { } while (0)
16
17 #define CVMX_HELPER_INPUT_TAG_TYPE 0
18 #define CVMX_HELPER_FIRST_MBUFF_SKIP 7
19 #define CVMX_FAU_REG_END (2048)
20 #define CVMX_FPA_OUTPUT_BUFFER_POOL (2)
21 #define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE 16
22 #define CVMX_FPA_PACKET_POOL (0)
23 #define CVMX_FPA_PACKET_POOL_SIZE 16
24 #define CVMX_FPA_WQE_POOL (1)
25 #define CVMX_FPA_WQE_POOL_SIZE 16
26 #define CVMX_GMXX_RXX_ADR_CAM_EN(a, b) ((a) + (b))
27 #define CVMX_GMXX_RXX_ADR_CTL(a, b) ((a) + (b))
28 #define CVMX_GMXX_PRTX_CFG(a, b) ((a) + (b))
29 #define CVMX_GMXX_RXX_FRM_MAX(a, b) ((a) + (b))
30 #define CVMX_GMXX_RXX_JABBER(a, b) ((a) + (b))
31 #define CVMX_IPD_CTL_STATUS 0
32 #define CVMX_PIP_FRM_LEN_CHKX(a) (a)
33 #define CVMX_PIP_NUM_INPUT_PORTS 1
34 #define CVMX_SCR_SCRATCH 0
35 #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 2
36 #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 2
37 #define CVMX_IPD_SUB_PORT_FCS 0
38 #define CVMX_SSO_WQ_IQ_DIS 0
39 #define CVMX_SSO_WQ_INT 0
40 #define CVMX_POW_WQ_INT 0
41 #define CVMX_SSO_WQ_INT_PC 0
42 #define CVMX_NPI_RSL_INT_BLOCKS 0
43 #define CVMX_POW_WQ_INT_PC 0
44
45 union cvmx_pip_wqe_word2 {
46 u64 u64;
47
48 struct {
49 u64 bufs : 8;
50 u64 ip_offset : 8;
51 u64 vlan_valid : 1;
52 u64 vlan_stacked : 1;
53 u64 unassigned : 1;
54 u64 vlan_cfi : 1;
55 u64 vlan_id : 12;
56 u64 pr : 4;
57 u64 unassigned2 : 8;
58 u64 dec_ipcomp : 1;
59 u64 tcp_or_udp : 1;
60 u64 dec_ipsec : 1;
61 u64 is_v6 : 1;
62 u64 software : 1;
63 u64 L4_error : 1;
64 u64 is_frag : 1;
65 u64 IP_exc : 1;
66 u64 is_bcast : 1;
67 u64 is_mcast : 1;
68 u64 not_IP : 1;
69 u64 rcv_error : 1;
70 u64 err_code : 8;
71 } s;
72
73 struct {
74 u64 bufs : 8;
75 u64 ip_offset : 8;
76 u64 vlan_valid : 1;
77 u64 vlan_stacked : 1;
78 u64 unassigned : 1;
79 u64 vlan_cfi : 1;
80 u64 vlan_id : 12;
81 u64 port : 12;
82 u64 dec_ipcomp : 1;
83 u64 tcp_or_udp : 1;
84 u64 dec_ipsec : 1;
85 u64 is_v6 : 1;
86 u64 software : 1;
87 u64 L4_error : 1;
88 u64 is_frag : 1;
89 u64 IP_exc : 1;
90 u64 is_bcast : 1;
91 u64 is_mcast : 1;
92 u64 not_IP : 1;
93 u64 rcv_error : 1;
94 u64 err_code : 8;
95 } s_cn68xx;
96
97 struct {
98 u64 unused1 : 16;
99 u64 vlan : 16;
100 u64 unused2 : 32;
101 } svlan;
102
103 struct {
104 u64 bufs : 8;
105 u64 unused : 8;
106 u64 vlan_valid : 1;
107 u64 vlan_stacked : 1;
108 u64 unassigned : 1;
109 u64 vlan_cfi : 1;
110 u64 vlan_id : 12;
111 u64 pr : 4;
112 u64 unassigned2 : 12;
113 u64 software : 1;
114 u64 unassigned3 : 1;
115 u64 is_rarp : 1;
116 u64 is_arp : 1;
117 u64 is_bcast : 1;
118 u64 is_mcast : 1;
119 u64 not_IP : 1;
120 u64 rcv_error : 1;
121 u64 err_code : 8;
122 } snoip;
123 };
124
125 union cvmx_pip_wqe_word0 {
126 struct {
127 uint64_t next_ptr:40;
128 uint8_t unused;
129 __wsum hw_chksum;
130 } cn38xx;
131 struct {
132 uint64_t pknd:6; /* 0..5 */
133 uint64_t unused2:2; /* 6..7 */
134 uint64_t bpid:6; /* 8..13 */
135 uint64_t unused1:18; /* 14..31 */
136 uint64_t l2ptr:8; /* 32..39 */
137 uint64_t l3ptr:8; /* 40..47 */
138 uint64_t unused0:8; /* 48..55 */
139 uint64_t l4ptr:8; /* 56..63 */
140 } cn68xx;
141 };
142
143 union cvmx_wqe_word0 {
144 uint64_t u64;
145 union cvmx_pip_wqe_word0 pip;
146 };
147
148 union cvmx_wqe_word1 {
149 uint64_t u64;
150 struct {
151 uint64_t tag:32;
152 uint64_t tag_type:2;
153 uint64_t varies:14;
154 uint64_t len:16;
155 };
156 struct {
157 uint64_t tag:32;
158 uint64_t tag_type:2;
159 uint64_t zero_2:3;
160 uint64_t grp:6;
161 uint64_t zero_1:1;
162 uint64_t qos:3;
163 uint64_t zero_0:1;
164 uint64_t len:16;
165 } cn68xx;
166 struct {
167 uint64_t tag:32;
168 uint64_t tag_type:2;
169 uint64_t zero_2:1;
170 uint64_t grp:4;
171 uint64_t qos:3;
172 uint64_t ipprt:6;
173 uint64_t len:16;
174 } cn38xx;
175 };
176
177 union cvmx_buf_ptr {
178 void *ptr;
179 uint64_t u64;
180 struct {
181 uint64_t i:1;
182 uint64_t back:4;
183 uint64_t pool:3;
184 uint64_t size:16;
185 uint64_t addr:40;
186 } s;
187 };
188
189 struct cvmx_wqe {
190 union cvmx_wqe_word0 word0;
191 union cvmx_wqe_word1 word1;
192 union cvmx_pip_wqe_word2 word2;
193 union cvmx_buf_ptr packet_ptr;
194 uint8_t packet_data[96];
195 };
196
197 union cvmx_helper_link_info {
198 uint64_t u64;
199 struct {
200 uint64_t reserved_20_63:44;
201 uint64_t link_up:1; /**< Is the physical link up? */
202 uint64_t full_duplex:1; /**< 1 if the link is full duplex */
203 uint64_t speed:18; /**< Speed of the link in Mbps */
204 } s;
205 };
206
207 enum cvmx_fau_reg_32 {
208 CVMX_FAU_REG_32_START = 0,
209 };
210
211 enum cvmx_fau_op_size {
212 CVMX_FAU_OP_SIZE_8 = 0,
213 CVMX_FAU_OP_SIZE_16 = 1,
214 CVMX_FAU_OP_SIZE_32 = 2,
215 CVMX_FAU_OP_SIZE_64 = 3
216 };
217
218 typedef enum {
219 CVMX_SPI_MODE_UNKNOWN = 0,
220 CVMX_SPI_MODE_TX_HALFPLEX = 1,
221 CVMX_SPI_MODE_RX_HALFPLEX = 2,
222 CVMX_SPI_MODE_DUPLEX = 3
223 } cvmx_spi_mode_t;
224
225 typedef enum {
226 CVMX_HELPER_INTERFACE_MODE_DISABLED,
227 CVMX_HELPER_INTERFACE_MODE_RGMII,
228 CVMX_HELPER_INTERFACE_MODE_GMII,
229 CVMX_HELPER_INTERFACE_MODE_SPI,
230 CVMX_HELPER_INTERFACE_MODE_PCIE,
231 CVMX_HELPER_INTERFACE_MODE_XAUI,
232 CVMX_HELPER_INTERFACE_MODE_SGMII,
233 CVMX_HELPER_INTERFACE_MODE_PICMG,
234 CVMX_HELPER_INTERFACE_MODE_NPI,
235 CVMX_HELPER_INTERFACE_MODE_LOOP,
236 } cvmx_helper_interface_mode_t;
237
238 typedef enum {
239 CVMX_POW_WAIT = 1,
240 CVMX_POW_NO_WAIT = 0,
241 } cvmx_pow_wait_t;
242
243 typedef enum {
244 CVMX_PKO_LOCK_NONE = 0,
245 CVMX_PKO_LOCK_ATOMIC_TAG = 1,
246 CVMX_PKO_LOCK_CMD_QUEUE = 2,
247 } cvmx_pko_lock_t;
248
249 typedef enum {
250 CVMX_PKO_SUCCESS,
251 CVMX_PKO_INVALID_PORT,
252 CVMX_PKO_INVALID_QUEUE,
253 CVMX_PKO_INVALID_PRIORITY,
254 CVMX_PKO_NO_MEMORY,
255 CVMX_PKO_PORT_ALREADY_SETUP,
256 CVMX_PKO_CMD_QUEUE_INIT_ERROR
257 } cvmx_pko_status_t;
258
259 enum cvmx_pow_tag_type {
260 CVMX_POW_TAG_TYPE_ORDERED = 0L,
261 CVMX_POW_TAG_TYPE_ATOMIC = 1L,
262 CVMX_POW_TAG_TYPE_NULL = 2L,
263 CVMX_POW_TAG_TYPE_NULL_NULL = 3L
264 };
265
266 union cvmx_ipd_ctl_status {
267 uint64_t u64;
268 struct cvmx_ipd_ctl_status_s {
269 uint64_t reserved_18_63:46;
270 uint64_t use_sop:1;
271 uint64_t rst_done:1;
272 uint64_t clken:1;
273 uint64_t no_wptr:1;
274 uint64_t pq_apkt:1;
275 uint64_t pq_nabuf:1;
276 uint64_t ipd_full:1;
277 uint64_t pkt_off:1;
278 uint64_t len_m8:1;
279 uint64_t reset:1;
280 uint64_t addpkt:1;
281 uint64_t naddbuf:1;
282 uint64_t pkt_lend:1;
283 uint64_t wqe_lend:1;
284 uint64_t pbp_en:1;
285 uint64_t opc_mode:2;
286 uint64_t ipd_en:1;
287 } s;
288 struct cvmx_ipd_ctl_status_cn30xx {
289 uint64_t reserved_10_63:54;
290 uint64_t len_m8:1;
291 uint64_t reset:1;
292 uint64_t addpkt:1;
293 uint64_t naddbuf:1;
294 uint64_t pkt_lend:1;
295 uint64_t wqe_lend:1;
296 uint64_t pbp_en:1;
297 uint64_t opc_mode:2;
298 uint64_t ipd_en:1;
299 } cn30xx;
300 struct cvmx_ipd_ctl_status_cn38xxp2 {
301 uint64_t reserved_9_63:55;
302 uint64_t reset:1;
303 uint64_t addpkt:1;
304 uint64_t naddbuf:1;
305 uint64_t pkt_lend:1;
306 uint64_t wqe_lend:1;
307 uint64_t pbp_en:1;
308 uint64_t opc_mode:2;
309 uint64_t ipd_en:1;
310 } cn38xxp2;
311 struct cvmx_ipd_ctl_status_cn50xx {
312 uint64_t reserved_15_63:49;
313 uint64_t no_wptr:1;
314 uint64_t pq_apkt:1;
315 uint64_t pq_nabuf:1;
316 uint64_t ipd_full:1;
317 uint64_t pkt_off:1;
318 uint64_t len_m8:1;
319 uint64_t reset:1;
320 uint64_t addpkt:1;
321 uint64_t naddbuf:1;
322 uint64_t pkt_lend:1;
323 uint64_t wqe_lend:1;
324 uint64_t pbp_en:1;
325 uint64_t opc_mode:2;
326 uint64_t ipd_en:1;
327 } cn50xx;
328 struct cvmx_ipd_ctl_status_cn58xx {
329 uint64_t reserved_12_63:52;
330 uint64_t ipd_full:1;
331 uint64_t pkt_off:1;
332 uint64_t len_m8:1;
333 uint64_t reset:1;
334 uint64_t addpkt:1;
335 uint64_t naddbuf:1;
336 uint64_t pkt_lend:1;
337 uint64_t wqe_lend:1;
338 uint64_t pbp_en:1;
339 uint64_t opc_mode:2;
340 uint64_t ipd_en:1;
341 } cn58xx;
342 struct cvmx_ipd_ctl_status_cn63xxp1 {
343 uint64_t reserved_16_63:48;
344 uint64_t clken:1;
345 uint64_t no_wptr:1;
346 uint64_t pq_apkt:1;
347 uint64_t pq_nabuf:1;
348 uint64_t ipd_full:1;
349 uint64_t pkt_off:1;
350 uint64_t len_m8:1;
351 uint64_t reset:1;
352 uint64_t addpkt:1;
353 uint64_t naddbuf:1;
354 uint64_t pkt_lend:1;
355 uint64_t wqe_lend:1;
356 uint64_t pbp_en:1;
357 uint64_t opc_mode:2;
358 uint64_t ipd_en:1;
359 } cn63xxp1;
360 };
361
362 union cvmx_ipd_sub_port_fcs {
363 uint64_t u64;
364 struct cvmx_ipd_sub_port_fcs_s {
365 uint64_t port_bit:32;
366 uint64_t reserved_32_35:4;
367 uint64_t port_bit2:4;
368 uint64_t reserved_40_63:24;
369 } s;
370 struct cvmx_ipd_sub_port_fcs_cn30xx {
371 uint64_t port_bit:3;
372 uint64_t reserved_3_63:61;
373 } cn30xx;
374 struct cvmx_ipd_sub_port_fcs_cn38xx {
375 uint64_t port_bit:32;
376 uint64_t reserved_32_63:32;
377 } cn38xx;
378 };
379
380 union cvmx_ipd_sub_port_qos_cnt {
381 uint64_t u64;
382 struct cvmx_ipd_sub_port_qos_cnt_s {
383 uint64_t cnt:32;
384 uint64_t port_qos:9;
385 uint64_t reserved_41_63:23;
386 } s;
387 };
388
389 typedef struct {
390 uint32_t dropped_octets;
391 uint32_t dropped_packets;
392 uint32_t pci_raw_packets;
393 uint32_t octets;
394 uint32_t packets;
395 uint32_t multicast_packets;
396 uint32_t broadcast_packets;
397 uint32_t len_64_packets;
398 uint32_t len_65_127_packets;
399 uint32_t len_128_255_packets;
400 uint32_t len_256_511_packets;
401 uint32_t len_512_1023_packets;
402 uint32_t len_1024_1518_packets;
403 uint32_t len_1519_max_packets;
404 uint32_t fcs_align_err_packets;
405 uint32_t runt_packets;
406 uint32_t runt_crc_packets;
407 uint32_t oversize_packets;
408 uint32_t oversize_crc_packets;
409 uint32_t inb_packets;
410 uint64_t inb_octets;
411 uint16_t inb_errors;
412 } cvmx_pip_port_status_t;
413
414 typedef struct {
415 uint32_t packets;
416 uint64_t octets;
417 uint64_t doorbell;
418 } cvmx_pko_port_status_t;
419
420 union cvmx_pip_frm_len_chkx {
421 uint64_t u64;
422 struct cvmx_pip_frm_len_chkx_s {
423 uint64_t reserved_32_63:32;
424 uint64_t maxlen:16;
425 uint64_t minlen:16;
426 } s;
427 };
428
429 union cvmx_gmxx_rxx_frm_ctl {
430 uint64_t u64;
431 struct cvmx_gmxx_rxx_frm_ctl_s {
432 uint64_t pre_chk:1;
433 uint64_t pre_strp:1;
434 uint64_t ctl_drp:1;
435 uint64_t ctl_bck:1;
436 uint64_t ctl_mcst:1;
437 uint64_t ctl_smac:1;
438 uint64_t pre_free:1;
439 uint64_t vlan_len:1;
440 uint64_t pad_len:1;
441 uint64_t pre_align:1;
442 uint64_t null_dis:1;
443 uint64_t reserved_11_11:1;
444 uint64_t ptp_mode:1;
445 uint64_t reserved_13_63:51;
446 } s;
447 struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
448 uint64_t pre_chk:1;
449 uint64_t pre_strp:1;
450 uint64_t ctl_drp:1;
451 uint64_t ctl_bck:1;
452 uint64_t ctl_mcst:1;
453 uint64_t ctl_smac:1;
454 uint64_t pre_free:1;
455 uint64_t vlan_len:1;
456 uint64_t pad_len:1;
457 uint64_t reserved_9_63:55;
458 } cn30xx;
459 struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
460 uint64_t pre_chk:1;
461 uint64_t pre_strp:1;
462 uint64_t ctl_drp:1;
463 uint64_t ctl_bck:1;
464 uint64_t ctl_mcst:1;
465 uint64_t ctl_smac:1;
466 uint64_t pre_free:1;
467 uint64_t vlan_len:1;
468 uint64_t reserved_8_63:56;
469 } cn31xx;
470 struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
471 uint64_t pre_chk:1;
472 uint64_t pre_strp:1;
473 uint64_t ctl_drp:1;
474 uint64_t ctl_bck:1;
475 uint64_t ctl_mcst:1;
476 uint64_t ctl_smac:1;
477 uint64_t pre_free:1;
478 uint64_t reserved_7_8:2;
479 uint64_t pre_align:1;
480 uint64_t null_dis:1;
481 uint64_t reserved_11_63:53;
482 } cn50xx;
483 struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
484 uint64_t pre_chk:1;
485 uint64_t pre_strp:1;
486 uint64_t ctl_drp:1;
487 uint64_t ctl_bck:1;
488 uint64_t ctl_mcst:1;
489 uint64_t ctl_smac:1;
490 uint64_t pre_free:1;
491 uint64_t reserved_7_8:2;
492 uint64_t pre_align:1;
493 uint64_t reserved_10_63:54;
494 } cn56xxp1;
495 struct cvmx_gmxx_rxx_frm_ctl_cn58xx {
496 uint64_t pre_chk:1;
497 uint64_t pre_strp:1;
498 uint64_t ctl_drp:1;
499 uint64_t ctl_bck:1;
500 uint64_t ctl_mcst:1;
501 uint64_t ctl_smac:1;
502 uint64_t pre_free:1;
503 uint64_t vlan_len:1;
504 uint64_t pad_len:1;
505 uint64_t pre_align:1;
506 uint64_t null_dis:1;
507 uint64_t reserved_11_63:53;
508 } cn58xx;
509 struct cvmx_gmxx_rxx_frm_ctl_cn61xx {
510 uint64_t pre_chk:1;
511 uint64_t pre_strp:1;
512 uint64_t ctl_drp:1;
513 uint64_t ctl_bck:1;
514 uint64_t ctl_mcst:1;
515 uint64_t ctl_smac:1;
516 uint64_t pre_free:1;
517 uint64_t reserved_7_8:2;
518 uint64_t pre_align:1;
519 uint64_t null_dis:1;
520 uint64_t reserved_11_11:1;
521 uint64_t ptp_mode:1;
522 uint64_t reserved_13_63:51;
523 } cn61xx;
524 };
525
526 union cvmx_gmxx_rxx_int_reg {
527 uint64_t u64;
528 struct cvmx_gmxx_rxx_int_reg_s {
529 uint64_t minerr:1;
530 uint64_t carext:1;
531 uint64_t maxerr:1;
532 uint64_t jabber:1;
533 uint64_t fcserr:1;
534 uint64_t alnerr:1;
535 uint64_t lenerr:1;
536 uint64_t rcverr:1;
537 uint64_t skperr:1;
538 uint64_t niberr:1;
539 uint64_t ovrerr:1;
540 uint64_t pcterr:1;
541 uint64_t rsverr:1;
542 uint64_t falerr:1;
543 uint64_t coldet:1;
544 uint64_t ifgerr:1;
545 uint64_t phy_link:1;
546 uint64_t phy_spd:1;
547 uint64_t phy_dupx:1;
548 uint64_t pause_drp:1;
549 uint64_t loc_fault:1;
550 uint64_t rem_fault:1;
551 uint64_t bad_seq:1;
552 uint64_t bad_term:1;
553 uint64_t unsop:1;
554 uint64_t uneop:1;
555 uint64_t undat:1;
556 uint64_t hg2fld:1;
557 uint64_t hg2cc:1;
558 uint64_t reserved_29_63:35;
559 } s;
560 struct cvmx_gmxx_rxx_int_reg_cn30xx {
561 uint64_t minerr:1;
562 uint64_t carext:1;
563 uint64_t maxerr:1;
564 uint64_t jabber:1;
565 uint64_t fcserr:1;
566 uint64_t alnerr:1;
567 uint64_t lenerr:1;
568 uint64_t rcverr:1;
569 uint64_t skperr:1;
570 uint64_t niberr:1;
571 uint64_t ovrerr:1;
572 uint64_t pcterr:1;
573 uint64_t rsverr:1;
574 uint64_t falerr:1;
575 uint64_t coldet:1;
576 uint64_t ifgerr:1;
577 uint64_t phy_link:1;
578 uint64_t phy_spd:1;
579 uint64_t phy_dupx:1;
580 uint64_t reserved_19_63:45;
581 } cn30xx;
582 struct cvmx_gmxx_rxx_int_reg_cn50xx {
583 uint64_t reserved_0_0:1;
584 uint64_t carext:1;
585 uint64_t reserved_2_2:1;
586 uint64_t jabber:1;
587 uint64_t fcserr:1;
588 uint64_t alnerr:1;
589 uint64_t reserved_6_6:1;
590 uint64_t rcverr:1;
591 uint64_t skperr:1;
592 uint64_t niberr:1;
593 uint64_t ovrerr:1;
594 uint64_t pcterr:1;
595 uint64_t rsverr:1;
596 uint64_t falerr:1;
597 uint64_t coldet:1;
598 uint64_t ifgerr:1;
599 uint64_t phy_link:1;
600 uint64_t phy_spd:1;
601 uint64_t phy_dupx:1;
602 uint64_t pause_drp:1;
603 uint64_t reserved_20_63:44;
604 } cn50xx;
605 struct cvmx_gmxx_rxx_int_reg_cn52xx {
606 uint64_t reserved_0_0:1;
607 uint64_t carext:1;
608 uint64_t reserved_2_2:1;
609 uint64_t jabber:1;
610 uint64_t fcserr:1;
611 uint64_t reserved_5_6:2;
612 uint64_t rcverr:1;
613 uint64_t skperr:1;
614 uint64_t reserved_9_9:1;
615 uint64_t ovrerr:1;
616 uint64_t pcterr:1;
617 uint64_t rsverr:1;
618 uint64_t falerr:1;
619 uint64_t coldet:1;
620 uint64_t ifgerr:1;
621 uint64_t reserved_16_18:3;
622 uint64_t pause_drp:1;
623 uint64_t loc_fault:1;
624 uint64_t rem_fault:1;
625 uint64_t bad_seq:1;
626 uint64_t bad_term:1;
627 uint64_t unsop:1;
628 uint64_t uneop:1;
629 uint64_t undat:1;
630 uint64_t hg2fld:1;
631 uint64_t hg2cc:1;
632 uint64_t reserved_29_63:35;
633 } cn52xx;
634 struct cvmx_gmxx_rxx_int_reg_cn56xxp1 {
635 uint64_t reserved_0_0:1;
636 uint64_t carext:1;
637 uint64_t reserved_2_2:1;
638 uint64_t jabber:1;
639 uint64_t fcserr:1;
640 uint64_t reserved_5_6:2;
641 uint64_t rcverr:1;
642 uint64_t skperr:1;
643 uint64_t reserved_9_9:1;
644 uint64_t ovrerr:1;
645 uint64_t pcterr:1;
646 uint64_t rsverr:1;
647 uint64_t falerr:1;
648 uint64_t coldet:1;
649 uint64_t ifgerr:1;
650 uint64_t reserved_16_18:3;
651 uint64_t pause_drp:1;
652 uint64_t loc_fault:1;
653 uint64_t rem_fault:1;
654 uint64_t bad_seq:1;
655 uint64_t bad_term:1;
656 uint64_t unsop:1;
657 uint64_t uneop:1;
658 uint64_t undat:1;
659 uint64_t reserved_27_63:37;
660 } cn56xxp1;
661 struct cvmx_gmxx_rxx_int_reg_cn58xx {
662 uint64_t minerr:1;
663 uint64_t carext:1;
664 uint64_t maxerr:1;
665 uint64_t jabber:1;
666 uint64_t fcserr:1;
667 uint64_t alnerr:1;
668 uint64_t lenerr:1;
669 uint64_t rcverr:1;
670 uint64_t skperr:1;
671 uint64_t niberr:1;
672 uint64_t ovrerr:1;
673 uint64_t pcterr:1;
674 uint64_t rsverr:1;
675 uint64_t falerr:1;
676 uint64_t coldet:1;
677 uint64_t ifgerr:1;
678 uint64_t phy_link:1;
679 uint64_t phy_spd:1;
680 uint64_t phy_dupx:1;
681 uint64_t pause_drp:1;
682 uint64_t reserved_20_63:44;
683 } cn58xx;
684 struct cvmx_gmxx_rxx_int_reg_cn61xx {
685 uint64_t minerr:1;
686 uint64_t carext:1;
687 uint64_t reserved_2_2:1;
688 uint64_t jabber:1;
689 uint64_t fcserr:1;
690 uint64_t reserved_5_6:2;
691 uint64_t rcverr:1;
692 uint64_t skperr:1;
693 uint64_t reserved_9_9:1;
694 uint64_t ovrerr:1;
695 uint64_t pcterr:1;
696 uint64_t rsverr:1;
697 uint64_t falerr:1;
698 uint64_t coldet:1;
699 uint64_t ifgerr:1;
700 uint64_t reserved_16_18:3;
701 uint64_t pause_drp:1;
702 uint64_t loc_fault:1;
703 uint64_t rem_fault:1;
704 uint64_t bad_seq:1;
705 uint64_t bad_term:1;
706 uint64_t unsop:1;
707 uint64_t uneop:1;
708 uint64_t undat:1;
709 uint64_t hg2fld:1;
710 uint64_t hg2cc:1;
711 uint64_t reserved_29_63:35;
712 } cn61xx;
713 };
714
715 union cvmx_gmxx_prtx_cfg {
716 uint64_t u64;
717 struct cvmx_gmxx_prtx_cfg_s {
718 uint64_t reserved_22_63:42;
719 uint64_t pknd:6;
720 uint64_t reserved_14_15:2;
721 uint64_t tx_idle:1;
722 uint64_t rx_idle:1;
723 uint64_t reserved_9_11:3;
724 uint64_t speed_msb:1;
725 uint64_t reserved_4_7:4;
726 uint64_t slottime:1;
727 uint64_t duplex:1;
728 uint64_t speed:1;
729 uint64_t en:1;
730 } s;
731 struct cvmx_gmxx_prtx_cfg_cn30xx {
732 uint64_t reserved_4_63:60;
733 uint64_t slottime:1;
734 uint64_t duplex:1;
735 uint64_t speed:1;
736 uint64_t en:1;
737 } cn30xx;
738 struct cvmx_gmxx_prtx_cfg_cn52xx {
739 uint64_t reserved_14_63:50;
740 uint64_t tx_idle:1;
741 uint64_t rx_idle:1;
742 uint64_t reserved_9_11:3;
743 uint64_t speed_msb:1;
744 uint64_t reserved_4_7:4;
745 uint64_t slottime:1;
746 uint64_t duplex:1;
747 uint64_t speed:1;
748 uint64_t en:1;
749 } cn52xx;
750 };
751
752 union cvmx_gmxx_rxx_adr_ctl {
753 uint64_t u64;
754 struct cvmx_gmxx_rxx_adr_ctl_s {
755 uint64_t reserved_4_63:60;
756 uint64_t cam_mode:1;
757 uint64_t mcst:2;
758 uint64_t bcst:1;
759 } s;
760 };
761
762 union cvmx_pip_prt_tagx {
763 uint64_t u64;
764 struct cvmx_pip_prt_tagx_s {
765 uint64_t reserved_54_63:10;
766 uint64_t portadd_en:1;
767 uint64_t inc_hwchk:1;
768 uint64_t reserved_50_51:2;
769 uint64_t grptagbase_msb:2;
770 uint64_t reserved_46_47:2;
771 uint64_t grptagmask_msb:2;
772 uint64_t reserved_42_43:2;
773 uint64_t grp_msb:2;
774 uint64_t grptagbase:4;
775 uint64_t grptagmask:4;
776 uint64_t grptag:1;
777 uint64_t grptag_mskip:1;
778 uint64_t tag_mode:2;
779 uint64_t inc_vs:2;
780 uint64_t inc_vlan:1;
781 uint64_t inc_prt_flag:1;
782 uint64_t ip6_dprt_flag:1;
783 uint64_t ip4_dprt_flag:1;
784 uint64_t ip6_sprt_flag:1;
785 uint64_t ip4_sprt_flag:1;
786 uint64_t ip6_nxth_flag:1;
787 uint64_t ip4_pctl_flag:1;
788 uint64_t ip6_dst_flag:1;
789 uint64_t ip4_dst_flag:1;
790 uint64_t ip6_src_flag:1;
791 uint64_t ip4_src_flag:1;
792 uint64_t tcp6_tag_type:2;
793 uint64_t tcp4_tag_type:2;
794 uint64_t ip6_tag_type:2;
795 uint64_t ip4_tag_type:2;
796 uint64_t non_tag_type:2;
797 uint64_t grp:4;
798 } s;
799 struct cvmx_pip_prt_tagx_cn30xx {
800 uint64_t reserved_40_63:24;
801 uint64_t grptagbase:4;
802 uint64_t grptagmask:4;
803 uint64_t grptag:1;
804 uint64_t reserved_30_30:1;
805 uint64_t tag_mode:2;
806 uint64_t inc_vs:2;
807 uint64_t inc_vlan:1;
808 uint64_t inc_prt_flag:1;
809 uint64_t ip6_dprt_flag:1;
810 uint64_t ip4_dprt_flag:1;
811 uint64_t ip6_sprt_flag:1;
812 uint64_t ip4_sprt_flag:1;
813 uint64_t ip6_nxth_flag:1;
814 uint64_t ip4_pctl_flag:1;
815 uint64_t ip6_dst_flag:1;
816 uint64_t ip4_dst_flag:1;
817 uint64_t ip6_src_flag:1;
818 uint64_t ip4_src_flag:1;
819 uint64_t tcp6_tag_type:2;
820 uint64_t tcp4_tag_type:2;
821 uint64_t ip6_tag_type:2;
822 uint64_t ip4_tag_type:2;
823 uint64_t non_tag_type:2;
824 uint64_t grp:4;
825 } cn30xx;
826 struct cvmx_pip_prt_tagx_cn50xx {
827 uint64_t reserved_40_63:24;
828 uint64_t grptagbase:4;
829 uint64_t grptagmask:4;
830 uint64_t grptag:1;
831 uint64_t grptag_mskip:1;
832 uint64_t tag_mode:2;
833 uint64_t inc_vs:2;
834 uint64_t inc_vlan:1;
835 uint64_t inc_prt_flag:1;
836 uint64_t ip6_dprt_flag:1;
837 uint64_t ip4_dprt_flag:1;
838 uint64_t ip6_sprt_flag:1;
839 uint64_t ip4_sprt_flag:1;
840 uint64_t ip6_nxth_flag:1;
841 uint64_t ip4_pctl_flag:1;
842 uint64_t ip6_dst_flag:1;
843 uint64_t ip4_dst_flag:1;
844 uint64_t ip6_src_flag:1;
845 uint64_t ip4_src_flag:1;
846 uint64_t tcp6_tag_type:2;
847 uint64_t tcp4_tag_type:2;
848 uint64_t ip6_tag_type:2;
849 uint64_t ip4_tag_type:2;
850 uint64_t non_tag_type:2;
851 uint64_t grp:4;
852 } cn50xx;
853 };
854
855 union cvmx_spxx_int_reg {
856 uint64_t u64;
857 struct cvmx_spxx_int_reg_s {
858 uint64_t reserved_32_63:32;
859 uint64_t spf:1;
860 uint64_t reserved_12_30:19;
861 uint64_t calerr:1;
862 uint64_t syncerr:1;
863 uint64_t diperr:1;
864 uint64_t tpaovr:1;
865 uint64_t rsverr:1;
866 uint64_t drwnng:1;
867 uint64_t clserr:1;
868 uint64_t spiovr:1;
869 uint64_t reserved_2_3:2;
870 uint64_t abnorm:1;
871 uint64_t prtnxa:1;
872 } s;
873 };
874
875 union cvmx_spxx_int_msk {
876 uint64_t u64;
877 struct cvmx_spxx_int_msk_s {
878 uint64_t reserved_12_63:52;
879 uint64_t calerr:1;
880 uint64_t syncerr:1;
881 uint64_t diperr:1;
882 uint64_t tpaovr:1;
883 uint64_t rsverr:1;
884 uint64_t drwnng:1;
885 uint64_t clserr:1;
886 uint64_t spiovr:1;
887 uint64_t reserved_2_3:2;
888 uint64_t abnorm:1;
889 uint64_t prtnxa:1;
890 } s;
891 };
892
893 union cvmx_pow_wq_int {
894 uint64_t u64;
895 struct cvmx_pow_wq_int_s {
896 uint64_t wq_int:16;
897 uint64_t iq_dis:16;
898 uint64_t reserved_32_63:32;
899 } s;
900 };
901
902 union cvmx_sso_wq_int_thrx {
903 uint64_t u64;
904 struct {
905 uint64_t iq_thr:12;
906 uint64_t reserved_12_13:2;
907 uint64_t ds_thr:12;
908 uint64_t reserved_26_27:2;
909 uint64_t tc_thr:4;
910 uint64_t tc_en:1;
911 uint64_t reserved_33_63:31;
912 } s;
913 };
914
915 union cvmx_stxx_int_reg {
916 uint64_t u64;
917 struct cvmx_stxx_int_reg_s {
918 uint64_t reserved_9_63:55;
919 uint64_t syncerr:1;
920 uint64_t frmerr:1;
921 uint64_t unxfrm:1;
922 uint64_t nosync:1;
923 uint64_t diperr:1;
924 uint64_t datovr:1;
925 uint64_t ovrbst:1;
926 uint64_t calpar1:1;
927 uint64_t calpar0:1;
928 } s;
929 };
930
931 union cvmx_stxx_int_msk {
932 uint64_t u64;
933 struct cvmx_stxx_int_msk_s {
934 uint64_t reserved_8_63:56;
935 uint64_t frmerr:1;
936 uint64_t unxfrm:1;
937 uint64_t nosync:1;
938 uint64_t diperr:1;
939 uint64_t datovr:1;
940 uint64_t ovrbst:1;
941 uint64_t calpar1:1;
942 uint64_t calpar0:1;
943 } s;
944 };
945
946 union cvmx_pow_wq_int_pc {
947 uint64_t u64;
948 struct cvmx_pow_wq_int_pc_s {
949 uint64_t reserved_0_7:8;
950 uint64_t pc_thr:20;
951 uint64_t reserved_28_31:4;
952 uint64_t pc:28;
953 uint64_t reserved_60_63:4;
954 } s;
955 };
956
957 union cvmx_pow_wq_int_thrx {
958 uint64_t u64;
959 struct cvmx_pow_wq_int_thrx_s {
960 uint64_t reserved_29_63:35;
961 uint64_t tc_en:1;
962 uint64_t tc_thr:4;
963 uint64_t reserved_23_23:1;
964 uint64_t ds_thr:11;
965 uint64_t reserved_11_11:1;
966 uint64_t iq_thr:11;
967 } s;
968 struct cvmx_pow_wq_int_thrx_cn30xx {
969 uint64_t reserved_29_63:35;
970 uint64_t tc_en:1;
971 uint64_t tc_thr:4;
972 uint64_t reserved_18_23:6;
973 uint64_t ds_thr:6;
974 uint64_t reserved_6_11:6;
975 uint64_t iq_thr:6;
976 } cn30xx;
977 struct cvmx_pow_wq_int_thrx_cn31xx {
978 uint64_t reserved_29_63:35;
979 uint64_t tc_en:1;
980 uint64_t tc_thr:4;
981 uint64_t reserved_20_23:4;
982 uint64_t ds_thr:8;
983 uint64_t reserved_8_11:4;
984 uint64_t iq_thr:8;
985 } cn31xx;
986 struct cvmx_pow_wq_int_thrx_cn52xx {
987 uint64_t reserved_29_63:35;
988 uint64_t tc_en:1;
989 uint64_t tc_thr:4;
990 uint64_t reserved_21_23:3;
991 uint64_t ds_thr:9;
992 uint64_t reserved_9_11:3;
993 uint64_t iq_thr:9;
994 } cn52xx;
995 struct cvmx_pow_wq_int_thrx_cn63xx {
996 uint64_t reserved_29_63:35;
997 uint64_t tc_en:1;
998 uint64_t tc_thr:4;
999 uint64_t reserved_22_23:2;
1000 uint64_t ds_thr:10;
1001 uint64_t reserved_10_11:2;
1002 uint64_t iq_thr:10;
1003 } cn63xx;
1004 };
1005
1006 union cvmx_npi_rsl_int_blocks {
1007 uint64_t u64;
1008 struct cvmx_npi_rsl_int_blocks_s {
1009 uint64_t reserved_32_63:32;
1010 uint64_t rint_31:1;
1011 uint64_t iob:1;
1012 uint64_t reserved_28_29:2;
1013 uint64_t rint_27:1;
1014 uint64_t rint_26:1;
1015 uint64_t rint_25:1;
1016 uint64_t rint_24:1;
1017 uint64_t asx1:1;
1018 uint64_t asx0:1;
1019 uint64_t rint_21:1;
1020 uint64_t pip:1;
1021 uint64_t spx1:1;
1022 uint64_t spx0:1;
1023 uint64_t lmc:1;
1024 uint64_t l2c:1;
1025 uint64_t rint_15:1;
1026 uint64_t reserved_13_14:2;
1027 uint64_t pow:1;
1028 uint64_t tim:1;
1029 uint64_t pko:1;
1030 uint64_t ipd:1;
1031 uint64_t rint_8:1;
1032 uint64_t zip:1;
1033 uint64_t dfa:1;
1034 uint64_t fpa:1;
1035 uint64_t key:1;
1036 uint64_t npi:1;
1037 uint64_t gmx1:1;
1038 uint64_t gmx0:1;
1039 uint64_t mio:1;
1040 } s;
1041 struct cvmx_npi_rsl_int_blocks_cn30xx {
1042 uint64_t reserved_32_63:32;
1043 uint64_t rint_31:1;
1044 uint64_t iob:1;
1045 uint64_t rint_29:1;
1046 uint64_t rint_28:1;
1047 uint64_t rint_27:1;
1048 uint64_t rint_26:1;
1049 uint64_t rint_25:1;
1050 uint64_t rint_24:1;
1051 uint64_t asx1:1;
1052 uint64_t asx0:1;
1053 uint64_t rint_21:1;
1054 uint64_t pip:1;
1055 uint64_t spx1:1;
1056 uint64_t spx0:1;
1057 uint64_t lmc:1;
1058 uint64_t l2c:1;
1059 uint64_t rint_15:1;
1060 uint64_t rint_14:1;
1061 uint64_t usb:1;
1062 uint64_t pow:1;
1063 uint64_t tim:1;
1064 uint64_t pko:1;
1065 uint64_t ipd:1;
1066 uint64_t rint_8:1;
1067 uint64_t zip:1;
1068 uint64_t dfa:1;
1069 uint64_t fpa:1;
1070 uint64_t key:1;
1071 uint64_t npi:1;
1072 uint64_t gmx1:1;
1073 uint64_t gmx0:1;
1074 uint64_t mio:1;
1075 } cn30xx;
1076 struct cvmx_npi_rsl_int_blocks_cn38xx {
1077 uint64_t reserved_32_63:32;
1078 uint64_t rint_31:1;
1079 uint64_t iob:1;
1080 uint64_t rint_29:1;
1081 uint64_t rint_28:1;
1082 uint64_t rint_27:1;
1083 uint64_t rint_26:1;
1084 uint64_t rint_25:1;
1085 uint64_t rint_24:1;
1086 uint64_t asx1:1;
1087 uint64_t asx0:1;
1088 uint64_t rint_21:1;
1089 uint64_t pip:1;
1090 uint64_t spx1:1;
1091 uint64_t spx0:1;
1092 uint64_t lmc:1;
1093 uint64_t l2c:1;
1094 uint64_t rint_15:1;
1095 uint64_t rint_14:1;
1096 uint64_t rint_13:1;
1097 uint64_t pow:1;
1098 uint64_t tim:1;
1099 uint64_t pko:1;
1100 uint64_t ipd:1;
1101 uint64_t rint_8:1;
1102 uint64_t zip:1;
1103 uint64_t dfa:1;
1104 uint64_t fpa:1;
1105 uint64_t key:1;
1106 uint64_t npi:1;
1107 uint64_t gmx1:1;
1108 uint64_t gmx0:1;
1109 uint64_t mio:1;
1110 } cn38xx;
1111 struct cvmx_npi_rsl_int_blocks_cn50xx {
1112 uint64_t reserved_31_63:33;
1113 uint64_t iob:1;
1114 uint64_t lmc1:1;
1115 uint64_t agl:1;
1116 uint64_t reserved_24_27:4;
1117 uint64_t asx1:1;
1118 uint64_t asx0:1;
1119 uint64_t reserved_21_21:1;
1120 uint64_t pip:1;
1121 uint64_t spx1:1;
1122 uint64_t spx0:1;
1123 uint64_t lmc:1;
1124 uint64_t l2c:1;
1125 uint64_t reserved_15_15:1;
1126 uint64_t rad:1;
1127 uint64_t usb:1;
1128 uint64_t pow:1;
1129 uint64_t tim:1;
1130 uint64_t pko:1;
1131 uint64_t ipd:1;
1132 uint64_t reserved_8_8:1;
1133 uint64_t zip:1;
1134 uint64_t dfa:1;
1135 uint64_t fpa:1;
1136 uint64_t key:1;
1137 uint64_t npi:1;
1138 uint64_t gmx1:1;
1139 uint64_t gmx0:1;
1140 uint64_t mio:1;
1141 } cn50xx;
1142 };
1143
1144 union cvmx_pko_command_word0 {
1145 uint64_t u64;
1146 struct {
1147 uint64_t total_bytes:16;
1148 uint64_t segs:6;
1149 uint64_t dontfree:1;
1150 uint64_t ignore_i:1;
1151 uint64_t ipoffp1:7;
1152 uint64_t gather:1;
1153 uint64_t rsp:1;
1154 uint64_t wqp:1;
1155 uint64_t n2:1;
1156 uint64_t le:1;
1157 uint64_t reg0:11;
1158 uint64_t subone0:1;
1159 uint64_t reg1:11;
1160 uint64_t subone1:1;
1161 uint64_t size0:2;
1162 uint64_t size1:2;
1163 } s;
1164 };
1165
1166 union cvmx_ciu_timx {
1167 uint64_t u64;
1168 struct cvmx_ciu_timx_s {
1169 uint64_t reserved_37_63:27;
1170 uint64_t one_shot:1;
1171 uint64_t len:36;
1172 } s;
1173 };
1174
1175 union cvmx_gmxx_rxx_rx_inbnd {
1176 uint64_t u64;
1177 struct cvmx_gmxx_rxx_rx_inbnd_s {
1178 uint64_t status:1;
1179 uint64_t speed:2;
1180 uint64_t duplex:1;
1181 uint64_t reserved_4_63:60;
1182 } s;
1183 };
1184
cvmx_fau_fetch_and_add32(enum cvmx_fau_reg_32 reg,int32_t value)1185 static inline int32_t cvmx_fau_fetch_and_add32(enum cvmx_fau_reg_32 reg,
1186 int32_t value)
1187 {
1188 return value;
1189 }
1190
cvmx_fau_atomic_add32(enum cvmx_fau_reg_32 reg,int32_t value)1191 static inline void cvmx_fau_atomic_add32(enum cvmx_fau_reg_32 reg,
1192 int32_t value)
1193 { }
1194
cvmx_fau_atomic_write32(enum cvmx_fau_reg_32 reg,int32_t value)1195 static inline void cvmx_fau_atomic_write32(enum cvmx_fau_reg_32 reg,
1196 int32_t value)
1197 { }
1198
cvmx_scratch_read64(uint64_t address)1199 static inline uint64_t cvmx_scratch_read64(uint64_t address)
1200 {
1201 return 0;
1202 }
1203
cvmx_scratch_write64(uint64_t address,uint64_t value)1204 static inline void cvmx_scratch_write64(uint64_t address, uint64_t value)
1205 { }
1206
cvmx_wqe_get_grp(struct cvmx_wqe * work)1207 static inline int cvmx_wqe_get_grp(struct cvmx_wqe *work)
1208 {
1209 return 0;
1210 }
1211
cvmx_phys_to_ptr(uint64_t physical_address)1212 static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
1213 {
1214 return (void *)(uintptr_t)(physical_address);
1215 }
1216
cvmx_ptr_to_phys(void * ptr)1217 static inline phys_addr_t cvmx_ptr_to_phys(void *ptr)
1218 {
1219 return (unsigned long)ptr;
1220 }
1221
cvmx_helper_get_interface_num(int ipd_port)1222 static inline int cvmx_helper_get_interface_num(int ipd_port)
1223 {
1224 return ipd_port;
1225 }
1226
cvmx_helper_get_interface_index_num(int ipd_port)1227 static inline int cvmx_helper_get_interface_index_num(int ipd_port)
1228 {
1229 return ipd_port;
1230 }
1231
cvmx_fpa_enable(void)1232 static inline void cvmx_fpa_enable(void)
1233 { }
1234
cvmx_read_csr(uint64_t csr_addr)1235 static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
1236 {
1237 return 0;
1238 }
1239
cvmx_write_csr(uint64_t csr_addr,uint64_t val)1240 static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
1241 { }
1242
cvmx_helper_setup_red(int pass_thresh,int drop_thresh)1243 static inline int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)
1244 {
1245 return 0;
1246 }
1247
cvmx_fpa_alloc(uint64_t pool)1248 static inline void *cvmx_fpa_alloc(uint64_t pool)
1249 {
1250 return NULL;
1251 }
1252
cvmx_fpa_free(void * ptr,uint64_t pool,uint64_t num_cache_lines)1253 static inline void cvmx_fpa_free(void *ptr, uint64_t pool,
1254 uint64_t num_cache_lines)
1255 { }
1256
octeon_is_simulation(void)1257 static inline int octeon_is_simulation(void)
1258 {
1259 return 1;
1260 }
1261
cvmx_pip_get_port_status(uint64_t port_num,uint64_t clear,cvmx_pip_port_status_t * status)1262 static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear,
1263 cvmx_pip_port_status_t *status)
1264 { }
1265
cvmx_pko_get_port_status(uint64_t port_num,uint64_t clear,cvmx_pko_port_status_t * status)1266 static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear,
1267 cvmx_pko_port_status_t *status)
1268 { }
1269
cvmx_helper_interface_get_mode(int interface)1270 static inline cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int
1271 interface)
1272 {
1273 return 0;
1274 }
1275
cvmx_helper_link_get(int ipd_port)1276 static inline union cvmx_helper_link_info cvmx_helper_link_get(int ipd_port)
1277 {
1278 union cvmx_helper_link_info ret = { .u64 = 0 };
1279
1280 return ret;
1281 }
1282
cvmx_helper_link_set(int ipd_port,union cvmx_helper_link_info link_info)1283 static inline int cvmx_helper_link_set(int ipd_port,
1284 union cvmx_helper_link_info link_info)
1285 {
1286 return 0;
1287 }
1288
cvmx_helper_initialize_packet_io_global(void)1289 static inline int cvmx_helper_initialize_packet_io_global(void)
1290 {
1291 return 0;
1292 }
1293
cvmx_helper_get_number_of_interfaces(void)1294 static inline int cvmx_helper_get_number_of_interfaces(void)
1295 {
1296 return 2;
1297 }
1298
cvmx_helper_ports_on_interface(int interface)1299 static inline int cvmx_helper_ports_on_interface(int interface)
1300 {
1301 return 1;
1302 }
1303
cvmx_helper_get_ipd_port(int interface,int port)1304 static inline int cvmx_helper_get_ipd_port(int interface, int port)
1305 {
1306 return 0;
1307 }
1308
cvmx_helper_ipd_and_packet_input_enable(void)1309 static inline int cvmx_helper_ipd_and_packet_input_enable(void)
1310 {
1311 return 0;
1312 }
1313
cvmx_ipd_disable(void)1314 static inline void cvmx_ipd_disable(void)
1315 { }
1316
cvmx_ipd_free_ptr(void)1317 static inline void cvmx_ipd_free_ptr(void)
1318 { }
1319
cvmx_pko_disable(void)1320 static inline void cvmx_pko_disable(void)
1321 { }
1322
cvmx_pko_shutdown(void)1323 static inline void cvmx_pko_shutdown(void)
1324 { }
1325
cvmx_pko_get_base_queue_per_core(int port,int core)1326 static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
1327 {
1328 return port;
1329 }
1330
cvmx_pko_get_base_queue(int port)1331 static inline int cvmx_pko_get_base_queue(int port)
1332 {
1333 return port;
1334 }
1335
cvmx_pko_get_num_queues(int port)1336 static inline int cvmx_pko_get_num_queues(int port)
1337 {
1338 return port;
1339 }
1340
cvmx_get_core_num(void)1341 static inline unsigned int cvmx_get_core_num(void)
1342 {
1343 return 0;
1344 }
1345
cvmx_pow_work_request_async_nocheck(int scr_addr,cvmx_pow_wait_t wait)1346 static inline void cvmx_pow_work_request_async_nocheck(int scr_addr,
1347 cvmx_pow_wait_t wait)
1348 { }
1349
cvmx_pow_work_request_async(int scr_addr,cvmx_pow_wait_t wait)1350 static inline void cvmx_pow_work_request_async(int scr_addr,
1351 cvmx_pow_wait_t wait)
1352 { }
1353
cvmx_pow_work_response_async(int scr_addr)1354 static inline struct cvmx_wqe *cvmx_pow_work_response_async(int scr_addr)
1355 {
1356 struct cvmx_wqe *wqe = (void *)(unsigned long)scr_addr;
1357
1358 return wqe;
1359 }
1360
cvmx_pow_work_request_sync(cvmx_pow_wait_t wait)1361 static inline struct cvmx_wqe *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait)
1362 {
1363 return (void *)(unsigned long)wait;
1364 }
1365
cvmx_spi_restart_interface(int interface,cvmx_spi_mode_t mode,int timeout)1366 static inline int cvmx_spi_restart_interface(int interface,
1367 cvmx_spi_mode_t mode, int timeout)
1368 {
1369 return 0;
1370 }
1371
cvmx_fau_async_fetch_and_add32(uint64_t scraddr,enum cvmx_fau_reg_32 reg,int32_t value)1372 static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr,
1373 enum cvmx_fau_reg_32 reg,
1374 int32_t value)
1375 { }
1376
cvmx_spi4000_check_speed(int interface,int port)1377 static inline union cvmx_gmxx_rxx_rx_inbnd cvmx_spi4000_check_speed(int interface, int port)
1378 {
1379 union cvmx_gmxx_rxx_rx_inbnd r;
1380
1381 r.u64 = 0;
1382 return r;
1383 }
1384
cvmx_pko_send_packet_prepare(uint64_t port,uint64_t queue,cvmx_pko_lock_t use_locking)1385 static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue,
1386 cvmx_pko_lock_t use_locking)
1387 { }
1388
cvmx_pko_send_packet_finish(uint64_t port,uint64_t queue,union cvmx_pko_command_word0 pko_command,union cvmx_buf_ptr packet,cvmx_pko_lock_t use_locking)1389 static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(uint64_t port,
1390 uint64_t queue, union cvmx_pko_command_word0 pko_command,
1391 union cvmx_buf_ptr packet, cvmx_pko_lock_t use_locking)
1392 {
1393 return 0;
1394 }
1395
cvmx_wqe_set_port(struct cvmx_wqe * work,int port)1396 static inline void cvmx_wqe_set_port(struct cvmx_wqe *work, int port)
1397 { }
1398
cvmx_wqe_set_qos(struct cvmx_wqe * work,int qos)1399 static inline void cvmx_wqe_set_qos(struct cvmx_wqe *work, int qos)
1400 { }
1401
cvmx_wqe_get_qos(struct cvmx_wqe * work)1402 static inline int cvmx_wqe_get_qos(struct cvmx_wqe *work)
1403 {
1404 return 0;
1405 }
1406
cvmx_wqe_set_grp(struct cvmx_wqe * work,int grp)1407 static inline void cvmx_wqe_set_grp(struct cvmx_wqe *work, int grp)
1408 { }
1409
cvmx_pow_work_submit(struct cvmx_wqe * wqp,uint32_t tag,enum cvmx_pow_tag_type tag_type,uint64_t qos,uint64_t grp)1410 static inline void cvmx_pow_work_submit(struct cvmx_wqe *wqp, uint32_t tag,
1411 enum cvmx_pow_tag_type tag_type,
1412 uint64_t qos, uint64_t grp)
1413 { }
1414
1415 #define CVMX_ASXX_RX_CLK_SETX(a, b) ((a) + (b))
1416 #define CVMX_ASXX_TX_CLK_SETX(a, b) ((a) + (b))
1417 #define CVMX_CIU_TIMX(a) (a)
1418 #define CVMX_GMXX_RXX_ADR_CAM0(a, b) ((a) + (b))
1419 #define CVMX_GMXX_RXX_ADR_CAM1(a, b) ((a) + (b))
1420 #define CVMX_GMXX_RXX_ADR_CAM2(a, b) ((a) + (b))
1421 #define CVMX_GMXX_RXX_ADR_CAM3(a, b) ((a) + (b))
1422 #define CVMX_GMXX_RXX_ADR_CAM4(a, b) ((a) + (b))
1423 #define CVMX_GMXX_RXX_ADR_CAM5(a, b) ((a) + (b))
1424 #define CVMX_GMXX_RXX_FRM_CTL(a, b) ((a) + (b))
1425 #define CVMX_GMXX_RXX_INT_REG(a, b) ((a) + (b))
1426 #define CVMX_GMXX_SMACX(a, b) ((a) + (b))
1427 #define CVMX_PIP_PRT_TAGX(a) (a)
1428 #define CVMX_POW_PP_GRP_MSKX(a) (a)
1429 #define CVMX_POW_WQ_INT_THRX(a) (a)
1430 #define CVMX_SPXX_INT_MSK(a) (a)
1431 #define CVMX_SPXX_INT_REG(a) (a)
1432 #define CVMX_SSO_PPX_GRP_MSK(a) (a)
1433 #define CVMX_SSO_WQ_INT_THRX(a) (a)
1434 #define CVMX_STXX_INT_MSK(a) (a)
1435 #define CVMX_STXX_INT_REG(a) (a)
1436