1 #include "drmP.h"
2 #include "drm.h"
3 #include "nouveau_drv.h"
4 #include "nouveau_drm.h"
5
6 void
nv40_fb_set_tile_region(struct drm_device * dev,int i)7 nv40_fb_set_tile_region(struct drm_device *dev, int i)
8 {
9 struct drm_nouveau_private *dev_priv = dev->dev_private;
10 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
11
12 switch (dev_priv->chipset) {
13 case 0x40:
14 nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit);
15 nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch);
16 nv_wr32(dev, NV10_PFB_TILE(i), tile->addr);
17 break;
18
19 default:
20 nv_wr32(dev, NV40_PFB_TLIMIT(i), tile->limit);
21 nv_wr32(dev, NV40_PFB_TSIZE(i), tile->pitch);
22 nv_wr32(dev, NV40_PFB_TILE(i), tile->addr);
23 break;
24 }
25 }
26
27 static void
nv40_fb_init_gart(struct drm_device * dev)28 nv40_fb_init_gart(struct drm_device *dev)
29 {
30 struct drm_nouveau_private *dev_priv = dev->dev_private;
31 struct nouveau_gpuobj *gart = dev_priv->gart_info.sg_ctxdma;
32
33 if (dev_priv->gart_info.type != NOUVEAU_GART_HW) {
34 nv_wr32(dev, 0x100800, 0x00000001);
35 return;
36 }
37
38 nv_wr32(dev, 0x100800, gart->pinst | 0x00000002);
39 nv_mask(dev, 0x10008c, 0x00000100, 0x00000100);
40 nv_wr32(dev, 0x100820, 0x00000000);
41 }
42
43 static void
nv44_fb_init_gart(struct drm_device * dev)44 nv44_fb_init_gart(struct drm_device *dev)
45 {
46 struct drm_nouveau_private *dev_priv = dev->dev_private;
47 struct nouveau_gpuobj *gart = dev_priv->gart_info.sg_ctxdma;
48 u32 vinst;
49
50 if (dev_priv->gart_info.type != NOUVEAU_GART_HW) {
51 nv_wr32(dev, 0x100850, 0x80000000);
52 nv_wr32(dev, 0x100800, 0x00000001);
53 return;
54 }
55
56 /* calculate vram address of this PRAMIN block, object
57 * must be allocated on 512KiB alignment, and not exceed
58 * a total size of 512KiB for this to work correctly
59 */
60 vinst = nv_rd32(dev, 0x10020c);
61 vinst -= ((gart->pinst >> 19) + 1) << 19;
62
63 nv_wr32(dev, 0x100850, 0x80000000);
64 nv_wr32(dev, 0x100818, dev_priv->gart_info.dummy.addr);
65
66 nv_wr32(dev, 0x100804, dev_priv->gart_info.aper_size);
67 nv_wr32(dev, 0x100850, 0x00008000);
68 nv_mask(dev, 0x10008c, 0x00000200, 0x00000200);
69 nv_wr32(dev, 0x100820, 0x00000000);
70 nv_wr32(dev, 0x10082c, 0x00000001);
71 nv_wr32(dev, 0x100800, vinst | 0x00000010);
72 }
73
74 int
nv40_fb_init(struct drm_device * dev)75 nv40_fb_init(struct drm_device *dev)
76 {
77 struct drm_nouveau_private *dev_priv = dev->dev_private;
78 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
79 uint32_t tmp;
80 int i;
81
82 if (dev_priv->chipset != 0x40 && dev_priv->chipset != 0x45) {
83 if (nv44_graph_class(dev))
84 nv44_fb_init_gart(dev);
85 else
86 nv40_fb_init_gart(dev);
87 }
88
89 switch (dev_priv->chipset) {
90 case 0x40:
91 case 0x45:
92 tmp = nv_rd32(dev, NV10_PFB_CLOSE_PAGE2);
93 nv_wr32(dev, NV10_PFB_CLOSE_PAGE2, tmp & ~(1 << 15));
94 pfb->num_tiles = NV10_PFB_TILE__SIZE;
95 break;
96 case 0x46: /* G72 */
97 case 0x47: /* G70 */
98 case 0x49: /* G71 */
99 case 0x4b: /* G73 */
100 case 0x4c: /* C51 (G7X version) */
101 pfb->num_tiles = NV40_PFB_TILE__SIZE_1;
102 break;
103 default:
104 pfb->num_tiles = NV40_PFB_TILE__SIZE_0;
105 break;
106 }
107
108 /* Turn all the tiling regions off. */
109 for (i = 0; i < pfb->num_tiles; i++)
110 pfb->set_tile_region(dev, i);
111
112 return 0;
113 }
114
115 void
nv40_fb_takedown(struct drm_device * dev)116 nv40_fb_takedown(struct drm_device *dev)
117 {
118 }
119