1 /*
2 * Machine definitions for boards featuring an NPCM8xx SoC.
3 *
4 * Copyright 2021 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 */
16
17 #include "qemu/osdep.h"
18
19 #include "chardev/char.h"
20 #include "hw/boards.h"
21 #include "hw/arm/npcm8xx.h"
22 #include "hw/core/cpu.h"
23 #include "hw/loader.h"
24 #include "hw/qdev-core.h"
25 #include "hw/qdev-properties.h"
26 #include "qapi/error.h"
27 #include "qemu/error-report.h"
28 #include "qemu/datadir.h"
29 #include "qemu/units.h"
30
31 #define NPCM845_EVB_POWER_ON_STRAPS 0x000017ff
32
33 static const char npcm8xx_default_bootrom[] = "npcm8xx_bootrom.bin";
34
npcm8xx_load_bootrom(MachineState * machine,NPCM8xxState * soc)35 static void npcm8xx_load_bootrom(MachineState *machine, NPCM8xxState *soc)
36 {
37 const char *bios_name = machine->firmware ?: npcm8xx_default_bootrom;
38 g_autofree char *filename = NULL;
39 int ret;
40
41 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
42 if (!filename) {
43 error_report("Could not find ROM image '%s'", bios_name);
44 if (!machine->kernel_filename) {
45 /* We can't boot without a bootrom or a kernel image. */
46 exit(1);
47 }
48 return;
49 }
50 ret = load_image_mr(filename, machine->ram);
51 if (ret < 0) {
52 error_report("Failed to load ROM image '%s'", filename);
53 exit(1);
54 }
55 }
56
npcm8xx_connect_flash(NPCM7xxFIUState * fiu,int cs_no,const char * flash_type,DriveInfo * dinfo)57 static void npcm8xx_connect_flash(NPCM7xxFIUState *fiu, int cs_no,
58 const char *flash_type, DriveInfo *dinfo)
59 {
60 DeviceState *flash;
61 qemu_irq flash_cs;
62
63 flash = qdev_new(flash_type);
64 if (dinfo) {
65 qdev_prop_set_drive(flash, "drive", blk_by_legacy_dinfo(dinfo));
66 }
67 qdev_realize_and_unref(flash, BUS(fiu->spi), &error_fatal);
68
69 flash_cs = qdev_get_gpio_in_named(flash, SSI_GPIO_CS, 0);
70 qdev_connect_gpio_out_named(DEVICE(fiu), "cs", cs_no, flash_cs);
71 }
72
npcm8xx_connect_dram(NPCM8xxState * soc,MemoryRegion * dram)73 static void npcm8xx_connect_dram(NPCM8xxState *soc, MemoryRegion *dram)
74 {
75 memory_region_add_subregion(get_system_memory(), NPCM8XX_DRAM_BA, dram);
76
77 object_property_set_link(OBJECT(soc), "dram-mr", OBJECT(dram),
78 &error_abort);
79 }
80
npcm8xx_create_soc(MachineState * machine,uint32_t hw_straps)81 static NPCM8xxState *npcm8xx_create_soc(MachineState *machine,
82 uint32_t hw_straps)
83 {
84 NPCM8xxMachineClass *nmc = NPCM8XX_MACHINE_GET_CLASS(machine);
85 Object *obj;
86
87 obj = object_new_with_props(nmc->soc_type, OBJECT(machine), "soc",
88 &error_abort, NULL);
89 object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abort);
90
91 return NPCM8XX(obj);
92 }
93
npcm8xx_i2c_get_bus(NPCM8xxState * soc,uint32_t num)94 static I2CBus *npcm8xx_i2c_get_bus(NPCM8xxState *soc, uint32_t num)
95 {
96 g_assert(num < ARRAY_SIZE(soc->smbus));
97 return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus"));
98 }
99
npcm8xx_init_pwm_splitter(NPCM8xxMachine * machine,NPCM8xxState * soc,const int * fan_counts)100 static void npcm8xx_init_pwm_splitter(NPCM8xxMachine *machine,
101 NPCM8xxState *soc, const int *fan_counts)
102 {
103 SplitIRQ *splitters = machine->fan_splitter;
104
105 /*
106 * PWM 0~3 belong to module 0 output 0~3.
107 * PWM 4~7 belong to module 1 output 0~3.
108 */
109 for (int i = 0; i < NPCM8XX_NR_PWM_MODULES; ++i) {
110 for (int j = 0; j < NPCM7XX_PWM_PER_MODULE; ++j) {
111 int splitter_no = i * NPCM7XX_PWM_PER_MODULE + j;
112 DeviceState *splitter;
113
114 if (fan_counts[splitter_no] < 1) {
115 continue;
116 }
117 object_initialize_child(OBJECT(machine), "fan-splitter[*]",
118 &splitters[splitter_no], TYPE_SPLIT_IRQ);
119 splitter = DEVICE(&splitters[splitter_no]);
120 qdev_prop_set_uint16(splitter, "num-lines",
121 fan_counts[splitter_no]);
122 qdev_realize(splitter, NULL, &error_abort);
123 qdev_connect_gpio_out_named(DEVICE(&soc->pwm[i]), "duty-gpio-out",
124 j, qdev_get_gpio_in(splitter, 0));
125 }
126 }
127 }
128
npcm8xx_connect_pwm_fan(NPCM8xxState * soc,SplitIRQ * splitter,int fan_no,int output_no)129 static void npcm8xx_connect_pwm_fan(NPCM8xxState *soc, SplitIRQ *splitter,
130 int fan_no, int output_no)
131 {
132 DeviceState *fan;
133 int fan_input;
134 qemu_irq fan_duty_gpio;
135
136 g_assert(fan_no >= 0 && fan_no <= NPCM7XX_MFT_MAX_FAN_INPUT);
137 /*
138 * Fan 0~1 belong to module 0 input 0~1.
139 * Fan 2~3 belong to module 1 input 0~1.
140 * ...
141 * Fan 14~15 belong to module 7 input 0~1.
142 * Fan 16~17 belong to module 0 input 2~3.
143 * Fan 18~19 belong to module 1 input 2~3.
144 */
145 if (fan_no < 16) {
146 fan = DEVICE(&soc->mft[fan_no / 2]);
147 fan_input = fan_no % 2;
148 } else {
149 fan = DEVICE(&soc->mft[(fan_no - 16) / 2]);
150 fan_input = fan_no % 2 + 2;
151 }
152
153 /* Connect the Fan to PWM module */
154 fan_duty_gpio = qdev_get_gpio_in_named(fan, "duty", fan_input);
155 qdev_connect_gpio_out(DEVICE(splitter), output_no, fan_duty_gpio);
156 }
157
npcm845_evb_i2c_init(NPCM8xxState * soc)158 static void npcm845_evb_i2c_init(NPCM8xxState *soc)
159 {
160 /* tmp100 temperature sensor on SVB, tmp105 is compatible */
161 i2c_slave_create_simple(npcm8xx_i2c_get_bus(soc, 6), "tmp105", 0x48);
162 }
163
npcm845_evb_fan_init(NPCM8xxMachine * machine,NPCM8xxState * soc)164 static void npcm845_evb_fan_init(NPCM8xxMachine *machine, NPCM8xxState *soc)
165 {
166 SplitIRQ *splitter = machine->fan_splitter;
167 static const int fan_counts[] = {2, 2, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0};
168
169 npcm8xx_init_pwm_splitter(machine, soc, fan_counts);
170 npcm8xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0);
171 npcm8xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1);
172 npcm8xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0);
173 npcm8xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1);
174 npcm8xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0);
175 npcm8xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1);
176 npcm8xx_connect_pwm_fan(soc, &splitter[3], 0x06, 0);
177 npcm8xx_connect_pwm_fan(soc, &splitter[3], 0x07, 1);
178 npcm8xx_connect_pwm_fan(soc, &splitter[4], 0x08, 0);
179 npcm8xx_connect_pwm_fan(soc, &splitter[4], 0x09, 1);
180 npcm8xx_connect_pwm_fan(soc, &splitter[5], 0x0a, 0);
181 npcm8xx_connect_pwm_fan(soc, &splitter[5], 0x0b, 1);
182 npcm8xx_connect_pwm_fan(soc, &splitter[6], 0x0c, 0);
183 npcm8xx_connect_pwm_fan(soc, &splitter[6], 0x0d, 1);
184 npcm8xx_connect_pwm_fan(soc, &splitter[7], 0x0e, 0);
185 npcm8xx_connect_pwm_fan(soc, &splitter[7], 0x0f, 1);
186 }
187
npcm845_evb_init(MachineState * machine)188 static void npcm845_evb_init(MachineState *machine)
189 {
190 NPCM8xxState *soc;
191
192 soc = npcm8xx_create_soc(machine, NPCM845_EVB_POWER_ON_STRAPS);
193 npcm8xx_connect_dram(soc, machine->ram);
194 qdev_realize(DEVICE(soc), NULL, &error_fatal);
195
196 npcm8xx_load_bootrom(machine, soc);
197 npcm8xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0));
198 npcm845_evb_i2c_init(soc);
199 npcm845_evb_fan_init(NPCM8XX_MACHINE(machine), soc);
200 npcm8xx_load_kernel(machine, soc);
201 }
202
npcm8xx_set_soc_type(NPCM8xxMachineClass * nmc,const char * type)203 static void npcm8xx_set_soc_type(NPCM8xxMachineClass *nmc, const char *type)
204 {
205 NPCM8xxClass *sc = NPCM8XX_CLASS(object_class_by_name(type));
206 MachineClass *mc = MACHINE_CLASS(nmc);
207
208 nmc->soc_type = type;
209 mc->default_cpus = mc->min_cpus = mc->max_cpus = sc->num_cpus;
210 }
211
npcm8xx_machine_class_init(ObjectClass * oc,const void * data)212 static void npcm8xx_machine_class_init(ObjectClass *oc, const void *data)
213 {
214 MachineClass *mc = MACHINE_CLASS(oc);
215 static const char * const valid_cpu_types[] = {
216 ARM_CPU_TYPE_NAME("cortex-a35"),
217 NULL
218 };
219
220 mc->no_floppy = 1;
221 mc->no_cdrom = 1;
222 mc->no_parallel = 1;
223 mc->default_ram_id = "ram";
224 mc->valid_cpu_types = valid_cpu_types;
225 }
226
npcm845_evb_machine_class_init(ObjectClass * oc,const void * data)227 static void npcm845_evb_machine_class_init(ObjectClass *oc, const void *data)
228 {
229 NPCM8xxMachineClass *nmc = NPCM8XX_MACHINE_CLASS(oc);
230 MachineClass *mc = MACHINE_CLASS(oc);
231
232 npcm8xx_set_soc_type(nmc, TYPE_NPCM8XX);
233
234 mc->desc = "Nuvoton NPCM845 Evaluation Board (Cortex-A35)";
235 mc->init = npcm845_evb_init;
236 mc->default_ram_size = 1 * GiB;
237 };
238
239 static const TypeInfo npcm8xx_machine_types[] = {
240 {
241 .name = TYPE_NPCM8XX_MACHINE,
242 .parent = TYPE_MACHINE,
243 .instance_size = sizeof(NPCM8xxMachine),
244 .class_size = sizeof(NPCM8xxMachineClass),
245 .class_init = npcm8xx_machine_class_init,
246 .abstract = true,
247 }, {
248 .name = MACHINE_TYPE_NAME("npcm845-evb"),
249 .parent = TYPE_NPCM8XX_MACHINE,
250 .class_init = npcm845_evb_machine_class_init,
251 },
252 };
253
254 DEFINE_TYPES(npcm8xx_machine_types)
255