1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/gce/mt8195-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8195-memory-port.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15#include <dt-bindings/power/mt8195-power.h> 16#include <dt-bindings/reset/mt8195-resets.h> 17#include <dt-bindings/thermal/thermal.h> 18#include <dt-bindings/thermal/mediatek,lvts-thermal.h> 19 20/ { 21 compatible = "mediatek,mt8195"; 22 interrupt-parent = <&gic>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 aliases { 27 dp-intf0 = &dp_intf0; 28 dp-intf1 = &dp_intf1; 29 dpi1 = &dpi1; 30 gce0 = &gce0; 31 gce1 = &gce1; 32 hdmi0 = &hdmi; 33 ethdr0 = ðdr0; 34 mutex0 = &mutex; 35 mutex1 = &mutex1; 36 merge1 = &merge1; 37 merge2 = &merge2; 38 merge3 = &merge3; 39 merge4 = &merge4; 40 merge5 = &merge5; 41 vdo1-rdma0 = &vdo1_rdma0; 42 vdo1-rdma1 = &vdo1_rdma1; 43 vdo1-rdma2 = &vdo1_rdma2; 44 vdo1-rdma3 = &vdo1_rdma3; 45 vdo1-rdma4 = &vdo1_rdma4; 46 vdo1-rdma5 = &vdo1_rdma5; 47 vdo1-rdma6 = &vdo1_rdma6; 48 vdo1-rdma7 = &vdo1_rdma7; 49 }; 50 51 cpus { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 55 cpu0: cpu@0 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a55"; 58 reg = <0x000>; 59 enable-method = "psci"; 60 performance-domains = <&performance 0>; 61 clock-frequency = <1701000000>; 62 capacity-dmips-mhz = <308>; 63 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 64 i-cache-size = <32768>; 65 i-cache-line-size = <64>; 66 i-cache-sets = <128>; 67 d-cache-size = <32768>; 68 d-cache-line-size = <64>; 69 d-cache-sets = <128>; 70 next-level-cache = <&l2_0>; 71 #cooling-cells = <2>; 72 }; 73 74 cpu1: cpu@100 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a55"; 77 reg = <0x100>; 78 enable-method = "psci"; 79 performance-domains = <&performance 0>; 80 clock-frequency = <1701000000>; 81 capacity-dmips-mhz = <308>; 82 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 83 i-cache-size = <32768>; 84 i-cache-line-size = <64>; 85 i-cache-sets = <128>; 86 d-cache-size = <32768>; 87 d-cache-line-size = <64>; 88 d-cache-sets = <128>; 89 next-level-cache = <&l2_0>; 90 #cooling-cells = <2>; 91 }; 92 93 cpu2: cpu@200 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a55"; 96 reg = <0x200>; 97 enable-method = "psci"; 98 performance-domains = <&performance 0>; 99 clock-frequency = <1701000000>; 100 capacity-dmips-mhz = <308>; 101 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 102 i-cache-size = <32768>; 103 i-cache-line-size = <64>; 104 i-cache-sets = <128>; 105 d-cache-size = <32768>; 106 d-cache-line-size = <64>; 107 d-cache-sets = <128>; 108 next-level-cache = <&l2_0>; 109 #cooling-cells = <2>; 110 }; 111 112 cpu3: cpu@300 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a55"; 115 reg = <0x300>; 116 enable-method = "psci"; 117 performance-domains = <&performance 0>; 118 clock-frequency = <1701000000>; 119 capacity-dmips-mhz = <308>; 120 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 121 i-cache-size = <32768>; 122 i-cache-line-size = <64>; 123 i-cache-sets = <128>; 124 d-cache-size = <32768>; 125 d-cache-line-size = <64>; 126 d-cache-sets = <128>; 127 next-level-cache = <&l2_0>; 128 #cooling-cells = <2>; 129 }; 130 131 cpu4: cpu@400 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a78"; 134 reg = <0x400>; 135 enable-method = "psci"; 136 performance-domains = <&performance 1>; 137 clock-frequency = <2171000000>; 138 capacity-dmips-mhz = <1024>; 139 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 140 i-cache-size = <65536>; 141 i-cache-line-size = <64>; 142 i-cache-sets = <256>; 143 d-cache-size = <65536>; 144 d-cache-line-size = <64>; 145 d-cache-sets = <256>; 146 next-level-cache = <&l2_1>; 147 #cooling-cells = <2>; 148 }; 149 150 cpu5: cpu@500 { 151 device_type = "cpu"; 152 compatible = "arm,cortex-a78"; 153 reg = <0x500>; 154 enable-method = "psci"; 155 performance-domains = <&performance 1>; 156 clock-frequency = <2171000000>; 157 capacity-dmips-mhz = <1024>; 158 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 159 i-cache-size = <65536>; 160 i-cache-line-size = <64>; 161 i-cache-sets = <256>; 162 d-cache-size = <65536>; 163 d-cache-line-size = <64>; 164 d-cache-sets = <256>; 165 next-level-cache = <&l2_1>; 166 #cooling-cells = <2>; 167 }; 168 169 cpu6: cpu@600 { 170 device_type = "cpu"; 171 compatible = "arm,cortex-a78"; 172 reg = <0x600>; 173 enable-method = "psci"; 174 performance-domains = <&performance 1>; 175 clock-frequency = <2171000000>; 176 capacity-dmips-mhz = <1024>; 177 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 178 i-cache-size = <65536>; 179 i-cache-line-size = <64>; 180 i-cache-sets = <256>; 181 d-cache-size = <65536>; 182 d-cache-line-size = <64>; 183 d-cache-sets = <256>; 184 next-level-cache = <&l2_1>; 185 #cooling-cells = <2>; 186 }; 187 188 cpu7: cpu@700 { 189 device_type = "cpu"; 190 compatible = "arm,cortex-a78"; 191 reg = <0x700>; 192 enable-method = "psci"; 193 performance-domains = <&performance 1>; 194 clock-frequency = <2171000000>; 195 capacity-dmips-mhz = <1024>; 196 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 197 i-cache-size = <65536>; 198 i-cache-line-size = <64>; 199 i-cache-sets = <256>; 200 d-cache-size = <65536>; 201 d-cache-line-size = <64>; 202 d-cache-sets = <256>; 203 next-level-cache = <&l2_1>; 204 #cooling-cells = <2>; 205 }; 206 207 cpu-map { 208 cluster0 { 209 core0 { 210 cpu = <&cpu0>; 211 }; 212 213 core1 { 214 cpu = <&cpu1>; 215 }; 216 217 core2 { 218 cpu = <&cpu2>; 219 }; 220 221 core3 { 222 cpu = <&cpu3>; 223 }; 224 225 core4 { 226 cpu = <&cpu4>; 227 }; 228 229 core5 { 230 cpu = <&cpu5>; 231 }; 232 233 core6 { 234 cpu = <&cpu6>; 235 }; 236 237 core7 { 238 cpu = <&cpu7>; 239 }; 240 }; 241 }; 242 243 idle-states { 244 entry-method = "psci"; 245 246 cpu_ret_l: cpu-retention-l { 247 compatible = "arm,idle-state"; 248 arm,psci-suspend-param = <0x00010001>; 249 local-timer-stop; 250 entry-latency-us = <50>; 251 exit-latency-us = <95>; 252 min-residency-us = <580>; 253 }; 254 255 cpu_ret_b: cpu-retention-b { 256 compatible = "arm,idle-state"; 257 arm,psci-suspend-param = <0x00010001>; 258 local-timer-stop; 259 entry-latency-us = <45>; 260 exit-latency-us = <140>; 261 min-residency-us = <740>; 262 }; 263 264 cpu_off_l: cpu-off-l { 265 compatible = "arm,idle-state"; 266 arm,psci-suspend-param = <0x01010002>; 267 local-timer-stop; 268 entry-latency-us = <55>; 269 exit-latency-us = <155>; 270 min-residency-us = <840>; 271 }; 272 273 cpu_off_b: cpu-off-b { 274 compatible = "arm,idle-state"; 275 arm,psci-suspend-param = <0x01010002>; 276 local-timer-stop; 277 entry-latency-us = <50>; 278 exit-latency-us = <200>; 279 min-residency-us = <1000>; 280 }; 281 }; 282 283 l2_0: l2-cache0 { 284 compatible = "cache"; 285 cache-level = <2>; 286 cache-size = <131072>; 287 cache-line-size = <64>; 288 cache-sets = <512>; 289 next-level-cache = <&l3_0>; 290 cache-unified; 291 }; 292 293 l2_1: l2-cache1 { 294 compatible = "cache"; 295 cache-level = <2>; 296 cache-size = <262144>; 297 cache-line-size = <64>; 298 cache-sets = <512>; 299 next-level-cache = <&l3_0>; 300 cache-unified; 301 }; 302 303 l3_0: l3-cache { 304 compatible = "cache"; 305 cache-level = <3>; 306 cache-size = <2097152>; 307 cache-line-size = <64>; 308 cache-sets = <2048>; 309 cache-unified; 310 }; 311 }; 312 313 dsu-pmu { 314 compatible = "arm,dsu-pmu"; 315 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 316 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 317 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 318 status = "fail"; 319 }; 320 321 dmic_codec: dmic-codec { 322 compatible = "dmic-codec"; 323 num-channels = <2>; 324 wakeup-delay-ms = <50>; 325 }; 326 327 sound: mt8195-sound { 328 mediatek,platform = <&afe>; 329 status = "disabled"; 330 }; 331 332 clk13m: fixed-factor-clock-13m { 333 compatible = "fixed-factor-clock"; 334 #clock-cells = <0>; 335 clocks = <&clk26m>; 336 clock-div = <2>; 337 clock-mult = <1>; 338 clock-output-names = "clk13m"; 339 }; 340 341 clk26m: oscillator-26m { 342 compatible = "fixed-clock"; 343 #clock-cells = <0>; 344 clock-frequency = <26000000>; 345 clock-output-names = "clk26m"; 346 }; 347 348 clk32k: oscillator-32k { 349 compatible = "fixed-clock"; 350 #clock-cells = <0>; 351 clock-frequency = <32768>; 352 clock-output-names = "clk32k"; 353 }; 354 355 performance: performance-controller@11bc10 { 356 compatible = "mediatek,cpufreq-hw"; 357 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 358 #performance-domain-cells = <1>; 359 }; 360 361 gpu_opp_table: opp-table-gpu { 362 compatible = "operating-points-v2"; 363 opp-shared; 364 365 opp-390000000 { 366 opp-hz = /bits/ 64 <390000000>; 367 opp-microvolt = <625000>; 368 }; 369 opp-410000000 { 370 opp-hz = /bits/ 64 <410000000>; 371 opp-microvolt = <631250>; 372 }; 373 opp-431000000 { 374 opp-hz = /bits/ 64 <431000000>; 375 opp-microvolt = <631250>; 376 }; 377 opp-473000000 { 378 opp-hz = /bits/ 64 <473000000>; 379 opp-microvolt = <637500>; 380 }; 381 opp-515000000 { 382 opp-hz = /bits/ 64 <515000000>; 383 opp-microvolt = <637500>; 384 }; 385 opp-556000000 { 386 opp-hz = /bits/ 64 <556000000>; 387 opp-microvolt = <643750>; 388 }; 389 opp-598000000 { 390 opp-hz = /bits/ 64 <598000000>; 391 opp-microvolt = <650000>; 392 }; 393 opp-640000000 { 394 opp-hz = /bits/ 64 <640000000>; 395 opp-microvolt = <650000>; 396 }; 397 opp-670000000 { 398 opp-hz = /bits/ 64 <670000000>; 399 opp-microvolt = <662500>; 400 }; 401 opp-700000000 { 402 opp-hz = /bits/ 64 <700000000>; 403 opp-microvolt = <675000>; 404 }; 405 opp-730000000 { 406 opp-hz = /bits/ 64 <730000000>; 407 opp-microvolt = <687500>; 408 }; 409 opp-760000000 { 410 opp-hz = /bits/ 64 <760000000>; 411 opp-microvolt = <700000>; 412 }; 413 opp-790000000 { 414 opp-hz = /bits/ 64 <790000000>; 415 opp-microvolt = <712500>; 416 }; 417 opp-820000000 { 418 opp-hz = /bits/ 64 <820000000>; 419 opp-microvolt = <725000>; 420 }; 421 opp-850000000 { 422 opp-hz = /bits/ 64 <850000000>; 423 opp-microvolt = <737500>; 424 }; 425 opp-880000000 { 426 opp-hz = /bits/ 64 <880000000>; 427 opp-microvolt = <750000>; 428 }; 429 }; 430 431 pmu-a55 { 432 compatible = "arm,cortex-a55-pmu"; 433 interrupt-parent = <&gic>; 434 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 435 }; 436 437 pmu-a78 { 438 compatible = "arm,cortex-a78-pmu"; 439 interrupt-parent = <&gic>; 440 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 441 }; 442 443 psci { 444 compatible = "arm,psci-1.0"; 445 method = "smc"; 446 }; 447 448 timer: timer { 449 compatible = "arm,armv8-timer"; 450 interrupt-parent = <&gic>; 451 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 452 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 453 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 454 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 455 }; 456 457 soc { 458 #address-cells = <2>; 459 #size-cells = <2>; 460 compatible = "simple-bus"; 461 ranges; 462 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 463 464 gic: interrupt-controller@c000000 { 465 compatible = "arm,gic-v3"; 466 #interrupt-cells = <4>; 467 #redistributor-regions = <1>; 468 interrupt-parent = <&gic>; 469 interrupt-controller; 470 reg = <0 0x0c000000 0 0x40000>, 471 <0 0x0c040000 0 0x200000>; 472 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 473 474 ppi-partitions { 475 ppi_cluster0: interrupt-partition-0 { 476 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 477 }; 478 479 ppi_cluster1: interrupt-partition-1 { 480 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 481 }; 482 }; 483 }; 484 485 topckgen: syscon@10000000 { 486 compatible = "mediatek,mt8195-topckgen", "syscon"; 487 reg = <0 0x10000000 0 0x1000>; 488 #clock-cells = <1>; 489 }; 490 491 infracfg_ao: syscon@10001000 { 492 compatible = "mediatek,mt8195-infracfg_ao", "syscon"; 493 reg = <0 0x10001000 0 0x1000>; 494 #clock-cells = <1>; 495 #reset-cells = <1>; 496 }; 497 498 pericfg: syscon@10003000 { 499 compatible = "mediatek,mt8195-pericfg", "syscon"; 500 reg = <0 0x10003000 0 0x1000>; 501 #clock-cells = <1>; 502 }; 503 504 pio: pinctrl@10005000 { 505 compatible = "mediatek,mt8195-pinctrl"; 506 reg = <0 0x10005000 0 0x1000>, 507 <0 0x11d10000 0 0x1000>, 508 <0 0x11d30000 0 0x1000>, 509 <0 0x11d40000 0 0x1000>, 510 <0 0x11e20000 0 0x1000>, 511 <0 0x11eb0000 0 0x1000>, 512 <0 0x11f40000 0 0x1000>, 513 <0 0x1000b000 0 0x1000>; 514 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 515 "iocfg_br", "iocfg_lm", "iocfg_rb", 516 "iocfg_tl", "eint"; 517 gpio-controller; 518 #gpio-cells = <2>; 519 gpio-ranges = <&pio 0 0 144>; 520 interrupt-controller; 521 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 522 #interrupt-cells = <2>; 523 }; 524 525 scpsys: syscon@10006000 { 526 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; 527 reg = <0 0x10006000 0 0x1000>; 528 529 /* System Power Manager */ 530 spm: power-controller { 531 compatible = "mediatek,mt8195-power-controller"; 532 #address-cells = <1>; 533 #size-cells = <0>; 534 #power-domain-cells = <1>; 535 536 /* power domain of the SoC */ 537 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { 538 reg = <MT8195_POWER_DOMAIN_MFG0>; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 #power-domain-cells = <1>; 542 543 mfg1: power-domain@MT8195_POWER_DOMAIN_MFG1 { 544 reg = <MT8195_POWER_DOMAIN_MFG1>; 545 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>, 546 <&topckgen CLK_TOP_MFG_CORE_TMP>; 547 clock-names = "mfg", "alt"; 548 mediatek,infracfg = <&infracfg_ao>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 #power-domain-cells = <1>; 552 553 power-domain@MT8195_POWER_DOMAIN_MFG2 { 554 reg = <MT8195_POWER_DOMAIN_MFG2>; 555 #power-domain-cells = <0>; 556 }; 557 558 power-domain@MT8195_POWER_DOMAIN_MFG3 { 559 reg = <MT8195_POWER_DOMAIN_MFG3>; 560 #power-domain-cells = <0>; 561 }; 562 563 power-domain@MT8195_POWER_DOMAIN_MFG4 { 564 reg = <MT8195_POWER_DOMAIN_MFG4>; 565 #power-domain-cells = <0>; 566 }; 567 568 power-domain@MT8195_POWER_DOMAIN_MFG5 { 569 reg = <MT8195_POWER_DOMAIN_MFG5>; 570 #power-domain-cells = <0>; 571 }; 572 573 power-domain@MT8195_POWER_DOMAIN_MFG6 { 574 reg = <MT8195_POWER_DOMAIN_MFG6>; 575 #power-domain-cells = <0>; 576 }; 577 }; 578 }; 579 580 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { 581 reg = <MT8195_POWER_DOMAIN_VPPSYS0>; 582 clocks = <&topckgen CLK_TOP_VPP>, 583 <&topckgen CLK_TOP_CAM>, 584 <&topckgen CLK_TOP_CCU>, 585 <&topckgen CLK_TOP_IMG>, 586 <&topckgen CLK_TOP_VENC>, 587 <&topckgen CLK_TOP_VDEC>, 588 <&topckgen CLK_TOP_WPE_VPP>, 589 <&topckgen CLK_TOP_CFG_VPP0>, 590 <&vppsys0 CLK_VPP0_SMI_COMMON>, 591 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, 592 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, 593 <&vppsys0 CLK_VPP0_GALS_VENCSYS>, 594 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, 595 <&vppsys0 CLK_VPP0_GALS_INFRA>, 596 <&vppsys0 CLK_VPP0_GALS_CAMSYS>, 597 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, 598 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, 599 <&vppsys0 CLK_VPP0_SMI_REORDER>, 600 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 601 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 602 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 603 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 604 <&vppsys0 CLK_VPP0_SMI_RSI>, 605 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 606 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 607 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 608 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 609 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", 610 "vppsys4", "vppsys5", "vppsys6", "vppsys7", 611 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", 612 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", 613 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", 614 "vppsys0-12", "vppsys0-13", "vppsys0-14", 615 "vppsys0-15", "vppsys0-16", "vppsys0-17", 616 "vppsys0-18"; 617 mediatek,infracfg = <&infracfg_ao>; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 #power-domain-cells = <1>; 621 622 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { 623 reg = <MT8195_POWER_DOMAIN_VDOSYS0>; 624 clocks = <&topckgen CLK_TOP_CFG_VDO0>, 625 <&vdosys0 CLK_VDO0_SMI_GALS>, 626 <&vdosys0 CLK_VDO0_SMI_COMMON>, 627 <&vdosys0 CLK_VDO0_SMI_EMI>, 628 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 629 <&vdosys0 CLK_VDO0_SMI_LARB>, 630 <&vdosys0 CLK_VDO0_SMI_RSI>; 631 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", 632 "vdosys0-2", "vdosys0-3", 633 "vdosys0-4", "vdosys0-5"; 634 mediatek,infracfg = <&infracfg_ao>; 635 #address-cells = <1>; 636 #size-cells = <0>; 637 #power-domain-cells = <1>; 638 639 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { 640 reg = <MT8195_POWER_DOMAIN_VPPSYS1>; 641 clocks = <&topckgen CLK_TOP_CFG_VPP1>, 642 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 643 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; 644 clock-names = "vppsys1", "vppsys1-0", 645 "vppsys1-1"; 646 mediatek,infracfg = <&infracfg_ao>; 647 #power-domain-cells = <0>; 648 }; 649 650 power-domain@MT8195_POWER_DOMAIN_WPESYS { 651 reg = <MT8195_POWER_DOMAIN_WPESYS>; 652 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 653 <&wpesys CLK_WPE_SMI_LARB8>, 654 <&wpesys CLK_WPE_SMI_LARB7_P>, 655 <&wpesys CLK_WPE_SMI_LARB8_P>; 656 clock-names = "wepsys-0", "wepsys-1", "wepsys-2", 657 "wepsys-3"; 658 mediatek,infracfg = <&infracfg_ao>; 659 #power-domain-cells = <0>; 660 }; 661 662 power-domain@MT8195_POWER_DOMAIN_VDEC0 { 663 reg = <MT8195_POWER_DOMAIN_VDEC0>; 664 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 665 clock-names = "vdec0-0"; 666 mediatek,infracfg = <&infracfg_ao>; 667 #address-cells = <1>; 668 #size-cells = <0>; 669 #power-domain-cells = <0>; 670 671 power-domain@MT8195_POWER_DOMAIN_VDEC1 { 672 reg = <MT8195_POWER_DOMAIN_VDEC1>; 673 clocks = <&vdecsys CLK_VDEC_LARB1>; 674 clock-names = "vdec1-0"; 675 mediatek,infracfg = <&infracfg_ao>; 676 #power-domain-cells = <0>; 677 }; 678 679 power-domain@MT8195_POWER_DOMAIN_VDEC2 { 680 reg = <MT8195_POWER_DOMAIN_VDEC2>; 681 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 682 clock-names = "vdec2-0"; 683 mediatek,infracfg = <&infracfg_ao>; 684 #power-domain-cells = <0>; 685 }; 686 }; 687 688 power-domain@MT8195_POWER_DOMAIN_VENC { 689 reg = <MT8195_POWER_DOMAIN_VENC>; 690 clocks = <&vencsys CLK_VENC_LARB>; 691 clock-names = "venc0-larb"; 692 mediatek,infracfg = <&infracfg_ao>; 693 #address-cells = <1>; 694 #size-cells = <0>; 695 #power-domain-cells = <0>; 696 697 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { 698 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>; 699 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>; 700 clock-names = "venc1-larb"; 701 mediatek,infracfg = <&infracfg_ao>; 702 #power-domain-cells = <0>; 703 }; 704 }; 705 706 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { 707 reg = <MT8195_POWER_DOMAIN_VDOSYS1>; 708 clocks = <&topckgen CLK_TOP_CFG_VDO1>, 709 <&vdosys1 CLK_VDO1_SMI_LARB2>, 710 <&vdosys1 CLK_VDO1_SMI_LARB3>, 711 <&vdosys1 CLK_VDO1_GALS>; 712 clock-names = "vdosys1", "vdosys1-0", 713 "vdosys1-1", "vdosys1-2"; 714 mediatek,infracfg = <&infracfg_ao>; 715 #address-cells = <1>; 716 #size-cells = <0>; 717 #power-domain-cells = <1>; 718 719 power-domain@MT8195_POWER_DOMAIN_DP_TX { 720 reg = <MT8195_POWER_DOMAIN_DP_TX>; 721 mediatek,infracfg = <&infracfg_ao>; 722 #power-domain-cells = <0>; 723 }; 724 725 power-domain@MT8195_POWER_DOMAIN_EPD_TX { 726 reg = <MT8195_POWER_DOMAIN_EPD_TX>; 727 mediatek,infracfg = <&infracfg_ao>; 728 #power-domain-cells = <0>; 729 }; 730 731 power-domain@MT8195_POWER_DOMAIN_HDMI_TX { 732 reg = <MT8195_POWER_DOMAIN_HDMI_TX>; 733 clocks = <&topckgen CLK_TOP_HDMI_APB>; 734 clock-names = "hdmi_tx"; 735 #power-domain-cells = <0>; 736 }; 737 }; 738 739 power-domain@MT8195_POWER_DOMAIN_IMG { 740 reg = <MT8195_POWER_DOMAIN_IMG>; 741 clocks = <&imgsys CLK_IMG_LARB9>, 742 <&imgsys CLK_IMG_GALS>; 743 clock-names = "img-0", "img-1"; 744 mediatek,infracfg = <&infracfg_ao>; 745 #address-cells = <1>; 746 #size-cells = <0>; 747 #power-domain-cells = <1>; 748 749 power-domain@MT8195_POWER_DOMAIN_DIP { 750 reg = <MT8195_POWER_DOMAIN_DIP>; 751 #power-domain-cells = <0>; 752 }; 753 754 power-domain@MT8195_POWER_DOMAIN_IPE { 755 reg = <MT8195_POWER_DOMAIN_IPE>; 756 clocks = <&topckgen CLK_TOP_IPE>, 757 <&imgsys CLK_IMG_IPE>, 758 <&ipesys CLK_IPE_SMI_LARB12>; 759 clock-names = "ipe", "ipe-0", "ipe-1"; 760 mediatek,infracfg = <&infracfg_ao>; 761 #power-domain-cells = <0>; 762 }; 763 }; 764 765 power-domain@MT8195_POWER_DOMAIN_CAM { 766 reg = <MT8195_POWER_DOMAIN_CAM>; 767 clocks = <&camsys CLK_CAM_LARB13>, 768 <&camsys CLK_CAM_LARB14>, 769 <&camsys CLK_CAM_CAM2MM0_GALS>, 770 <&camsys CLK_CAM_CAM2MM1_GALS>, 771 <&camsys CLK_CAM_CAM2SYS_GALS>; 772 clock-names = "cam-0", "cam-1", "cam-2", "cam-3", 773 "cam-4"; 774 mediatek,infracfg = <&infracfg_ao>; 775 #address-cells = <1>; 776 #size-cells = <0>; 777 #power-domain-cells = <1>; 778 779 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { 780 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>; 781 #power-domain-cells = <0>; 782 }; 783 784 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { 785 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>; 786 #power-domain-cells = <0>; 787 }; 788 789 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { 790 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>; 791 #power-domain-cells = <0>; 792 }; 793 }; 794 }; 795 }; 796 797 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { 798 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 799 mediatek,infracfg = <&infracfg_ao>; 800 #power-domain-cells = <0>; 801 }; 802 803 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { 804 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 805 mediatek,infracfg = <&infracfg_ao>; 806 #power-domain-cells = <0>; 807 }; 808 809 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { 810 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; 811 #power-domain-cells = <0>; 812 }; 813 814 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { 815 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 816 #power-domain-cells = <0>; 817 }; 818 819 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { 820 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>; 821 clocks = <&topckgen CLK_TOP_SENINF>, 822 <&topckgen CLK_TOP_SENINF2>; 823 clock-names = "csi_rx_top", "csi_rx_top1"; 824 #power-domain-cells = <0>; 825 }; 826 827 power-domain@MT8195_POWER_DOMAIN_ETHER { 828 reg = <MT8195_POWER_DOMAIN_ETHER>; 829 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 830 clock-names = "ether"; 831 #power-domain-cells = <0>; 832 }; 833 834 power-domain@MT8195_POWER_DOMAIN_ADSP { 835 reg = <MT8195_POWER_DOMAIN_ADSP>; 836 clocks = <&topckgen CLK_TOP_ADSP>, 837 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 838 clock-names = "adsp", "adsp1"; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 mediatek,infracfg = <&infracfg_ao>; 842 #power-domain-cells = <1>; 843 844 power-domain@MT8195_POWER_DOMAIN_AUDIO { 845 reg = <MT8195_POWER_DOMAIN_AUDIO>; 846 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 847 <&topckgen CLK_TOP_AUD_INTBUS>, 848 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 849 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; 850 clock-names = "audio", "audio1", "audio2", 851 "audio3"; 852 mediatek,infracfg = <&infracfg_ao>; 853 #power-domain-cells = <0>; 854 }; 855 }; 856 }; 857 }; 858 859 watchdog: watchdog@10007000 { 860 compatible = "mediatek,mt8195-wdt"; 861 mediatek,disable-extrst; 862 reg = <0 0x10007000 0 0x100>; 863 #reset-cells = <1>; 864 }; 865 866 apmixedsys: syscon@1000c000 { 867 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 868 reg = <0 0x1000c000 0 0x1000>; 869 #clock-cells = <1>; 870 }; 871 872 systimer: timer@10017000 { 873 compatible = "mediatek,mt8195-timer", 874 "mediatek,mt6765-timer"; 875 reg = <0 0x10017000 0 0x1000>; 876 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 877 clocks = <&clk13m>; 878 }; 879 880 pwrap: pwrap@10024000 { 881 compatible = "mediatek,mt8195-pwrap", "syscon"; 882 reg = <0 0x10024000 0 0x1000>; 883 reg-names = "pwrap"; 884 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 885 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 886 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 887 clock-names = "spi", "wrap"; 888 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 889 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 890 }; 891 892 spmi: spmi@10027000 { 893 compatible = "mediatek,mt8195-spmi"; 894 reg = <0 0x10027000 0 0x000e00>, 895 <0 0x10029000 0 0x000100>; 896 reg-names = "pmif", "spmimst"; 897 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 898 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 899 <&topckgen CLK_TOP_SPMI_M_MST>; 900 clock-names = "pmif_sys_ck", 901 "pmif_tmr_ck", 902 "spmimst_clk_mux"; 903 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 904 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 905 }; 906 907 iommu_infra: infra-iommu@10315000 { 908 compatible = "mediatek,mt8195-iommu-infra"; 909 reg = <0 0x10315000 0 0x5000>; 910 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>, 911 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>, 912 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>, 913 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>, 914 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>; 915 #iommu-cells = <1>; 916 }; 917 918 gce0: mailbox@10320000 { 919 compatible = "mediatek,mt8195-gce"; 920 reg = <0 0x10320000 0 0x4000>; 921 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 922 #mbox-cells = <2>; 923 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 924 }; 925 926 gce1: mailbox@10330000 { 927 compatible = "mediatek,mt8195-gce"; 928 reg = <0 0x10330000 0 0x4000>; 929 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; 930 #mbox-cells = <2>; 931 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; 932 }; 933 934 scp: scp@10500000 { 935 compatible = "mediatek,mt8195-scp"; 936 reg = <0 0x10500000 0 0x100000>, 937 <0 0x10720000 0 0xe0000>, 938 <0 0x10700000 0 0x8000>; 939 reg-names = "sram", "cfg", "l1tcm"; 940 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 941 status = "disabled"; 942 }; 943 944 scp_adsp: clock-controller@10720000 { 945 compatible = "mediatek,mt8195-scp_adsp"; 946 reg = <0 0x10720000 0 0x1000>; 947 #clock-cells = <1>; 948 }; 949 950 adsp: dsp@10803000 { 951 compatible = "mediatek,mt8195-dsp"; 952 reg = <0 0x10803000 0 0x1000>, 953 <0 0x10840000 0 0x40000>; 954 reg-names = "cfg", "sram"; 955 clocks = <&topckgen CLK_TOP_ADSP>, 956 <&clk26m>, 957 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 958 <&topckgen CLK_TOP_MAINPLL_D7_D2>, 959 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, 960 <&topckgen CLK_TOP_AUDIO_H>; 961 clock-names = "adsp_sel", 962 "clk26m_ck", 963 "audio_local_bus", 964 "mainpll_d7_d2", 965 "scp_adsp_audiodsp", 966 "audio_h"; 967 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; 968 mbox-names = "rx", "tx"; 969 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 970 status = "disabled"; 971 }; 972 973 adsp_mailbox0: mailbox@10816000 { 974 compatible = "mediatek,mt8195-adsp-mbox"; 975 #mbox-cells = <0>; 976 reg = <0 0x10816000 0 0x1000>; 977 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; 978 }; 979 980 adsp_mailbox1: mailbox@10817000 { 981 compatible = "mediatek,mt8195-adsp-mbox"; 982 #mbox-cells = <0>; 983 reg = <0 0x10817000 0 0x1000>; 984 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; 985 }; 986 987 afe: mt8195-afe-pcm@10890000 { 988 compatible = "mediatek,mt8195-audio"; 989 reg = <0 0x10890000 0 0x10000>; 990 mediatek,topckgen = <&topckgen>; 991 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; 992 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 993 resets = <&watchdog 14>; 994 reset-names = "audiosys"; 995 clocks = <&clk26m>, 996 <&apmixedsys CLK_APMIXED_APLL1>, 997 <&apmixedsys CLK_APMIXED_APLL2>, 998 <&topckgen CLK_TOP_APLL12_DIV0>, 999 <&topckgen CLK_TOP_APLL12_DIV1>, 1000 <&topckgen CLK_TOP_APLL12_DIV2>, 1001 <&topckgen CLK_TOP_APLL12_DIV3>, 1002 <&topckgen CLK_TOP_APLL12_DIV9>, 1003 <&topckgen CLK_TOP_A1SYS_HP>, 1004 <&topckgen CLK_TOP_AUD_INTBUS>, 1005 <&topckgen CLK_TOP_AUDIO_H>, 1006 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 1007 <&topckgen CLK_TOP_DPTX_MCK>, 1008 <&topckgen CLK_TOP_I2SO1_MCK>, 1009 <&topckgen CLK_TOP_I2SO2_MCK>, 1010 <&topckgen CLK_TOP_I2SI1_MCK>, 1011 <&topckgen CLK_TOP_I2SI2_MCK>, 1012 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, 1013 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; 1014 clock-names = "clk26m", 1015 "apll1_ck", 1016 "apll2_ck", 1017 "apll12_div0", 1018 "apll12_div1", 1019 "apll12_div2", 1020 "apll12_div3", 1021 "apll12_div9", 1022 "a1sys_hp_sel", 1023 "aud_intbus_sel", 1024 "audio_h_sel", 1025 "audio_local_bus_sel", 1026 "dptx_m_sel", 1027 "i2so1_m_sel", 1028 "i2so2_m_sel", 1029 "i2si1_m_sel", 1030 "i2si2_m_sel", 1031 "infra_ao_audio_26m_b", 1032 "scp_adsp_audiodsp"; 1033 status = "disabled"; 1034 }; 1035 1036 uart0: serial@11001100 { 1037 compatible = "mediatek,mt8195-uart", 1038 "mediatek,mt6577-uart"; 1039 reg = <0 0x11001100 0 0x100>; 1040 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 1041 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 1042 clock-names = "baud", "bus"; 1043 status = "disabled"; 1044 }; 1045 1046 uart1: serial@11001200 { 1047 compatible = "mediatek,mt8195-uart", 1048 "mediatek,mt6577-uart"; 1049 reg = <0 0x11001200 0 0x100>; 1050 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 1051 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 1052 clock-names = "baud", "bus"; 1053 status = "disabled"; 1054 }; 1055 1056 uart2: serial@11001300 { 1057 compatible = "mediatek,mt8195-uart", 1058 "mediatek,mt6577-uart"; 1059 reg = <0 0x11001300 0 0x100>; 1060 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 1061 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 1062 clock-names = "baud", "bus"; 1063 status = "disabled"; 1064 }; 1065 1066 uart3: serial@11001400 { 1067 compatible = "mediatek,mt8195-uart", 1068 "mediatek,mt6577-uart"; 1069 reg = <0 0x11001400 0 0x100>; 1070 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 1071 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 1072 clock-names = "baud", "bus"; 1073 status = "disabled"; 1074 }; 1075 1076 uart4: serial@11001500 { 1077 compatible = "mediatek,mt8195-uart", 1078 "mediatek,mt6577-uart"; 1079 reg = <0 0x11001500 0 0x100>; 1080 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 1081 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 1082 clock-names = "baud", "bus"; 1083 status = "disabled"; 1084 }; 1085 1086 uart5: serial@11001600 { 1087 compatible = "mediatek,mt8195-uart", 1088 "mediatek,mt6577-uart"; 1089 reg = <0 0x11001600 0 0x100>; 1090 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 1091 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 1092 clock-names = "baud", "bus"; 1093 status = "disabled"; 1094 }; 1095 1096 auxadc: auxadc@11002000 { 1097 compatible = "mediatek,mt8195-auxadc", 1098 "mediatek,mt8173-auxadc"; 1099 reg = <0 0x11002000 0 0x1000>; 1100 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 1101 clock-names = "main"; 1102 #io-channel-cells = <1>; 1103 status = "disabled"; 1104 }; 1105 1106 pericfg_ao: syscon@11003000 { 1107 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 1108 reg = <0 0x11003000 0 0x1000>; 1109 #clock-cells = <1>; 1110 }; 1111 1112 spi0: spi@1100a000 { 1113 compatible = "mediatek,mt8195-spi", 1114 "mediatek,mt6765-spi"; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 reg = <0 0x1100a000 0 0x1000>; 1118 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 1119 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1120 <&topckgen CLK_TOP_SPI>, 1121 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1122 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1123 status = "disabled"; 1124 }; 1125 1126 lvts_ap: thermal-sensor@1100b000 { 1127 compatible = "mediatek,mt8195-lvts-ap"; 1128 reg = <0 0x1100b000 0 0xc00>; 1129 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 1130 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1131 resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; 1132 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1133 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1134 #thermal-sensor-cells = <1>; 1135 }; 1136 1137 svs: svs@1100bc00 { 1138 compatible = "mediatek,mt8195-svs"; 1139 reg = <0 0x1100bc00 0 0x400>; 1140 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 0>; 1141 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1142 clock-names = "main"; 1143 nvmem-cells = <&svs_calib_data &lvts_efuse_data1>; 1144 nvmem-cell-names = "svs-calibration-data", "t-calibration-data"; 1145 resets = <&infracfg_ao MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST>; 1146 reset-names = "svs_rst"; 1147 }; 1148 1149 disp_pwm0: pwm@1100e000 { 1150 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; 1151 reg = <0 0x1100e000 0 0x1000>; 1152 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>; 1153 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 1154 #pwm-cells = <2>; 1155 clocks = <&topckgen CLK_TOP_DISP_PWM0>, 1156 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 1157 clock-names = "main", "mm"; 1158 status = "disabled"; 1159 }; 1160 1161 disp_pwm1: pwm@1100f000 { 1162 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; 1163 reg = <0 0x1100f000 0 0x1000>; 1164 interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>; 1165 #pwm-cells = <2>; 1166 clocks = <&topckgen CLK_TOP_DISP_PWM1>, 1167 <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>; 1168 clock-names = "main", "mm"; 1169 status = "disabled"; 1170 }; 1171 1172 spi1: spi@11010000 { 1173 compatible = "mediatek,mt8195-spi", 1174 "mediatek,mt6765-spi"; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 reg = <0 0x11010000 0 0x1000>; 1178 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 1179 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1180 <&topckgen CLK_TOP_SPI>, 1181 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1182 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1183 status = "disabled"; 1184 }; 1185 1186 spi2: spi@11012000 { 1187 compatible = "mediatek,mt8195-spi", 1188 "mediatek,mt6765-spi"; 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 reg = <0 0x11012000 0 0x1000>; 1192 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 1193 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1194 <&topckgen CLK_TOP_SPI>, 1195 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1196 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1197 status = "disabled"; 1198 }; 1199 1200 spi3: spi@11013000 { 1201 compatible = "mediatek,mt8195-spi", 1202 "mediatek,mt6765-spi"; 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 reg = <0 0x11013000 0 0x1000>; 1206 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 1207 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1208 <&topckgen CLK_TOP_SPI>, 1209 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1210 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1211 status = "disabled"; 1212 }; 1213 1214 spi4: spi@11018000 { 1215 compatible = "mediatek,mt8195-spi", 1216 "mediatek,mt6765-spi"; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 reg = <0 0x11018000 0 0x1000>; 1220 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1221 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1222 <&topckgen CLK_TOP_SPI>, 1223 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1224 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1225 status = "disabled"; 1226 }; 1227 1228 spi5: spi@11019000 { 1229 compatible = "mediatek,mt8195-spi", 1230 "mediatek,mt6765-spi"; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 reg = <0 0x11019000 0 0x1000>; 1234 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1235 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1236 <&topckgen CLK_TOP_SPI>, 1237 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1238 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1239 status = "disabled"; 1240 }; 1241 1242 spis0: spi@1101d000 { 1243 compatible = "mediatek,mt8195-spi-slave"; 1244 reg = <0 0x1101d000 0 0x1000>; 1245 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 1246 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 1247 clock-names = "spi"; 1248 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1249 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1250 status = "disabled"; 1251 }; 1252 1253 spis1: spi@1101e000 { 1254 compatible = "mediatek,mt8195-spi-slave"; 1255 reg = <0 0x1101e000 0 0x1000>; 1256 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 1257 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 1258 clock-names = "spi"; 1259 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1260 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1261 status = "disabled"; 1262 }; 1263 1264 eth: ethernet@11021000 { 1265 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; 1266 reg = <0 0x11021000 0 0x4000>; 1267 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; 1268 interrupt-names = "macirq"; 1269 clock-names = "axi", 1270 "apb", 1271 "mac_main", 1272 "ptp_ref", 1273 "rmii_internal", 1274 "mac_cg"; 1275 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, 1276 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, 1277 <&topckgen CLK_TOP_SNPS_ETH_250M>, 1278 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1279 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, 1280 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 1281 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, 1282 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1283 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; 1284 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, 1285 <&topckgen CLK_TOP_ETHPLL_D8>, 1286 <&topckgen CLK_TOP_ETHPLL_D10>; 1287 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; 1288 mediatek,pericfg = <&infracfg_ao>; 1289 snps,axi-config = <&stmmac_axi_setup>; 1290 snps,mtl-rx-config = <&mtl_rx_setup>; 1291 snps,mtl-tx-config = <&mtl_tx_setup>; 1292 snps,txpbl = <16>; 1293 snps,rxpbl = <16>; 1294 snps,clk-csr = <0>; 1295 status = "disabled"; 1296 1297 mdio { 1298 compatible = "snps,dwmac-mdio"; 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 }; 1302 1303 stmmac_axi_setup: stmmac-axi-config { 1304 snps,wr_osr_lmt = <0x7>; 1305 snps,rd_osr_lmt = <0x7>; 1306 snps,blen = <0 0 0 0 16 8 4>; 1307 }; 1308 1309 mtl_rx_setup: rx-queues-config { 1310 snps,rx-queues-to-use = <4>; 1311 snps,rx-sched-sp; 1312 queue0 { 1313 snps,dcb-algorithm; 1314 snps,map-to-dma-channel = <0x0>; 1315 }; 1316 queue1 { 1317 snps,dcb-algorithm; 1318 snps,map-to-dma-channel = <0x0>; 1319 }; 1320 queue2 { 1321 snps,dcb-algorithm; 1322 snps,map-to-dma-channel = <0x0>; 1323 }; 1324 queue3 { 1325 snps,dcb-algorithm; 1326 snps,map-to-dma-channel = <0x0>; 1327 }; 1328 }; 1329 1330 mtl_tx_setup: tx-queues-config { 1331 snps,tx-queues-to-use = <4>; 1332 snps,tx-sched-wrr; 1333 queue0 { 1334 snps,weight = <0x10>; 1335 snps,dcb-algorithm; 1336 snps,priority = <0x0>; 1337 }; 1338 queue1 { 1339 snps,weight = <0x11>; 1340 snps,dcb-algorithm; 1341 snps,priority = <0x1>; 1342 }; 1343 queue2 { 1344 snps,weight = <0x12>; 1345 snps,dcb-algorithm; 1346 snps,priority = <0x2>; 1347 }; 1348 queue3 { 1349 snps,weight = <0x13>; 1350 snps,dcb-algorithm; 1351 snps,priority = <0x3>; 1352 }; 1353 }; 1354 }; 1355 1356 ssusb0: usb@11201000 { 1357 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3"; 1358 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; 1359 reg-names = "mac", "ippc"; 1360 ranges = <0 0 0 0x11200000 0 0x3f00>; 1361 #address-cells = <2>; 1362 #size-cells = <2>; 1363 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>; 1364 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1365 <&topckgen CLK_TOP_SSUSB_REF>, 1366 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1367 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1368 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; 1369 wakeup-source; 1370 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 1371 status = "disabled"; 1372 1373 xhci0: usb@0 { 1374 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; 1375 reg = <0 0 0 0x1000>; 1376 reg-names = "mac"; 1377 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1378 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 1379 <&topckgen CLK_TOP_SSUSB_XHCI>; 1380 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1381 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1382 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1383 <&topckgen CLK_TOP_SSUSB_REF>, 1384 <&apmixedsys CLK_APMIXED_USB1PLL>, 1385 <&clk26m>, 1386 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1387 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1388 status = "disabled"; 1389 }; 1390 }; 1391 1392 mmc0: mmc@11230000 { 1393 compatible = "mediatek,mt8195-mmc", 1394 "mediatek,mt8183-mmc"; 1395 reg = <0 0x11230000 0 0x10000>, 1396 <0 0x11f50000 0 0x1000>; 1397 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1398 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1399 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1400 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 1401 clock-names = "source", "hclk", "source_cg"; 1402 status = "disabled"; 1403 }; 1404 1405 mmc1: mmc@11240000 { 1406 compatible = "mediatek,mt8195-mmc", 1407 "mediatek,mt8183-mmc"; 1408 reg = <0 0x11240000 0 0x1000>, 1409 <0 0x11c70000 0 0x1000>; 1410 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1411 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1412 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1413 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1414 clock-names = "source", "hclk", "source_cg"; 1415 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1416 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1417 status = "disabled"; 1418 }; 1419 1420 mmc2: mmc@11250000 { 1421 compatible = "mediatek,mt8195-mmc", 1422 "mediatek,mt8183-mmc"; 1423 reg = <0 0x11250000 0 0x1000>, 1424 <0 0x11e60000 0 0x1000>; 1425 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1426 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1427 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 1428 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 1429 clock-names = "source", "hclk", "source_cg"; 1430 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1431 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1432 status = "disabled"; 1433 }; 1434 1435 ufshci: ufshci@11270000 { 1436 compatible = "mediatek,mt8195-ufshci"; 1437 reg = <0 0x11270000 0 0x2300>; 1438 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH 0>; 1439 phys = <&ufsphy>; 1440 clocks = <&infracfg_ao CLK_INFRA_AO_AES_UFSFDE>, 1441 <&infracfg_ao CLK_INFRA_AO_AES>, 1442 <&infracfg_ao CLK_INFRA_AO_UFS_TICK>, 1443 <&infracfg_ao CLK_INFRA_AO_UNIPRO_SYS>, 1444 <&infracfg_ao CLK_INFRA_AO_UNIPRO_TICK>, 1445 <&infracfg_ao CLK_INFRA_AO_UFS_MP_SAP_B>, 1446 <&infracfg_ao CLK_INFRA_AO_UFS_TX_SYMBOL>, 1447 <&infracfg_ao CLK_INFRA_AO_PERI_UFS_MEM_SUB>; 1448 clock-names = "ufs", "ufs_aes", "ufs_tick", 1449 "unipro_sysclk", "unipro_tick", 1450 "unipro_mp_bclk", "ufs_tx_symbol", 1451 "ufs_mem_sub"; 1452 freq-table-hz = <0 0>, <0 0>, <0 0>, 1453 <0 0>, <0 0>, <0 0>, 1454 <0 0>, <0 0>; 1455 1456 mediatek,ufs-disable-mcq; 1457 status = "disabled"; 1458 }; 1459 1460 lvts_mcu: thermal-sensor@11278000 { 1461 compatible = "mediatek,mt8195-lvts-mcu"; 1462 reg = <0 0x11278000 0 0x1000>; 1463 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 1464 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1465 resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; 1466 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1467 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1468 #thermal-sensor-cells = <1>; 1469 }; 1470 1471 xhci1: usb@11290000 { 1472 compatible = "mediatek,mt8195-xhci", 1473 "mediatek,mtk-xhci"; 1474 reg = <0 0x11290000 0 0x1000>, 1475 <0 0x11293e00 0 0x0100>; 1476 reg-names = "mac", "ippc"; 1477 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 1478 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 1479 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 1480 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 1481 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1482 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1483 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 1484 <&topckgen CLK_TOP_SSUSB_P1_REF>, 1485 <&apmixedsys CLK_APMIXED_USB1PLL>, 1486 <&clk26m>, 1487 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 1488 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1489 "xhci_ck"; 1490 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 1491 wakeup-source; 1492 status = "disabled"; 1493 }; 1494 1495 ssusb2: usb@112a1000 { 1496 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3"; 1497 reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>; 1498 reg-names = "mac", "ippc"; 1499 ranges = <0 0 0 0x112a0000 0 0x3f00>; 1500 #address-cells = <2>; 1501 #size-cells = <2>; 1502 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>; 1503 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>; 1504 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1505 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1506 <&topckgen CLK_TOP_SSUSB_P2_REF>, 1507 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1508 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1509 phys = <&u2port2 PHY_TYPE_USB2>; 1510 wakeup-source; 1511 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 1512 status = "disabled"; 1513 1514 xhci2: usb@0 { 1515 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; 1516 reg = <0 0 0 0x1000>; 1517 reg-names = "mac"; 1518 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1519 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1520 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1521 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1522 clock-names = "sys_ck"; 1523 status = "disabled"; 1524 }; 1525 }; 1526 1527 ssusb3: usb@112b1000 { 1528 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3"; 1529 reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>; 1530 reg-names = "mac", "ippc"; 1531 ranges = <0 0 0 0x112b0000 0 0x3f00>; 1532 #address-cells = <2>; 1533 #size-cells = <2>; 1534 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>; 1535 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>; 1536 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1537 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1538 <&topckgen CLK_TOP_SSUSB_P3_REF>, 1539 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1540 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1541 phys = <&u2port3 PHY_TYPE_USB2>; 1542 wakeup-source; 1543 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 1544 status = "disabled"; 1545 1546 xhci3: usb@0 { 1547 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; 1548 reg = <0 0 0 0x1000>; 1549 reg-names = "mac"; 1550 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1551 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1552 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1553 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1554 clock-names = "sys_ck"; 1555 status = "disabled"; 1556 }; 1557 }; 1558 1559 pcie0: pcie@112f0000 { 1560 compatible = "mediatek,mt8195-pcie", 1561 "mediatek,mt8192-pcie"; 1562 device_type = "pci"; 1563 #address-cells = <3>; 1564 #size-cells = <2>; 1565 reg = <0 0x112f0000 0 0x4000>; 1566 reg-names = "pcie-mac"; 1567 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; 1568 bus-range = <0x00 0xff>; 1569 ranges = <0x81000000 0 0x20000000 1570 0x0 0x20000000 0 0x200000>, 1571 <0x82000000 0 0x20200000 1572 0x0 0x20200000 0 0x3e00000>; 1573 1574 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; 1575 iommu-map-mask = <0x0>; 1576 1577 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, 1578 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, 1579 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1580 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, 1581 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1582 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1583 clock-names = "pl_250m", "tl_26m", "tl_96m", 1584 "tl_32k", "peri_26m", "peri_mem"; 1585 assigned-clocks = <&topckgen CLK_TOP_TL>; 1586 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1587 1588 phys = <&pciephy>; 1589 phy-names = "pcie-phy"; 1590 1591 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 1592 1593 #interrupt-cells = <1>; 1594 interrupt-map-mask = <0 0 0 7>; 1595 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 1596 <0 0 0 2 &pcie_intc0 1>, 1597 <0 0 0 3 &pcie_intc0 2>, 1598 <0 0 0 4 &pcie_intc0 3>; 1599 status = "disabled"; 1600 1601 pcie_intc0: interrupt-controller { 1602 interrupt-controller; 1603 #address-cells = <0>; 1604 #interrupt-cells = <1>; 1605 }; 1606 }; 1607 1608 pcie1: pcie@112f8000 { 1609 compatible = "mediatek,mt8195-pcie", 1610 "mediatek,mt8192-pcie"; 1611 device_type = "pci"; 1612 #address-cells = <3>; 1613 #size-cells = <2>; 1614 reg = <0 0x112f8000 0 0x4000>; 1615 reg-names = "pcie-mac"; 1616 interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>; 1617 bus-range = <0x00 0xff>; 1618 ranges = <0x81000000 0 0x24000000 1619 0x0 0x24000000 0 0x200000>, 1620 <0x82000000 0 0x24200000 1621 0x0 0x24200000 0 0x3e00000>; 1622 1623 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; 1624 iommu-map-mask = <0x0>; 1625 1626 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, 1627 <&clk26m>, 1628 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>, 1629 <&clk26m>, 1630 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>, 1631 /* Designer has connect pcie1 with peri_mem_p0 clock */ 1632 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1633 clock-names = "pl_250m", "tl_26m", "tl_96m", 1634 "tl_32k", "peri_26m", "peri_mem"; 1635 assigned-clocks = <&topckgen CLK_TOP_TL_P1>; 1636 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1637 1638 phys = <&u3port1 PHY_TYPE_PCIE>; 1639 phy-names = "pcie-phy"; 1640 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 1641 1642 #interrupt-cells = <1>; 1643 interrupt-map-mask = <0 0 0 7>; 1644 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 1645 <0 0 0 2 &pcie_intc1 1>, 1646 <0 0 0 3 &pcie_intc1 2>, 1647 <0 0 0 4 &pcie_intc1 3>; 1648 status = "disabled"; 1649 1650 pcie_intc1: interrupt-controller { 1651 interrupt-controller; 1652 #address-cells = <0>; 1653 #interrupt-cells = <1>; 1654 }; 1655 }; 1656 1657 nor_flash: spi@1132c000 { 1658 compatible = "mediatek,mt8195-nor", 1659 "mediatek,mt8173-nor"; 1660 reg = <0 0x1132c000 0 0x1000>; 1661 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1662 clocks = <&topckgen CLK_TOP_SPINOR>, 1663 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 1664 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1665 clock-names = "spi", "sf", "axi"; 1666 #address-cells = <1>; 1667 #size-cells = <0>; 1668 status = "disabled"; 1669 }; 1670 1671 efuse: efuse@11c10000 { 1672 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 1673 reg = <0 0x11c10000 0 0x1000>; 1674 #address-cells = <1>; 1675 #size-cells = <1>; 1676 u3_tx_imp_p0: usb3-tx-imp@184,1 { 1677 reg = <0x184 0x1>; 1678 bits = <0 5>; 1679 }; 1680 u3_rx_imp_p0: usb3-rx-imp@184,2 { 1681 reg = <0x184 0x2>; 1682 bits = <5 5>; 1683 }; 1684 u3_intr_p0: usb3-intr@185 { 1685 reg = <0x185 0x1>; 1686 bits = <2 6>; 1687 }; 1688 comb_tx_imp_p1: usb3-tx-imp@186,1 { 1689 reg = <0x186 0x1>; 1690 bits = <0 5>; 1691 }; 1692 comb_rx_imp_p1: usb3-rx-imp@186,2 { 1693 reg = <0x186 0x2>; 1694 bits = <5 5>; 1695 }; 1696 comb_intr_p1: usb3-intr@187 { 1697 reg = <0x187 0x1>; 1698 bits = <2 6>; 1699 }; 1700 u2_intr_p0: usb2-intr-p0@188,1 { 1701 reg = <0x188 0x1>; 1702 bits = <0 5>; 1703 }; 1704 u2_intr_p1: usb2-intr-p1@188,2 { 1705 reg = <0x188 0x2>; 1706 bits = <5 5>; 1707 }; 1708 u2_intr_p2: usb2-intr-p2@189,1 { 1709 reg = <0x189 0x1>; 1710 bits = <2 5>; 1711 }; 1712 u2_intr_p3: usb2-intr-p3@189,2 { 1713 reg = <0x189 0x2>; 1714 bits = <7 5>; 1715 }; 1716 pciephy_rx_ln1: pciephy-rx-ln1@190,1 { 1717 reg = <0x190 0x1>; 1718 bits = <0 4>; 1719 }; 1720 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 { 1721 reg = <0x190 0x1>; 1722 bits = <4 4>; 1723 }; 1724 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 { 1725 reg = <0x191 0x1>; 1726 bits = <0 4>; 1727 }; 1728 pciephy_rx_ln0: pciephy-rx-ln0@191,2 { 1729 reg = <0x191 0x1>; 1730 bits = <4 4>; 1731 }; 1732 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { 1733 reg = <0x192 0x1>; 1734 bits = <0 4>; 1735 }; 1736 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { 1737 reg = <0x192 0x1>; 1738 bits = <4 4>; 1739 }; 1740 pciephy_glb_intr: pciephy-glb-intr@193 { 1741 reg = <0x193 0x1>; 1742 bits = <0 4>; 1743 }; 1744 dp_calibration: dp-data@1ac { 1745 reg = <0x1ac 0x10>; 1746 }; 1747 lvts_efuse_data1: lvts1-calib@1bc { 1748 reg = <0x1bc 0x14>; 1749 }; 1750 lvts_efuse_data2: lvts2-calib@1d0 { 1751 reg = <0x1d0 0x38>; 1752 }; 1753 svs_calib_data: svs-calib@580 { 1754 reg = <0x580 0x64>; 1755 }; 1756 socinfo-data1@7a0 { 1757 reg = <0x7a0 0x4>; 1758 }; 1759 }; 1760 1761 u3phy2: t-phy@11c40000 { 1762 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1763 #address-cells = <1>; 1764 #size-cells = <1>; 1765 ranges = <0 0 0x11c40000 0x700>; 1766 status = "disabled"; 1767 1768 u2port2: usb-phy@0 { 1769 reg = <0x0 0x700>; 1770 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 1771 clock-names = "ref"; 1772 #phy-cells = <1>; 1773 }; 1774 }; 1775 1776 u3phy3: t-phy@11c50000 { 1777 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1778 #address-cells = <1>; 1779 #size-cells = <1>; 1780 ranges = <0 0 0x11c50000 0x700>; 1781 status = "disabled"; 1782 1783 u2port3: usb-phy@0 { 1784 reg = <0x0 0x700>; 1785 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 1786 clock-names = "ref"; 1787 #phy-cells = <1>; 1788 }; 1789 }; 1790 1791 mipi_tx0: dsi-phy@11c80000 { 1792 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx"; 1793 reg = <0 0x11c80000 0 0x1000>; 1794 clocks = <&clk26m>; 1795 clock-output-names = "mipi_tx0_pll"; 1796 #clock-cells = <0>; 1797 #phy-cells = <0>; 1798 status = "disabled"; 1799 }; 1800 1801 mipi_tx1: dsi-phy@11c90000 { 1802 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx"; 1803 reg = <0 0x11c90000 0 0x1000>; 1804 clocks = <&clk26m>; 1805 clock-output-names = "mipi_tx1_pll"; 1806 #clock-cells = <0>; 1807 #phy-cells = <0>; 1808 status = "disabled"; 1809 }; 1810 1811 i2c5: i2c@11d00000 { 1812 compatible = "mediatek,mt8195-i2c", 1813 "mediatek,mt8192-i2c"; 1814 reg = <0 0x11d00000 0 0x1000>, 1815 <0 0x10220580 0 0x80>; 1816 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 1817 clock-div = <1>; 1818 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 1819 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1820 clock-names = "main", "dma"; 1821 #address-cells = <1>; 1822 #size-cells = <0>; 1823 status = "disabled"; 1824 }; 1825 1826 i2c6: i2c@11d01000 { 1827 compatible = "mediatek,mt8195-i2c", 1828 "mediatek,mt8192-i2c"; 1829 reg = <0 0x11d01000 0 0x1000>, 1830 <0 0x10220600 0 0x80>; 1831 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 1832 clock-div = <1>; 1833 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 1834 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1835 clock-names = "main", "dma"; 1836 #address-cells = <1>; 1837 #size-cells = <0>; 1838 status = "disabled"; 1839 }; 1840 1841 i2c7: i2c@11d02000 { 1842 compatible = "mediatek,mt8195-i2c", 1843 "mediatek,mt8192-i2c"; 1844 reg = <0 0x11d02000 0 0x1000>, 1845 <0 0x10220680 0 0x80>; 1846 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1847 clock-div = <1>; 1848 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1849 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1850 clock-names = "main", "dma"; 1851 #address-cells = <1>; 1852 #size-cells = <0>; 1853 status = "disabled"; 1854 }; 1855 1856 imp_iic_wrap_s: clock-controller@11d03000 { 1857 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 1858 reg = <0 0x11d03000 0 0x1000>; 1859 #clock-cells = <1>; 1860 }; 1861 1862 hdmi_phy: hdmi-phy@11d5f000 { 1863 compatible = "mediatek,mt8195-hdmi-phy"; 1864 reg = <0 0x11d5f000 0 0x100>; 1865 clocks = <&topckgen CLK_TOP_HDMI_XTAL>, 1866 <&infracfg_ao CLK_INFRA_AO_HDMI_26M>, 1867 <&apmixedsys CLK_APMIXED_HDMIPLL1>, 1868 <&apmixedsys CLK_APMIXED_HDMIPLL2>; 1869 clock-names = "pll_ref", "26m", "pll1", "pll2"; 1870 clock-output-names = "hdmi_txpll"; 1871 1872 #clock-cells = <0>; 1873 #phy-cells = <0>; 1874 mediatek,ibias = <0xa>; 1875 mediatek,ibias_up = <0x1c>; 1876 status = "disabled"; 1877 }; 1878 1879 i2c0: i2c@11e00000 { 1880 compatible = "mediatek,mt8195-i2c", 1881 "mediatek,mt8192-i2c"; 1882 reg = <0 0x11e00000 0 0x1000>, 1883 <0 0x10220080 0 0x80>; 1884 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 1885 clock-div = <1>; 1886 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 1887 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1888 clock-names = "main", "dma"; 1889 #address-cells = <1>; 1890 #size-cells = <0>; 1891 status = "disabled"; 1892 }; 1893 1894 i2c1: i2c@11e01000 { 1895 compatible = "mediatek,mt8195-i2c", 1896 "mediatek,mt8192-i2c"; 1897 reg = <0 0x11e01000 0 0x1000>, 1898 <0 0x10220200 0 0x80>; 1899 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1900 clock-div = <1>; 1901 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 1902 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1903 clock-names = "main", "dma"; 1904 #address-cells = <1>; 1905 #size-cells = <0>; 1906 status = "disabled"; 1907 }; 1908 1909 i2c2: i2c@11e02000 { 1910 compatible = "mediatek,mt8195-i2c", 1911 "mediatek,mt8192-i2c"; 1912 reg = <0 0x11e02000 0 0x1000>, 1913 <0 0x10220380 0 0x80>; 1914 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 1915 clock-div = <1>; 1916 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 1917 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1918 clock-names = "main", "dma"; 1919 #address-cells = <1>; 1920 #size-cells = <0>; 1921 status = "disabled"; 1922 }; 1923 1924 i2c3: i2c@11e03000 { 1925 compatible = "mediatek,mt8195-i2c", 1926 "mediatek,mt8192-i2c"; 1927 reg = <0 0x11e03000 0 0x1000>, 1928 <0 0x10220480 0 0x80>; 1929 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1930 clock-div = <1>; 1931 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 1932 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1933 clock-names = "main", "dma"; 1934 #address-cells = <1>; 1935 #size-cells = <0>; 1936 status = "disabled"; 1937 }; 1938 1939 i2c4: i2c@11e04000 { 1940 compatible = "mediatek,mt8195-i2c", 1941 "mediatek,mt8192-i2c"; 1942 reg = <0 0x11e04000 0 0x1000>, 1943 <0 0x10220500 0 0x80>; 1944 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 1945 clock-div = <1>; 1946 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 1947 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1948 clock-names = "main", "dma"; 1949 #address-cells = <1>; 1950 #size-cells = <0>; 1951 status = "disabled"; 1952 }; 1953 1954 imp_iic_wrap_w: clock-controller@11e05000 { 1955 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 1956 reg = <0 0x11e05000 0 0x1000>; 1957 #clock-cells = <1>; 1958 }; 1959 1960 u3phy1: t-phy@11e30000 { 1961 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1962 #address-cells = <1>; 1963 #size-cells = <1>; 1964 ranges = <0 0 0x11e30000 0xe00>; 1965 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 1966 status = "disabled"; 1967 1968 u2port1: usb-phy@0 { 1969 reg = <0x0 0x700>; 1970 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 1971 <&clk26m>; 1972 clock-names = "ref", "da_ref"; 1973 #phy-cells = <1>; 1974 }; 1975 1976 u3port1: usb-phy@700 { 1977 reg = <0x700 0x700>; 1978 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1979 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 1980 clock-names = "ref", "da_ref"; 1981 nvmem-cells = <&comb_intr_p1>, 1982 <&comb_rx_imp_p1>, 1983 <&comb_tx_imp_p1>; 1984 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1985 #phy-cells = <1>; 1986 }; 1987 }; 1988 1989 u3phy0: t-phy@11e40000 { 1990 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1991 #address-cells = <1>; 1992 #size-cells = <1>; 1993 ranges = <0 0 0x11e40000 0xe00>; 1994 status = "disabled"; 1995 1996 u2port0: usb-phy@0 { 1997 reg = <0x0 0x700>; 1998 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 1999 <&clk26m>; 2000 clock-names = "ref", "da_ref"; 2001 #phy-cells = <1>; 2002 }; 2003 2004 u3port0: usb-phy@700 { 2005 reg = <0x700 0x700>; 2006 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 2007 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 2008 clock-names = "ref", "da_ref"; 2009 nvmem-cells = <&u3_intr_p0>, 2010 <&u3_rx_imp_p0>, 2011 <&u3_tx_imp_p0>; 2012 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 2013 #phy-cells = <1>; 2014 }; 2015 }; 2016 2017 pciephy: phy@11e80000 { 2018 compatible = "mediatek,mt8195-pcie-phy"; 2019 reg = <0 0x11e80000 0 0x10000>; 2020 reg-names = "sif"; 2021 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, 2022 <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, 2023 <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, 2024 <&pciephy_rx_ln1>; 2025 nvmem-cell-names = "glb_intr", "tx_ln0_pmos", 2026 "tx_ln0_nmos", "rx_ln0", 2027 "tx_ln1_pmos", "tx_ln1_nmos", 2028 "rx_ln1"; 2029 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; 2030 #phy-cells = <0>; 2031 status = "disabled"; 2032 }; 2033 2034 ufsphy: ufs-phy@11fa0000 { 2035 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 2036 reg = <0 0x11fa0000 0 0xc000>; 2037 clocks = <&clk26m>, <&clk26m>; 2038 clock-names = "unipro", "mp"; 2039 #phy-cells = <0>; 2040 status = "disabled"; 2041 }; 2042 2043 gpu: gpu@13000000 { 2044 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali", 2045 "arm,mali-valhall-jm"; 2046 reg = <0 0x13000000 0 0x4000>; 2047 2048 clocks = <&mfgcfg CLK_MFG_BG3D>; 2049 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, 2050 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, 2051 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>; 2052 interrupt-names = "job", "mmu", "gpu"; 2053 operating-points-v2 = <&gpu_opp_table>; 2054 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>, 2055 <&spm MT8195_POWER_DOMAIN_MFG3>, 2056 <&spm MT8195_POWER_DOMAIN_MFG4>, 2057 <&spm MT8195_POWER_DOMAIN_MFG5>, 2058 <&spm MT8195_POWER_DOMAIN_MFG6>; 2059 power-domain-names = "core0", "core1", "core2", "core3", "core4"; 2060 status = "disabled"; 2061 }; 2062 2063 mfgcfg: clock-controller@13fbf000 { 2064 compatible = "mediatek,mt8195-mfgcfg"; 2065 reg = <0 0x13fbf000 0 0x1000>; 2066 #clock-cells = <1>; 2067 }; 2068 2069 vppsys0: syscon@14000000 { 2070 compatible = "mediatek,mt8195-vppsys0", "syscon"; 2071 reg = <0 0x14000000 0 0x1000>; 2072 #clock-cells = <1>; 2073 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>; 2074 }; 2075 2076 dma-controller@14001000 { 2077 compatible = "mediatek,mt8195-mdp3-rdma"; 2078 reg = <0 0x14001000 0 0x1000>; 2079 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>; 2080 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>, 2081 <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>; 2082 mediatek,scp = <&scp>; 2083 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2084 iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>; 2085 clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>; 2086 mboxes = <&gce1 12 CMDQ_THR_PRIO_1>, 2087 <&gce1 13 CMDQ_THR_PRIO_1>, 2088 <&gce1 14 CMDQ_THR_PRIO_1>, 2089 <&gce1 21 CMDQ_THR_PRIO_1>, 2090 <&gce1 22 CMDQ_THR_PRIO_1>; 2091 #dma-cells = <1>; 2092 }; 2093 2094 display@14002000 { 2095 compatible = "mediatek,mt8195-mdp3-fg"; 2096 reg = <0 0x14002000 0 0x1000>; 2097 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>; 2098 clocks = <&vppsys0 CLK_VPP0_MDP_FG>; 2099 }; 2100 2101 display@14003000 { 2102 compatible = "mediatek,mt8195-mdp3-stitch"; 2103 reg = <0 0x14003000 0 0x1000>; 2104 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>; 2105 clocks = <&vppsys0 CLK_VPP0_STITCH>; 2106 }; 2107 2108 display@14004000 { 2109 compatible = "mediatek,mt8195-mdp3-hdr"; 2110 reg = <0 0x14004000 0 0x1000>; 2111 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>; 2112 clocks = <&vppsys0 CLK_VPP0_MDP_HDR>; 2113 }; 2114 2115 display@14005000 { 2116 compatible = "mediatek,mt8195-mdp3-aal"; 2117 reg = <0 0x14005000 0 0x1000>; 2118 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>; 2119 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>; 2120 clocks = <&vppsys0 CLK_VPP0_MDP_AAL>; 2121 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2122 }; 2123 2124 display@14006000 { 2125 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2126 reg = <0 0x14006000 0 0x1000>; 2127 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>; 2128 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>, 2129 <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>; 2130 clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>; 2131 }; 2132 2133 display@14007000 { 2134 compatible = "mediatek,mt8195-mdp3-tdshp"; 2135 reg = <0 0x14007000 0 0x1000>; 2136 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>; 2137 clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>; 2138 }; 2139 2140 display@14008000 { 2141 compatible = "mediatek,mt8195-mdp3-color"; 2142 reg = <0 0x14008000 0 0x1000>; 2143 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 2144 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>; 2145 clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>; 2146 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2147 }; 2148 2149 display@14009000 { 2150 compatible = "mediatek,mt8195-mdp3-ovl"; 2151 reg = <0 0x14009000 0 0x1000>; 2152 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 2153 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>; 2154 clocks = <&vppsys0 CLK_VPP0_MDP_OVL>; 2155 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2156 iommus = <&iommu_vpp M4U_PORT_L4_MDP_OVL>; 2157 }; 2158 2159 display@1400a000 { 2160 compatible = "mediatek,mt8195-mdp3-padding"; 2161 reg = <0 0x1400a000 0 0x1000>; 2162 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>; 2163 clocks = <&vppsys0 CLK_VPP0_PADDING>; 2164 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2165 }; 2166 2167 display@1400b000 { 2168 compatible = "mediatek,mt8195-mdp3-tcc"; 2169 reg = <0 0x1400b000 0 0x1000>; 2170 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; 2171 clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; 2172 }; 2173 2174 dma-controller@1400c000 { 2175 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2176 reg = <0 0x1400c000 0 0x1000>; 2177 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>; 2178 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>, 2179 <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>; 2180 clocks = <&vppsys0 CLK_VPP0_MDP_WROT>; 2181 iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>; 2182 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2183 #dma-cells = <1>; 2184 }; 2185 2186 mutex@1400f000 { 2187 compatible = "mediatek,mt8195-vpp-mutex"; 2188 reg = <0 0x1400f000 0 0x1000>; 2189 interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>; 2190 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>; 2191 clocks = <&vppsys0 CLK_VPP0_MUTEX>; 2192 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2193 }; 2194 2195 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { 2196 compatible = "mediatek,mt8195-smi-sub-common"; 2197 reg = <0 0x14010000 0 0x1000>; 2198 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 2199 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 2200 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 2201 clock-names = "apb", "smi", "gals0"; 2202 mediatek,smi = <&smi_common_vpp>; 2203 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2204 }; 2205 2206 smi_sub_common_vdec_vpp0_2x1: smi@14011000 { 2207 compatible = "mediatek,mt8195-smi-sub-common"; 2208 reg = <0 0x14011000 0 0x1000>; 2209 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2210 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2211 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>; 2212 clock-names = "apb", "smi", "gals0"; 2213 mediatek,smi = <&smi_common_vpp>; 2214 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2215 }; 2216 2217 smi_common_vpp: smi@14012000 { 2218 compatible = "mediatek,mt8195-smi-common-vpp"; 2219 reg = <0 0x14012000 0 0x1000>; 2220 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2221 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2222 <&vppsys0 CLK_VPP0_SMI_RSI>, 2223 <&vppsys0 CLK_VPP0_SMI_RSI>; 2224 clock-names = "apb", "smi", "gals0", "gals1"; 2225 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2226 }; 2227 2228 larb4: larb@14013000 { 2229 compatible = "mediatek,mt8195-smi-larb"; 2230 reg = <0 0x14013000 0 0x1000>; 2231 mediatek,larb-id = <4>; 2232 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 2233 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 2234 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; 2235 clock-names = "apb", "smi"; 2236 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2237 }; 2238 2239 iommu_vpp: iommu@14018000 { 2240 compatible = "mediatek,mt8195-iommu-vpp"; 2241 reg = <0 0x14018000 0 0x1000>; 2242 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8 2243 &larb12 &larb14 &larb16 &larb18 2244 &larb20 &larb22 &larb23 &larb26 2245 &larb27>; 2246 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; 2247 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; 2248 clock-names = "bclk"; 2249 #iommu-cells = <1>; 2250 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2251 }; 2252 2253 wpesys: clock-controller@14e00000 { 2254 compatible = "mediatek,mt8195-wpesys"; 2255 reg = <0 0x14e00000 0 0x1000>; 2256 #clock-cells = <1>; 2257 }; 2258 2259 wpesys_vpp0: clock-controller@14e02000 { 2260 compatible = "mediatek,mt8195-wpesys_vpp0"; 2261 reg = <0 0x14e02000 0 0x1000>; 2262 #clock-cells = <1>; 2263 }; 2264 2265 wpesys_vpp1: clock-controller@14e03000 { 2266 compatible = "mediatek,mt8195-wpesys_vpp1"; 2267 reg = <0 0x14e03000 0 0x1000>; 2268 #clock-cells = <1>; 2269 }; 2270 2271 larb7: larb@14e04000 { 2272 compatible = "mediatek,mt8195-smi-larb"; 2273 reg = <0 0x14e04000 0 0x1000>; 2274 mediatek,larb-id = <7>; 2275 mediatek,smi = <&smi_common_vdo>; 2276 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 2277 <&wpesys CLK_WPE_SMI_LARB7>; 2278 clock-names = "apb", "smi"; 2279 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 2280 }; 2281 2282 larb8: larb@14e05000 { 2283 compatible = "mediatek,mt8195-smi-larb"; 2284 reg = <0 0x14e05000 0 0x1000>; 2285 mediatek,larb-id = <8>; 2286 mediatek,smi = <&smi_common_vpp>; 2287 clocks = <&wpesys CLK_WPE_SMI_LARB8>, 2288 <&wpesys CLK_WPE_SMI_LARB8>, 2289 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 2290 clock-names = "apb", "smi", "gals"; 2291 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 2292 }; 2293 2294 vppsys1: syscon@14f00000 { 2295 compatible = "mediatek,mt8195-vppsys1", "syscon"; 2296 reg = <0 0x14f00000 0 0x1000>; 2297 #clock-cells = <1>; 2298 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>; 2299 }; 2300 2301 mutex@14f01000 { 2302 compatible = "mediatek,mt8195-vpp-mutex"; 2303 reg = <0 0x14f01000 0 0x1000>; 2304 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 2305 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>; 2306 clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>; 2307 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2308 }; 2309 2310 larb5: larb@14f02000 { 2311 compatible = "mediatek,mt8195-smi-larb"; 2312 reg = <0 0x14f02000 0 0x1000>; 2313 mediatek,larb-id = <5>; 2314 mediatek,smi = <&smi_common_vdo>; 2315 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 2316 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 2317 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>; 2318 clock-names = "apb", "smi", "gals"; 2319 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2320 }; 2321 2322 larb6: larb@14f03000 { 2323 compatible = "mediatek,mt8195-smi-larb"; 2324 reg = <0 0x14f03000 0 0x1000>; 2325 mediatek,larb-id = <6>; 2326 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 2327 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 2328 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 2329 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>; 2330 clock-names = "apb", "smi", "gals"; 2331 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2332 }; 2333 2334 display@14f06000 { 2335 compatible = "mediatek,mt8195-mdp3-split"; 2336 reg = <0 0x14f06000 0 0x1000>; 2337 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>; 2338 clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>, 2339 <&vppsys1 CLK_VPP1_HDMI_META>, 2340 <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; 2341 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2342 }; 2343 2344 display@14f07000 { 2345 compatible = "mediatek,mt8195-mdp3-tcc"; 2346 reg = <0 0x14f07000 0 0x1000>; 2347 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>; 2348 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>; 2349 }; 2350 2351 dma-controller@14f08000 { 2352 compatible = "mediatek,mt8195-mdp3-rdma"; 2353 reg = <0 0x14f08000 0 0x1000>; 2354 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>; 2355 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>, 2356 <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE>; 2357 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>; 2358 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>; 2359 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2360 #dma-cells = <1>; 2361 }; 2362 2363 dma-controller@14f09000 { 2364 compatible = "mediatek,mt8195-mdp3-rdma"; 2365 reg = <0 0x14f09000 0 0x1000>; 2366 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>; 2367 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>, 2368 <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>; 2369 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>; 2370 iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>; 2371 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2372 #dma-cells = <1>; 2373 }; 2374 2375 dma-controller@14f0a000 { 2376 compatible = "mediatek,mt8195-mdp3-rdma"; 2377 reg = <0 0x14f0a000 0 0x1000>; 2378 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>; 2379 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>, 2380 <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>; 2381 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>; 2382 iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>; 2383 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2384 #dma-cells = <1>; 2385 }; 2386 2387 display@14f0b000 { 2388 compatible = "mediatek,mt8195-mdp3-fg"; 2389 reg = <0 0x14f0b000 0 0x1000>; 2390 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>; 2391 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>; 2392 }; 2393 2394 display@14f0c000 { 2395 compatible = "mediatek,mt8195-mdp3-fg"; 2396 reg = <0 0x14f0c000 0 0x1000>; 2397 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>; 2398 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>; 2399 }; 2400 2401 display@14f0d000 { 2402 compatible = "mediatek,mt8195-mdp3-fg"; 2403 reg = <0 0x14f0d000 0 0x1000>; 2404 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>; 2405 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>; 2406 }; 2407 2408 display@14f0e000 { 2409 compatible = "mediatek,mt8195-mdp3-hdr"; 2410 reg = <0 0x14f0e000 0 0x1000>; 2411 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>; 2412 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>; 2413 }; 2414 2415 display@14f0f000 { 2416 compatible = "mediatek,mt8195-mdp3-hdr"; 2417 reg = <0 0x14f0f000 0 0x1000>; 2418 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>; 2419 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>; 2420 }; 2421 2422 display@14f10000 { 2423 compatible = "mediatek,mt8195-mdp3-hdr"; 2424 reg = <0 0x14f10000 0 0x1000>; 2425 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>; 2426 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>; 2427 }; 2428 2429 display@14f11000 { 2430 compatible = "mediatek,mt8195-mdp3-aal"; 2431 reg = <0 0x14f11000 0 0x1000>; 2432 interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH 0>; 2433 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>; 2434 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>; 2435 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2436 }; 2437 2438 display@14f12000 { 2439 compatible = "mediatek,mt8195-mdp3-aal"; 2440 reg = <0 0x14f12000 0 0x1000>; 2441 interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>; 2442 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>; 2443 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>; 2444 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2445 }; 2446 2447 display@14f13000 { 2448 compatible = "mediatek,mt8195-mdp3-aal"; 2449 reg = <0 0x14f13000 0 0x1000>; 2450 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>; 2451 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>; 2452 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>; 2453 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2454 }; 2455 2456 display@14f14000 { 2457 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2458 reg = <0 0x14f14000 0 0x1000>; 2459 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>; 2460 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>, 2461 <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE>; 2462 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>; 2463 }; 2464 2465 display@14f15000 { 2466 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2467 reg = <0 0x14f15000 0 0x1000>; 2468 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>; 2469 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>, 2470 <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>; 2471 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>; 2472 }; 2473 2474 display@14f16000 { 2475 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2476 reg = <0 0x14f16000 0 0x1000>; 2477 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>; 2478 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>, 2479 <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>; 2480 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>; 2481 }; 2482 2483 display@14f17000 { 2484 compatible = "mediatek,mt8195-mdp3-tdshp"; 2485 reg = <0 0x14f17000 0 0x1000>; 2486 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>; 2487 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>; 2488 }; 2489 2490 display@14f18000 { 2491 compatible = "mediatek,mt8195-mdp3-tdshp"; 2492 reg = <0 0x14f18000 0 0x1000>; 2493 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>; 2494 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>; 2495 }; 2496 2497 display@14f19000 { 2498 compatible = "mediatek,mt8195-mdp3-tdshp"; 2499 reg = <0 0x14f19000 0 0x1000>; 2500 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>; 2501 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>; 2502 }; 2503 2504 display@14f1a000 { 2505 compatible = "mediatek,mt8195-mdp3-merge"; 2506 reg = <0 0x14f1a000 0 0x1000>; 2507 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>; 2508 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; 2509 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2510 }; 2511 2512 display@14f1b000 { 2513 compatible = "mediatek,mt8195-mdp3-merge"; 2514 reg = <0 0x14f1b000 0 0x1000>; 2515 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>; 2516 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>; 2517 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2518 }; 2519 2520 display@14f1c000 { 2521 compatible = "mediatek,mt8195-mdp3-color"; 2522 reg = <0 0x14f1c000 0 0x1000>; 2523 interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH 0>; 2524 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>; 2525 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>; 2526 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2527 }; 2528 2529 display@14f1d000 { 2530 compatible = "mediatek,mt8195-mdp3-color"; 2531 reg = <0 0x14f1d000 0 0x1000>; 2532 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>; 2533 interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>; 2534 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>; 2535 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2536 }; 2537 2538 display@14f1e000 { 2539 compatible = "mediatek,mt8195-mdp3-color"; 2540 reg = <0 0x14f1e000 0 0x1000>; 2541 interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>; 2542 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>; 2543 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>; 2544 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2545 }; 2546 2547 display@14f1f000 { 2548 compatible = "mediatek,mt8195-mdp3-ovl"; 2549 reg = <0 0x14f1f000 0 0x1000>; 2550 interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH 0>; 2551 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>; 2552 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>; 2553 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2554 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_OVL>; 2555 }; 2556 2557 display@14f20000 { 2558 compatible = "mediatek,mt8195-mdp3-padding"; 2559 reg = <0 0x14f20000 0 0x1000>; 2560 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>; 2561 clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>; 2562 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2563 }; 2564 2565 display@14f21000 { 2566 compatible = "mediatek,mt8195-mdp3-padding"; 2567 reg = <0 0x14f21000 0 0x1000>; 2568 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>; 2569 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>; 2570 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2571 }; 2572 2573 display@14f22000 { 2574 compatible = "mediatek,mt8195-mdp3-padding"; 2575 reg = <0 0x14f22000 0 0x1000>; 2576 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>; 2577 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>; 2578 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2579 }; 2580 2581 dma-controller@14f23000 { 2582 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2583 reg = <0 0x14f23000 0 0x1000>; 2584 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>; 2585 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>, 2586 <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE>; 2587 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>; 2588 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>; 2589 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2590 #dma-cells = <1>; 2591 }; 2592 2593 dma-controller@14f24000 { 2594 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2595 reg = <0 0x14f24000 0 0x1000>; 2596 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>; 2597 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>, 2598 <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>; 2599 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>; 2600 iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>; 2601 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2602 #dma-cells = <1>; 2603 }; 2604 2605 dma-controller@14f25000 { 2606 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2607 reg = <0 0x14f25000 0 0x1000>; 2608 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>; 2609 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>, 2610 <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>; 2611 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>; 2612 iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>; 2613 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2614 #dma-cells = <1>; 2615 }; 2616 2617 imgsys: clock-controller@15000000 { 2618 compatible = "mediatek,mt8195-imgsys"; 2619 reg = <0 0x15000000 0 0x1000>; 2620 #clock-cells = <1>; 2621 }; 2622 2623 larb9: larb@15001000 { 2624 compatible = "mediatek,mt8195-smi-larb"; 2625 reg = <0 0x15001000 0 0x1000>; 2626 mediatek,larb-id = <9>; 2627 mediatek,smi = <&smi_sub_common_img1_3x1>; 2628 clocks = <&imgsys CLK_IMG_LARB9>, 2629 <&imgsys CLK_IMG_LARB9>, 2630 <&imgsys CLK_IMG_GALS>; 2631 clock-names = "apb", "smi", "gals"; 2632 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2633 }; 2634 2635 smi_sub_common_img0_3x1: smi@15002000 { 2636 compatible = "mediatek,mt8195-smi-sub-common"; 2637 reg = <0 0x15002000 0 0x1000>; 2638 clocks = <&imgsys CLK_IMG_IPE>, 2639 <&imgsys CLK_IMG_IPE>, 2640 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2641 clock-names = "apb", "smi", "gals0"; 2642 mediatek,smi = <&smi_common_vpp>; 2643 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2644 }; 2645 2646 smi_sub_common_img1_3x1: smi@15003000 { 2647 compatible = "mediatek,mt8195-smi-sub-common"; 2648 reg = <0 0x15003000 0 0x1000>; 2649 clocks = <&imgsys CLK_IMG_LARB9>, 2650 <&imgsys CLK_IMG_LARB9>, 2651 <&imgsys CLK_IMG_GALS>; 2652 clock-names = "apb", "smi", "gals0"; 2653 mediatek,smi = <&smi_common_vdo>; 2654 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2655 }; 2656 2657 imgsys1_dip_top: clock-controller@15110000 { 2658 compatible = "mediatek,mt8195-imgsys1_dip_top"; 2659 reg = <0 0x15110000 0 0x1000>; 2660 #clock-cells = <1>; 2661 }; 2662 2663 larb10: larb@15120000 { 2664 compatible = "mediatek,mt8195-smi-larb"; 2665 reg = <0 0x15120000 0 0x1000>; 2666 mediatek,larb-id = <10>; 2667 mediatek,smi = <&smi_sub_common_img1_3x1>; 2668 clocks = <&imgsys CLK_IMG_DIP0>, 2669 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>; 2670 clock-names = "apb", "smi"; 2671 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2672 }; 2673 2674 imgsys1_dip_nr: clock-controller@15130000 { 2675 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 2676 reg = <0 0x15130000 0 0x1000>; 2677 #clock-cells = <1>; 2678 }; 2679 2680 imgsys1_wpe: clock-controller@15220000 { 2681 compatible = "mediatek,mt8195-imgsys1_wpe"; 2682 reg = <0 0x15220000 0 0x1000>; 2683 #clock-cells = <1>; 2684 }; 2685 2686 larb11: larb@15230000 { 2687 compatible = "mediatek,mt8195-smi-larb"; 2688 reg = <0 0x15230000 0 0x1000>; 2689 mediatek,larb-id = <11>; 2690 mediatek,smi = <&smi_sub_common_img1_3x1>; 2691 clocks = <&imgsys CLK_IMG_WPE0>, 2692 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>; 2693 clock-names = "apb", "smi"; 2694 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2695 }; 2696 2697 ipesys: clock-controller@15330000 { 2698 compatible = "mediatek,mt8195-ipesys"; 2699 reg = <0 0x15330000 0 0x1000>; 2700 #clock-cells = <1>; 2701 }; 2702 2703 larb12: larb@15340000 { 2704 compatible = "mediatek,mt8195-smi-larb"; 2705 reg = <0 0x15340000 0 0x1000>; 2706 mediatek,larb-id = <12>; 2707 mediatek,smi = <&smi_sub_common_img0_3x1>; 2708 clocks = <&ipesys CLK_IPE_SMI_LARB12>, 2709 <&ipesys CLK_IPE_SMI_LARB12>; 2710 clock-names = "apb", "smi"; 2711 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>; 2712 }; 2713 2714 camsys: clock-controller@16000000 { 2715 compatible = "mediatek,mt8195-camsys"; 2716 reg = <0 0x16000000 0 0x1000>; 2717 #clock-cells = <1>; 2718 }; 2719 2720 larb13: larb@16001000 { 2721 compatible = "mediatek,mt8195-smi-larb"; 2722 reg = <0 0x16001000 0 0x1000>; 2723 mediatek,larb-id = <13>; 2724 mediatek,smi = <&smi_sub_common_cam_4x1>; 2725 clocks = <&camsys CLK_CAM_LARB13>, 2726 <&camsys CLK_CAM_LARB13>, 2727 <&camsys CLK_CAM_CAM2MM0_GALS>; 2728 clock-names = "apb", "smi", "gals"; 2729 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2730 }; 2731 2732 larb14: larb@16002000 { 2733 compatible = "mediatek,mt8195-smi-larb"; 2734 reg = <0 0x16002000 0 0x1000>; 2735 mediatek,larb-id = <14>; 2736 mediatek,smi = <&smi_sub_common_cam_7x1>; 2737 clocks = <&camsys CLK_CAM_LARB14>, 2738 <&camsys CLK_CAM_LARB14>; 2739 clock-names = "apb", "smi"; 2740 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2741 }; 2742 2743 smi_sub_common_cam_4x1: smi@16004000 { 2744 compatible = "mediatek,mt8195-smi-sub-common"; 2745 reg = <0 0x16004000 0 0x1000>; 2746 clocks = <&camsys CLK_CAM_LARB13>, 2747 <&camsys CLK_CAM_LARB13>, 2748 <&camsys CLK_CAM_CAM2MM0_GALS>; 2749 clock-names = "apb", "smi", "gals0"; 2750 mediatek,smi = <&smi_common_vdo>; 2751 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2752 }; 2753 2754 smi_sub_common_cam_7x1: smi@16005000 { 2755 compatible = "mediatek,mt8195-smi-sub-common"; 2756 reg = <0 0x16005000 0 0x1000>; 2757 clocks = <&camsys CLK_CAM_LARB14>, 2758 <&camsys CLK_CAM_CAM2MM1_GALS>, 2759 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2760 clock-names = "apb", "smi", "gals0"; 2761 mediatek,smi = <&smi_common_vpp>; 2762 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2763 }; 2764 2765 larb16: larb@16012000 { 2766 compatible = "mediatek,mt8195-smi-larb"; 2767 reg = <0 0x16012000 0 0x1000>; 2768 mediatek,larb-id = <16>; 2769 mediatek,smi = <&smi_sub_common_cam_7x1>; 2770 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>, 2771 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 2772 clock-names = "apb", "smi"; 2773 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2774 }; 2775 2776 larb17: larb@16013000 { 2777 compatible = "mediatek,mt8195-smi-larb"; 2778 reg = <0 0x16013000 0 0x1000>; 2779 mediatek,larb-id = <17>; 2780 mediatek,smi = <&smi_sub_common_cam_4x1>; 2781 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>, 2782 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 2783 clock-names = "apb", "smi"; 2784 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2785 }; 2786 2787 larb27: larb@16014000 { 2788 compatible = "mediatek,mt8195-smi-larb"; 2789 reg = <0 0x16014000 0 0x1000>; 2790 mediatek,larb-id = <27>; 2791 mediatek,smi = <&smi_sub_common_cam_7x1>; 2792 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>, 2793 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 2794 clock-names = "apb", "smi"; 2795 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2796 }; 2797 2798 larb28: larb@16015000 { 2799 compatible = "mediatek,mt8195-smi-larb"; 2800 reg = <0 0x16015000 0 0x1000>; 2801 mediatek,larb-id = <28>; 2802 mediatek,smi = <&smi_sub_common_cam_4x1>; 2803 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>, 2804 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 2805 clock-names = "apb", "smi"; 2806 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2807 }; 2808 2809 camsys_rawa: clock-controller@1604f000 { 2810 compatible = "mediatek,mt8195-camsys_rawa"; 2811 reg = <0 0x1604f000 0 0x1000>; 2812 #clock-cells = <1>; 2813 }; 2814 2815 camsys_yuva: clock-controller@1606f000 { 2816 compatible = "mediatek,mt8195-camsys_yuva"; 2817 reg = <0 0x1606f000 0 0x1000>; 2818 #clock-cells = <1>; 2819 }; 2820 2821 camsys_rawb: clock-controller@1608f000 { 2822 compatible = "mediatek,mt8195-camsys_rawb"; 2823 reg = <0 0x1608f000 0 0x1000>; 2824 #clock-cells = <1>; 2825 }; 2826 2827 camsys_yuvb: clock-controller@160af000 { 2828 compatible = "mediatek,mt8195-camsys_yuvb"; 2829 reg = <0 0x160af000 0 0x1000>; 2830 #clock-cells = <1>; 2831 }; 2832 2833 camsys_mraw: clock-controller@16140000 { 2834 compatible = "mediatek,mt8195-camsys_mraw"; 2835 reg = <0 0x16140000 0 0x1000>; 2836 #clock-cells = <1>; 2837 }; 2838 2839 larb25: larb@16141000 { 2840 compatible = "mediatek,mt8195-smi-larb"; 2841 reg = <0 0x16141000 0 0x1000>; 2842 mediatek,larb-id = <25>; 2843 mediatek,smi = <&smi_sub_common_cam_4x1>; 2844 clocks = <&camsys CLK_CAM_LARB13>, 2845 <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2846 <&camsys CLK_CAM_CAM2MM0_GALS>; 2847 clock-names = "apb", "smi", "gals"; 2848 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2849 }; 2850 2851 larb26: larb@16142000 { 2852 compatible = "mediatek,mt8195-smi-larb"; 2853 reg = <0 0x16142000 0 0x1000>; 2854 mediatek,larb-id = <26>; 2855 mediatek,smi = <&smi_sub_common_cam_7x1>; 2856 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2857 <&camsys_mraw CLK_CAM_MRAW_LARBX>; 2858 clock-names = "apb", "smi"; 2859 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2860 2861 }; 2862 2863 ccusys: clock-controller@17200000 { 2864 compatible = "mediatek,mt8195-ccusys"; 2865 reg = <0 0x17200000 0 0x1000>; 2866 #clock-cells = <1>; 2867 }; 2868 2869 larb18: larb@17201000 { 2870 compatible = "mediatek,mt8195-smi-larb"; 2871 reg = <0 0x17201000 0 0x1000>; 2872 mediatek,larb-id = <18>; 2873 mediatek,smi = <&smi_sub_common_cam_7x1>; 2874 clocks = <&ccusys CLK_CCU_LARB18>, 2875 <&ccusys CLK_CCU_LARB18>; 2876 clock-names = "apb", "smi"; 2877 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2878 }; 2879 2880 video-codec@18000000 { 2881 compatible = "mediatek,mt8195-vcodec-dec"; 2882 mediatek,scp = <&scp>; 2883 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>; 2884 #address-cells = <2>; 2885 #size-cells = <2>; 2886 reg = <0 0x18000000 0 0x1000>, 2887 <0 0x18004000 0 0x1000>; 2888 ranges = <0 0 0 0x18000000 0 0x26000>; 2889 2890 video-codec@2000 { 2891 compatible = "mediatek,mtk-vcodec-lat-soc"; 2892 reg = <0 0x2000 0 0x800>; 2893 iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>, 2894 <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>; 2895 clocks = <&topckgen CLK_TOP_VDEC>, 2896 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 2897 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 2898 <&topckgen CLK_TOP_UNIVPLL_D4>; 2899 clock-names = "sel", "vdec", "lat", "top"; 2900 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2901 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2902 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2903 }; 2904 2905 video-codec@10000 { 2906 compatible = "mediatek,mtk-vcodec-lat"; 2907 reg = <0 0x10000 0 0x800>; 2908 interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>; 2909 iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>, 2910 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>, 2911 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>, 2912 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>, 2913 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>, 2914 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>; 2915 clocks = <&topckgen CLK_TOP_VDEC>, 2916 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 2917 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 2918 <&topckgen CLK_TOP_UNIVPLL_D4>; 2919 clock-names = "sel", "vdec", "lat", "top"; 2920 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2921 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2922 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2923 }; 2924 2925 video-codec@25000 { 2926 compatible = "mediatek,mtk-vcodec-core"; 2927 reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */ 2928 interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>; 2929 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>, 2930 <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>, 2931 <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>, 2932 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>, 2933 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>, 2934 <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>, 2935 <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>, 2936 <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>, 2937 <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>, 2938 <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>; 2939 clocks = <&topckgen CLK_TOP_VDEC>, 2940 <&vdecsys CLK_VDEC_VDEC>, 2941 <&vdecsys CLK_VDEC_LAT>, 2942 <&topckgen CLK_TOP_UNIVPLL_D4>; 2943 clock-names = "sel", "vdec", "lat", "top"; 2944 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2945 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2946 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2947 }; 2948 }; 2949 2950 larb24: larb@1800d000 { 2951 compatible = "mediatek,mt8195-smi-larb"; 2952 reg = <0 0x1800d000 0 0x1000>; 2953 mediatek,larb-id = <24>; 2954 mediatek,smi = <&smi_common_vdo>; 2955 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 2956 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2957 clock-names = "apb", "smi"; 2958 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2959 }; 2960 2961 larb23: larb@1800e000 { 2962 compatible = "mediatek,mt8195-smi-larb"; 2963 reg = <0 0x1800e000 0 0x1000>; 2964 mediatek,larb-id = <23>; 2965 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2966 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2967 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2968 clock-names = "apb", "smi"; 2969 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2970 }; 2971 2972 vdecsys_soc: clock-controller@1800f000 { 2973 compatible = "mediatek,mt8195-vdecsys_soc"; 2974 reg = <0 0x1800f000 0 0x1000>; 2975 #clock-cells = <1>; 2976 }; 2977 2978 larb21: larb@1802e000 { 2979 compatible = "mediatek,mt8195-smi-larb"; 2980 reg = <0 0x1802e000 0 0x1000>; 2981 mediatek,larb-id = <21>; 2982 mediatek,smi = <&smi_common_vdo>; 2983 clocks = <&vdecsys CLK_VDEC_LARB1>, 2984 <&vdecsys CLK_VDEC_LARB1>; 2985 clock-names = "apb", "smi"; 2986 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2987 }; 2988 2989 vdecsys: clock-controller@1802f000 { 2990 compatible = "mediatek,mt8195-vdecsys"; 2991 reg = <0 0x1802f000 0 0x1000>; 2992 #clock-cells = <1>; 2993 }; 2994 2995 larb22: larb@1803e000 { 2996 compatible = "mediatek,mt8195-smi-larb"; 2997 reg = <0 0x1803e000 0 0x1000>; 2998 mediatek,larb-id = <22>; 2999 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 3000 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 3001 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 3002 clock-names = "apb", "smi"; 3003 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 3004 }; 3005 3006 vdecsys_core1: clock-controller@1803f000 { 3007 compatible = "mediatek,mt8195-vdecsys_core1"; 3008 reg = <0 0x1803f000 0 0x1000>; 3009 #clock-cells = <1>; 3010 }; 3011 3012 apusys_pll: clock-controller@190f3000 { 3013 compatible = "mediatek,mt8195-apusys_pll"; 3014 reg = <0 0x190f3000 0 0x1000>; 3015 #clock-cells = <1>; 3016 }; 3017 3018 vencsys: clock-controller@1a000000 { 3019 compatible = "mediatek,mt8195-vencsys"; 3020 reg = <0 0x1a000000 0 0x1000>; 3021 #clock-cells = <1>; 3022 }; 3023 3024 larb19: larb@1a010000 { 3025 compatible = "mediatek,mt8195-smi-larb"; 3026 reg = <0 0x1a010000 0 0x1000>; 3027 mediatek,larb-id = <19>; 3028 mediatek,smi = <&smi_common_vdo>; 3029 clocks = <&vencsys CLK_VENC_VENC>, 3030 <&vencsys CLK_VENC_GALS>; 3031 clock-names = "apb", "smi"; 3032 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 3033 }; 3034 3035 venc: video-codec@1a020000 { 3036 compatible = "mediatek,mt8195-vcodec-enc"; 3037 reg = <0 0x1a020000 0 0x10000>; 3038 iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, 3039 <&iommu_vdo M4U_PORT_L19_VENC_REC>, 3040 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, 3041 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, 3042 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, 3043 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, 3044 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, 3045 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, 3046 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; 3047 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; 3048 mediatek,scp = <&scp>; 3049 clocks = <&vencsys CLK_VENC_VENC>; 3050 clock-names = "venc_sel"; 3051 assigned-clocks = <&topckgen CLK_TOP_VENC>; 3052 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 3053 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 3054 #address-cells = <2>; 3055 #size-cells = <2>; 3056 }; 3057 3058 jpeg-decoder@1a040000 { 3059 compatible = "mediatek,mt8195-jpgdec"; 3060 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 3061 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 3062 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 3063 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 3064 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 3065 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 3066 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 3067 #address-cells = <2>; 3068 #size-cells = <2>; 3069 ranges = <0 0 0 0x1a040000 0 0x20000>, 3070 <1 0 0 0x1b040000 0 0x10000>; 3071 3072 jpgdec@0,0 { 3073 compatible = "mediatek,mt8195-jpgdec-hw"; 3074 reg = <0 0 0 0x10000>;/* JPGDEC_C0 */ 3075 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 3076 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 3077 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 3078 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 3079 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 3080 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 3081 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>; 3082 clocks = <&vencsys CLK_VENC_JPGDEC>; 3083 clock-names = "jpgdec"; 3084 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 3085 }; 3086 3087 jpgdec@0,10000 { 3088 compatible = "mediatek,mt8195-jpgdec-hw"; 3089 reg = <0 0x10000 0 0x10000>;/* JPGDEC_C1 */ 3090 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 3091 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 3092 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 3093 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 3094 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 3095 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 3096 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>; 3097 clocks = <&vencsys CLK_VENC_JPGDEC_C1>; 3098 clock-names = "jpgdec"; 3099 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 3100 }; 3101 3102 jpgdec@1,0 { 3103 compatible = "mediatek,mt8195-jpgdec-hw"; 3104 reg = <1 0 0 0x10000>;/* JPGDEC_C2 */ 3105 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>, 3106 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>, 3107 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>, 3108 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>, 3109 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>, 3110 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>; 3111 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>; 3112 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>; 3113 clock-names = "jpgdec"; 3114 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 3115 }; 3116 }; 3117 3118 vencsys_core1: clock-controller@1b000000 { 3119 compatible = "mediatek,mt8195-vencsys_core1"; 3120 reg = <0 0x1b000000 0 0x1000>; 3121 #clock-cells = <1>; 3122 }; 3123 3124 vdosys0: syscon@1c01a000 { 3125 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon"; 3126 reg = <0 0x1c01a000 0 0x1000>; 3127 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; 3128 #clock-cells = <1>; 3129 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; 3130 }; 3131 3132 3133 jpeg-encoder@1a030000 { 3134 compatible = "mediatek,mt8195-jpgenc"; 3135 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 3136 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 3137 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 3138 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 3139 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 3140 #address-cells = <2>; 3141 #size-cells = <2>; 3142 ranges = <0 0 0 0x1a030000 0 0x10000>, 3143 <1 0 0 0x1b030000 0 0x10000>; 3144 3145 jpgenc@0,0 { 3146 compatible = "mediatek,mt8195-jpgenc-hw"; 3147 reg = <0 0 0 0x10000>; 3148 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, 3149 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, 3150 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, 3151 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; 3152 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>; 3153 clocks = <&vencsys CLK_VENC_JPGENC>; 3154 clock-names = "jpgenc"; 3155 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 3156 }; 3157 3158 jpgenc@1,0 { 3159 compatible = "mediatek,mt8195-jpgenc-hw"; 3160 reg = <1 0 0 0x10000>; 3161 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 3162 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 3163 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 3164 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 3165 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>; 3166 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; 3167 clock-names = "jpgenc"; 3168 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 3169 }; 3170 }; 3171 3172 larb20: larb@1b010000 { 3173 compatible = "mediatek,mt8195-smi-larb"; 3174 reg = <0 0x1b010000 0 0x1000>; 3175 mediatek,larb-id = <20>; 3176 mediatek,smi = <&smi_common_vpp>; 3177 clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>, 3178 <&vencsys_core1 CLK_VENC_CORE1_GALS>, 3179 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 3180 clock-names = "apb", "smi", "gals"; 3181 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 3182 }; 3183 3184 ovl0: ovl@1c000000 { 3185 compatible = "mediatek,mt8195-disp-ovl"; 3186 reg = <0 0x1c000000 0 0x1000>; 3187 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 3188 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3189 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; 3190 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; 3191 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; 3192 3193 ports { 3194 #address-cells = <1>; 3195 #size-cells = <0>; 3196 3197 port@0 { 3198 reg = <0>; 3199 ovl0_in: endpoint { }; 3200 }; 3201 3202 port@1 { 3203 reg = <1>; 3204 ovl0_out: endpoint { 3205 remote-endpoint = <&rdma0_in>; 3206 }; 3207 }; 3208 }; 3209 }; 3210 3211 rdma0: rdma@1c002000 { 3212 compatible = "mediatek,mt8195-disp-rdma"; 3213 reg = <0 0x1c002000 0 0x1000>; 3214 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 3215 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3216 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; 3217 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; 3218 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; 3219 3220 ports { 3221 #address-cells = <1>; 3222 #size-cells = <0>; 3223 3224 port@0 { 3225 reg = <0>; 3226 rdma0_in: endpoint { 3227 remote-endpoint = <&ovl0_out>; 3228 }; 3229 }; 3230 3231 port@1 { 3232 reg = <1>; 3233 rdma0_out: endpoint { 3234 remote-endpoint = <&color0_in>; 3235 }; 3236 }; 3237 }; 3238 }; 3239 3240 color0: color@1c003000 { 3241 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color"; 3242 reg = <0 0x1c003000 0 0x1000>; 3243 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 3244 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3245 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; 3246 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; 3247 3248 ports { 3249 #address-cells = <1>; 3250 #size-cells = <0>; 3251 3252 port@0 { 3253 reg = <0>; 3254 color0_in: endpoint { 3255 remote-endpoint = <&rdma0_out>; 3256 }; 3257 }; 3258 3259 port@1 { 3260 reg = <1>; 3261 color0_out: endpoint { 3262 remote-endpoint = <&ccorr0_in>; 3263 }; 3264 }; 3265 }; 3266 }; 3267 3268 ccorr0: ccorr@1c004000 { 3269 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 3270 reg = <0 0x1c004000 0 0x1000>; 3271 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 3272 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3273 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; 3274 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; 3275 3276 ports { 3277 #address-cells = <1>; 3278 #size-cells = <0>; 3279 3280 port@0 { 3281 reg = <0>; 3282 ccorr0_in: endpoint { 3283 remote-endpoint = <&color0_out>; 3284 }; 3285 }; 3286 3287 port@1 { 3288 reg = <1>; 3289 ccorr0_out: endpoint { 3290 remote-endpoint = <&aal0_in>; 3291 }; 3292 }; 3293 }; 3294 }; 3295 3296 aal0: aal@1c005000 { 3297 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal"; 3298 reg = <0 0x1c005000 0 0x1000>; 3299 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 3300 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3301 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; 3302 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; 3303 3304 ports { 3305 #address-cells = <1>; 3306 #size-cells = <0>; 3307 3308 port@0 { 3309 reg = <0>; 3310 aal0_in: endpoint { 3311 remote-endpoint = <&ccorr0_out>; 3312 }; 3313 }; 3314 3315 port@1 { 3316 reg = <1>; 3317 aal0_out: endpoint { 3318 remote-endpoint = <&gamma0_in>; 3319 }; 3320 }; 3321 }; 3322 }; 3323 3324 gamma0: gamma@1c006000 { 3325 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma"; 3326 reg = <0 0x1c006000 0 0x1000>; 3327 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 3328 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3329 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; 3330 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; 3331 3332 ports { 3333 #address-cells = <1>; 3334 #size-cells = <0>; 3335 3336 port@0 { 3337 reg = <0>; 3338 gamma0_in: endpoint { 3339 remote-endpoint = <&aal0_out>; 3340 }; 3341 }; 3342 3343 port@1 { 3344 reg = <1>; 3345 gamma0_out: endpoint { 3346 remote-endpoint = <&dither0_in>; 3347 }; 3348 }; 3349 }; 3350 }; 3351 3352 dither0: dither@1c007000 { 3353 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither"; 3354 reg = <0 0x1c007000 0 0x1000>; 3355 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 3356 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3357 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; 3358 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; 3359 3360 ports { 3361 #address-cells = <1>; 3362 #size-cells = <0>; 3363 3364 port@0 { 3365 reg = <0>; 3366 dither0_in: endpoint { 3367 remote-endpoint = <&gamma0_out>; 3368 }; 3369 }; 3370 3371 port@1 { 3372 reg = <1>; 3373 dither0_out: endpoint { }; 3374 }; 3375 }; 3376 }; 3377 3378 dsi0: dsi@1c008000 { 3379 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi"; 3380 reg = <0 0x1c008000 0 0x1000>; 3381 interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; 3382 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3383 clocks = <&vdosys0 CLK_VDO0_DSI0>, 3384 <&vdosys0 CLK_VDO0_DSI0_DSI>, 3385 <&mipi_tx0>; 3386 clock-names = "engine", "digital", "hs"; 3387 phys = <&mipi_tx0>; 3388 phy-names = "dphy"; 3389 status = "disabled"; 3390 }; 3391 3392 dsc0: dsc@1c009000 { 3393 compatible = "mediatek,mt8195-disp-dsc"; 3394 reg = <0 0x1c009000 0 0x1000>; 3395 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; 3396 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3397 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; 3398 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; 3399 }; 3400 3401 dsi1: dsi@1c012000 { 3402 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi"; 3403 reg = <0 0x1c012000 0 0x1000>; 3404 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 3405 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3406 clocks = <&vdosys0 CLK_VDO0_DSI1>, 3407 <&vdosys0 CLK_VDO0_DSI1_DSI>, 3408 <&mipi_tx1>; 3409 clock-names = "engine", "digital", "hs"; 3410 phys = <&mipi_tx1>; 3411 phy-names = "dphy"; 3412 status = "disabled"; 3413 }; 3414 3415 merge0: merge@1c014000 { 3416 compatible = "mediatek,mt8195-disp-merge"; 3417 reg = <0 0x1c014000 0 0x1000>; 3418 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 3419 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3420 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; 3421 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; 3422 }; 3423 3424 dp_intf0: dp-intf@1c015000 { 3425 compatible = "mediatek,mt8195-dp-intf"; 3426 reg = <0 0x1c015000 0 0x1000>; 3427 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; 3428 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3429 clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, 3430 <&vdosys0 CLK_VDO0_DP_INTF0>, 3431 <&apmixedsys CLK_APMIXED_TVDPLL1>; 3432 clock-names = "pixel", "engine", "pll"; 3433 status = "disabled"; 3434 }; 3435 3436 mutex: mutex@1c016000 { 3437 compatible = "mediatek,mt8195-disp-mutex"; 3438 reg = <0 0x1c016000 0 0x1000>; 3439 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; 3440 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3441 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; 3442 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>; 3443 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; 3444 }; 3445 3446 larb0: larb@1c018000 { 3447 compatible = "mediatek,mt8195-smi-larb"; 3448 reg = <0 0x1c018000 0 0x1000>; 3449 mediatek,larb-id = <0>; 3450 mediatek,smi = <&smi_common_vdo>; 3451 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 3452 <&vdosys0 CLK_VDO0_SMI_LARB>, 3453 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>; 3454 clock-names = "apb", "smi", "gals"; 3455 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3456 }; 3457 3458 larb1: larb@1c019000 { 3459 compatible = "mediatek,mt8195-smi-larb"; 3460 reg = <0 0x1c019000 0 0x1000>; 3461 mediatek,larb-id = <1>; 3462 mediatek,smi = <&smi_common_vpp>; 3463 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 3464 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>, 3465 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>; 3466 clock-names = "apb", "smi", "gals"; 3467 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3468 }; 3469 3470 vdosys1: syscon@1c100000 { 3471 compatible = "mediatek,mt8195-vdosys1", "syscon"; 3472 reg = <0 0x1c100000 0 0x1000>; 3473 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; 3474 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>; 3475 #clock-cells = <1>; 3476 #reset-cells = <1>; 3477 }; 3478 3479 smi_common_vdo: smi@1c01b000 { 3480 compatible = "mediatek,mt8195-smi-common-vdo"; 3481 reg = <0 0x1c01b000 0 0x1000>; 3482 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, 3483 <&vdosys0 CLK_VDO0_SMI_EMI>, 3484 <&vdosys0 CLK_VDO0_SMI_RSI>, 3485 <&vdosys0 CLK_VDO0_SMI_GALS>; 3486 clock-names = "apb", "smi", "gals0", "gals1"; 3487 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3488 3489 }; 3490 3491 iommu_vdo: iommu@1c01f000 { 3492 compatible = "mediatek,mt8195-iommu-vdo"; 3493 reg = <0 0x1c01f000 0 0x1000>; 3494 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9 3495 &larb10 &larb11 &larb13 &larb17 3496 &larb19 &larb21 &larb24 &larb25 3497 &larb28>; 3498 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>; 3499 #iommu-cells = <1>; 3500 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; 3501 clock-names = "bclk"; 3502 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3503 }; 3504 3505 mutex1: mutex@1c101000 { 3506 compatible = "mediatek,mt8195-disp-mutex"; 3507 reg = <0 0x1c101000 0 0x1000>; 3508 interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>; 3509 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3510 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; 3511 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>; 3512 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>; 3513 }; 3514 3515 larb2: larb@1c102000 { 3516 compatible = "mediatek,mt8195-smi-larb"; 3517 reg = <0 0x1c102000 0 0x1000>; 3518 mediatek,larb-id = <2>; 3519 mediatek,smi = <&smi_common_vdo>; 3520 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, 3521 <&vdosys1 CLK_VDO1_SMI_LARB2>, 3522 <&vdosys1 CLK_VDO1_GALS>; 3523 clock-names = "apb", "smi", "gals"; 3524 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3525 }; 3526 3527 larb3: larb@1c103000 { 3528 compatible = "mediatek,mt8195-smi-larb"; 3529 reg = <0 0x1c103000 0 0x1000>; 3530 mediatek,larb-id = <3>; 3531 mediatek,smi = <&smi_common_vpp>; 3532 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, 3533 <&vdosys1 CLK_VDO1_GALS>, 3534 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 3535 clock-names = "apb", "smi", "gals"; 3536 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3537 }; 3538 3539 vdo1_rdma0: dma-controller@1c104000 { 3540 compatible = "mediatek,mt8195-vdo1-rdma"; 3541 reg = <0 0x1c104000 0 0x1000>; 3542 interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; 3543 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; 3544 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3545 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; 3546 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; 3547 #dma-cells = <1>; 3548 }; 3549 3550 vdo1_rdma1: dma-controller@1c105000 { 3551 compatible = "mediatek,mt8195-vdo1-rdma"; 3552 reg = <0 0x1c105000 0 0x1000>; 3553 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>; 3554 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>; 3555 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3556 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>; 3557 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; 3558 #dma-cells = <1>; 3559 }; 3560 3561 vdo1_rdma2: dma-controller@1c106000 { 3562 compatible = "mediatek,mt8195-vdo1-rdma"; 3563 reg = <0 0x1c106000 0 0x1000>; 3564 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>; 3565 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>; 3566 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3567 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>; 3568 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; 3569 #dma-cells = <1>; 3570 }; 3571 3572 vdo1_rdma3: dma-controller@1c107000 { 3573 compatible = "mediatek,mt8195-vdo1-rdma"; 3574 reg = <0 0x1c107000 0 0x1000>; 3575 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>; 3576 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>; 3577 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3578 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>; 3579 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; 3580 #dma-cells = <1>; 3581 }; 3582 3583 vdo1_rdma4: dma-controller@1c108000 { 3584 compatible = "mediatek,mt8195-vdo1-rdma"; 3585 reg = <0 0x1c108000 0 0x1000>; 3586 interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>; 3587 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>; 3588 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3589 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>; 3590 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; 3591 #dma-cells = <1>; 3592 }; 3593 3594 vdo1_rdma5: dma-controller@1c109000 { 3595 compatible = "mediatek,mt8195-vdo1-rdma"; 3596 reg = <0 0x1c109000 0 0x1000>; 3597 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>; 3598 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>; 3599 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3600 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>; 3601 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; 3602 #dma-cells = <1>; 3603 }; 3604 3605 vdo1_rdma6: dma-controller@1c10a000 { 3606 compatible = "mediatek,mt8195-vdo1-rdma"; 3607 reg = <0 0x1c10a000 0 0x1000>; 3608 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>; 3609 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>; 3610 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3611 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>; 3612 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; 3613 #dma-cells = <1>; 3614 }; 3615 3616 vdo1_rdma7: dma-controller@1c10b000 { 3617 compatible = "mediatek,mt8195-vdo1-rdma"; 3618 reg = <0 0x1c10b000 0 0x1000>; 3619 interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>; 3620 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>; 3621 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3622 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>; 3623 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; 3624 #dma-cells = <1>; 3625 }; 3626 3627 merge1: vpp-merge@1c10c000 { 3628 compatible = "mediatek,mt8195-disp-merge"; 3629 reg = <0 0x1c10c000 0 0x1000>; 3630 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; 3631 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, 3632 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; 3633 clock-names = "merge","merge_async"; 3634 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3635 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; 3636 mediatek,merge-mute; 3637 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>; 3638 }; 3639 3640 merge2: vpp-merge@1c10d000 { 3641 compatible = "mediatek,mt8195-disp-merge"; 3642 reg = <0 0x1c10d000 0 0x1000>; 3643 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>; 3644 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>, 3645 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; 3646 clock-names = "merge","merge_async"; 3647 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3648 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; 3649 mediatek,merge-mute; 3650 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>; 3651 }; 3652 3653 merge3: vpp-merge@1c10e000 { 3654 compatible = "mediatek,mt8195-disp-merge"; 3655 reg = <0 0x1c10e000 0 0x1000>; 3656 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>; 3657 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>, 3658 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; 3659 clock-names = "merge","merge_async"; 3660 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3661 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; 3662 mediatek,merge-mute; 3663 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>; 3664 }; 3665 3666 merge4: vpp-merge@1c10f000 { 3667 compatible = "mediatek,mt8195-disp-merge"; 3668 reg = <0 0x1c10f000 0 0x1000>; 3669 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; 3670 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>, 3671 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; 3672 clock-names = "merge","merge_async"; 3673 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3674 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; 3675 mediatek,merge-mute; 3676 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>; 3677 }; 3678 3679 merge5: vpp-merge@1c110000 { 3680 compatible = "mediatek,mt8195-disp-merge"; 3681 reg = <0 0x1c110000 0 0x1000>; 3682 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; 3683 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, 3684 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; 3685 clock-names = "merge","merge_async"; 3686 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3687 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; 3688 mediatek,merge-fifo-en; 3689 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; 3690 }; 3691 3692 dpi1: dpi@1c112000 { 3693 compatible = "mediatek,mt8195-dpi"; 3694 reg = <0 0x1c112000 0 0x1000>; 3695 clocks = <&vdosys1 CLK_VDO1_DPI1>, 3696 <&vdosys1 CLK_VDO1_DPI1_MM>, 3697 <&vdosys1 CLK_VDO1_DPI1_HDMI>; 3698 clock-names = "pixel", "engine", "pll"; 3699 interrupts = <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH 0>; 3700 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3701 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_DPI1>; 3702 status = "disabled"; 3703 3704 ports { 3705 #address-cells = <1>; 3706 #size-cells = <0>; 3707 3708 port@0 { 3709 reg = <0>; 3710 dpi1_in: endpoint { }; 3711 }; 3712 3713 port@1 { 3714 reg = <1>; 3715 dpi1_out: endpoint { }; 3716 }; 3717 }; 3718 }; 3719 3720 dp_intf1: dp-intf@1c113000 { 3721 compatible = "mediatek,mt8195-dp-intf"; 3722 reg = <0 0x1c113000 0 0x1000>; 3723 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; 3724 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3725 clocks = <&vdosys1 CLK_VDO1_DPINTF>, 3726 <&vdosys1 CLK_VDO1_DP_INTF0_MM>, 3727 <&apmixedsys CLK_APMIXED_TVDPLL2>; 3728 clock-names = "pixel", "engine", "pll"; 3729 status = "disabled"; 3730 }; 3731 3732 ethdr0: hdr-engine@1c114000 { 3733 compatible = "mediatek,mt8195-disp-ethdr"; 3734 reg = <0 0x1c114000 0 0x1000>, 3735 <0 0x1c115000 0 0x1000>, 3736 <0 0x1c117000 0 0x1000>, 3737 <0 0x1c119000 0 0x1000>, 3738 <0 0x1c11a000 0 0x1000>, 3739 <0 0x1c11b000 0 0x1000>, 3740 <0 0x1c11c000 0 0x1000>; 3741 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3742 "vdo_be", "adl_ds"; 3743 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, 3744 <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, 3745 <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, 3746 <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, 3747 <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, 3748 <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, 3749 <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; 3750 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, 3751 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, 3752 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, 3753 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, 3754 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, 3755 <&vdosys1 CLK_VDO1_HDR_VDO_BE>, 3756 <&vdosys1 CLK_VDO1_26M_SLOW>, 3757 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, 3758 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, 3759 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, 3760 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, 3761 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, 3762 <&topckgen CLK_TOP_ETHDR>; 3763 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3764 "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", 3765 "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", 3766 "ethdr_top"; 3767 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3768 iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, 3769 <&iommu_vpp M4U_PORT_L3_HDR_ADL>; 3770 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */ 3771 resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, 3772 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, 3773 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, 3774 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, 3775 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; 3776 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async", 3777 "gfx_fe1_async", "vdo_be_async"; 3778 }; 3779 3780 hdmi: hdmi-tx@1c300000 { 3781 compatible = "mediatek,mt8195-hdmi-tx"; 3782 #sound-dai-cells = <1>; 3783 reg = <0 0x1c300000 0 0x1000>; 3784 clocks = <&topckgen CLK_TOP_HDMI_APB>, 3785 <&topckgen CLK_TOP_HDCP>, 3786 <&topckgen CLK_TOP_HDCP_24M>, 3787 <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; 3788 clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split"; 3789 assigned-clocks = <&topckgen CLK_TOP_HDCP>; 3790 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4_D8>; 3791 interrupts = <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>; 3792 power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>; 3793 phys = <&hdmi_phy>; 3794 phy-names = "hdmi"; 3795 status = "disabled"; 3796 3797 hdmitx_ddc: i2c { 3798 compatible = "mediatek,mt8195-hdmi-ddc"; 3799 clocks = <&clk26m>; 3800 }; 3801 3802 ports { 3803 #address-cells = <1>; 3804 #size-cells = <0>; 3805 3806 port@0 { 3807 reg = <0>; 3808 hdmi0_in: endpoint { }; 3809 }; 3810 3811 port@1 { 3812 reg = <1>; 3813 hdmi0_out: endpoint { }; 3814 }; 3815 }; 3816 }; 3817 3818 edp_tx: edp-tx@1c500000 { 3819 compatible = "mediatek,mt8195-edp-tx"; 3820 reg = <0 0x1c500000 0 0x8000>; 3821 nvmem-cells = <&dp_calibration>; 3822 nvmem-cell-names = "dp_calibration_data"; 3823 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; 3824 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; 3825 max-linkrate-mhz = <8100>; 3826 status = "disabled"; 3827 }; 3828 3829 dp_tx: dp-tx@1c600000 { 3830 compatible = "mediatek,mt8195-dp-tx"; 3831 reg = <0 0x1c600000 0 0x8000>; 3832 nvmem-cells = <&dp_calibration>; 3833 nvmem-cell-names = "dp_calibration_data"; 3834 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; 3835 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; 3836 max-linkrate-mhz = <8100>; 3837 status = "disabled"; 3838 }; 3839 }; 3840 3841 thermal_zones: thermal-zones { 3842 cpu0-thermal { 3843 polling-delay = <1000>; 3844 polling-delay-passive = <250>; 3845 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>; 3846 3847 trips { 3848 cpu0_alert: trip-alert { 3849 temperature = <85000>; 3850 hysteresis = <2000>; 3851 type = "passive"; 3852 }; 3853 3854 cpu0_crit: trip-crit { 3855 temperature = <100000>; 3856 hysteresis = <2000>; 3857 type = "critical"; 3858 }; 3859 }; 3860 3861 cooling-maps { 3862 map0 { 3863 trip = <&cpu0_alert>; 3864 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3865 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3866 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3867 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3868 }; 3869 }; 3870 }; 3871 3872 cpu1-thermal { 3873 polling-delay = <1000>; 3874 polling-delay-passive = <250>; 3875 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>; 3876 3877 trips { 3878 cpu1_alert: trip-alert { 3879 temperature = <85000>; 3880 hysteresis = <2000>; 3881 type = "passive"; 3882 }; 3883 3884 cpu1_crit: trip-crit { 3885 temperature = <100000>; 3886 hysteresis = <2000>; 3887 type = "critical"; 3888 }; 3889 }; 3890 3891 cooling-maps { 3892 map0 { 3893 trip = <&cpu1_alert>; 3894 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3895 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3896 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3897 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3898 }; 3899 }; 3900 }; 3901 3902 cpu2-thermal { 3903 polling-delay = <1000>; 3904 polling-delay-passive = <250>; 3905 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>; 3906 3907 trips { 3908 cpu2_alert: trip-alert { 3909 temperature = <85000>; 3910 hysteresis = <2000>; 3911 type = "passive"; 3912 }; 3913 3914 cpu2_crit: trip-crit { 3915 temperature = <100000>; 3916 hysteresis = <2000>; 3917 type = "critical"; 3918 }; 3919 }; 3920 3921 cooling-maps { 3922 map0 { 3923 trip = <&cpu2_alert>; 3924 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3925 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3926 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3927 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3928 }; 3929 }; 3930 }; 3931 3932 cpu3-thermal { 3933 polling-delay = <1000>; 3934 polling-delay-passive = <250>; 3935 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>; 3936 3937 trips { 3938 cpu3_alert: trip-alert { 3939 temperature = <85000>; 3940 hysteresis = <2000>; 3941 type = "passive"; 3942 }; 3943 3944 cpu3_crit: trip-crit { 3945 temperature = <100000>; 3946 hysteresis = <2000>; 3947 type = "critical"; 3948 }; 3949 }; 3950 3951 cooling-maps { 3952 map0 { 3953 trip = <&cpu3_alert>; 3954 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3955 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3956 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3957 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3958 }; 3959 }; 3960 }; 3961 3962 cpu4-thermal { 3963 polling-delay = <1000>; 3964 polling-delay-passive = <250>; 3965 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>; 3966 3967 trips { 3968 cpu4_alert: trip-alert { 3969 temperature = <85000>; 3970 hysteresis = <2000>; 3971 type = "passive"; 3972 }; 3973 3974 cpu4_crit: trip-crit { 3975 temperature = <100000>; 3976 hysteresis = <2000>; 3977 type = "critical"; 3978 }; 3979 }; 3980 3981 cooling-maps { 3982 map0 { 3983 trip = <&cpu4_alert>; 3984 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3985 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3986 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3987 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3988 }; 3989 }; 3990 }; 3991 3992 cpu5-thermal { 3993 polling-delay = <1000>; 3994 polling-delay-passive = <250>; 3995 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>; 3996 3997 trips { 3998 cpu5_alert: trip-alert { 3999 temperature = <85000>; 4000 hysteresis = <2000>; 4001 type = "passive"; 4002 }; 4003 4004 cpu5_crit: trip-crit { 4005 temperature = <100000>; 4006 hysteresis = <2000>; 4007 type = "critical"; 4008 }; 4009 }; 4010 4011 cooling-maps { 4012 map0 { 4013 trip = <&cpu5_alert>; 4014 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4015 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4016 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4017 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4018 }; 4019 }; 4020 }; 4021 4022 cpu6-thermal { 4023 polling-delay = <1000>; 4024 polling-delay-passive = <250>; 4025 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>; 4026 4027 trips { 4028 cpu6_alert: trip-alert { 4029 temperature = <85000>; 4030 hysteresis = <2000>; 4031 type = "passive"; 4032 }; 4033 4034 cpu6_crit: trip-crit { 4035 temperature = <100000>; 4036 hysteresis = <2000>; 4037 type = "critical"; 4038 }; 4039 }; 4040 4041 cooling-maps { 4042 map0 { 4043 trip = <&cpu6_alert>; 4044 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4045 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4046 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4047 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4048 }; 4049 }; 4050 }; 4051 4052 cpu7-thermal { 4053 polling-delay = <1000>; 4054 polling-delay-passive = <250>; 4055 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>; 4056 4057 trips { 4058 cpu7_alert: trip-alert { 4059 temperature = <85000>; 4060 hysteresis = <2000>; 4061 type = "passive"; 4062 }; 4063 4064 cpu7_crit: trip-crit { 4065 temperature = <100000>; 4066 hysteresis = <2000>; 4067 type = "critical"; 4068 }; 4069 }; 4070 4071 cooling-maps { 4072 map0 { 4073 trip = <&cpu7_alert>; 4074 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4075 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4076 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4077 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4078 }; 4079 }; 4080 }; 4081 4082 vpu0-thermal { 4083 polling-delay = <1000>; 4084 polling-delay-passive = <250>; 4085 thermal-sensors = <&lvts_ap MT8195_AP_VPU0>; 4086 4087 trips { 4088 vpu0_alert: trip-alert { 4089 temperature = <85000>; 4090 hysteresis = <2000>; 4091 type = "passive"; 4092 }; 4093 4094 vpu0_crit: trip-crit { 4095 temperature = <100000>; 4096 hysteresis = <2000>; 4097 type = "critical"; 4098 }; 4099 }; 4100 }; 4101 4102 vpu1-thermal { 4103 polling-delay = <1000>; 4104 polling-delay-passive = <250>; 4105 thermal-sensors = <&lvts_ap MT8195_AP_VPU1>; 4106 4107 trips { 4108 vpu1_alert: trip-alert { 4109 temperature = <85000>; 4110 hysteresis = <2000>; 4111 type = "passive"; 4112 }; 4113 4114 vpu1_crit: trip-crit { 4115 temperature = <100000>; 4116 hysteresis = <2000>; 4117 type = "critical"; 4118 }; 4119 }; 4120 }; 4121 4122 gpu-thermal { 4123 polling-delay = <1000>; 4124 polling-delay-passive = <250>; 4125 thermal-sensors = <&lvts_ap MT8195_AP_GPU0>; 4126 4127 trips { 4128 gpu0_alert: trip-alert { 4129 temperature = <85000>; 4130 hysteresis = <2000>; 4131 type = "passive"; 4132 }; 4133 4134 gpu0_crit: trip-crit { 4135 temperature = <100000>; 4136 hysteresis = <2000>; 4137 type = "critical"; 4138 }; 4139 }; 4140 }; 4141 4142 gpu1-thermal { 4143 polling-delay = <1000>; 4144 polling-delay-passive = <250>; 4145 thermal-sensors = <&lvts_ap MT8195_AP_GPU1>; 4146 4147 trips { 4148 gpu1_alert: trip-alert { 4149 temperature = <85000>; 4150 hysteresis = <2000>; 4151 type = "passive"; 4152 }; 4153 4154 gpu1_crit: trip-crit { 4155 temperature = <100000>; 4156 hysteresis = <2000>; 4157 type = "critical"; 4158 }; 4159 }; 4160 }; 4161 4162 vdec-thermal { 4163 polling-delay = <1000>; 4164 polling-delay-passive = <250>; 4165 thermal-sensors = <&lvts_ap MT8195_AP_VDEC>; 4166 4167 trips { 4168 vdec_alert: trip-alert { 4169 temperature = <85000>; 4170 hysteresis = <2000>; 4171 type = "passive"; 4172 }; 4173 4174 vdec_crit: trip-crit { 4175 temperature = <100000>; 4176 hysteresis = <2000>; 4177 type = "critical"; 4178 }; 4179 }; 4180 }; 4181 4182 img-thermal { 4183 polling-delay = <1000>; 4184 polling-delay-passive = <250>; 4185 thermal-sensors = <&lvts_ap MT8195_AP_IMG>; 4186 4187 trips { 4188 img_alert: trip-alert { 4189 temperature = <85000>; 4190 hysteresis = <2000>; 4191 type = "passive"; 4192 }; 4193 4194 img_crit: trip-crit { 4195 temperature = <100000>; 4196 hysteresis = <2000>; 4197 type = "critical"; 4198 }; 4199 }; 4200 }; 4201 4202 infra-thermal { 4203 polling-delay = <1000>; 4204 polling-delay-passive = <250>; 4205 thermal-sensors = <&lvts_ap MT8195_AP_INFRA>; 4206 4207 trips { 4208 infra_alert: trip-alert { 4209 temperature = <85000>; 4210 hysteresis = <2000>; 4211 type = "passive"; 4212 }; 4213 4214 infra_crit: trip-crit { 4215 temperature = <100000>; 4216 hysteresis = <2000>; 4217 type = "critical"; 4218 }; 4219 }; 4220 }; 4221 4222 cam0-thermal { 4223 polling-delay = <1000>; 4224 polling-delay-passive = <250>; 4225 thermal-sensors = <&lvts_ap MT8195_AP_CAM0>; 4226 4227 trips { 4228 cam0_alert: trip-alert { 4229 temperature = <85000>; 4230 hysteresis = <2000>; 4231 type = "passive"; 4232 }; 4233 4234 cam0_crit: trip-crit { 4235 temperature = <100000>; 4236 hysteresis = <2000>; 4237 type = "critical"; 4238 }; 4239 }; 4240 }; 4241 4242 cam1-thermal { 4243 polling-delay = <1000>; 4244 polling-delay-passive = <250>; 4245 thermal-sensors = <&lvts_ap MT8195_AP_CAM1>; 4246 4247 trips { 4248 cam1_alert: trip-alert { 4249 temperature = <85000>; 4250 hysteresis = <2000>; 4251 type = "passive"; 4252 }; 4253 4254 cam1_crit: trip-crit { 4255 temperature = <100000>; 4256 hysteresis = <2000>; 4257 type = "critical"; 4258 }; 4259 }; 4260 }; 4261 }; 4262}; 4263