1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,qcs8300-gcc.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/clock/qcom,sa8775p-camcc.h> 9#include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 10#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 11#include <dt-bindings/clock/qcom,sa8775p-videocc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/firmware/qcom,scm.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/soc/qcom,gpr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 clocks { 31 xo_board_clk: xo-board-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <38400000>; 35 }; 36 37 sleep_clk: sleep-clk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <32000>; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a78c"; 51 reg = <0x0 0x0>; 52 enable-method = "psci"; 53 next-level-cache = <&l2_0>; 54 power-domains = <&cpu_pd0>; 55 power-domain-names = "psci"; 56 capacity-dmips-mhz = <1946>; 57 dynamic-power-coefficient = <472>; 58 #cooling-cells = <2>; 59 qcom,freq-domain = <&cpufreq_hw 0>; 60 operating-points-v2 = <&cpu0_opp_table>; 61 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 62 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 63 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 64 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 65 66 l2_0: l2-cache { 67 compatible = "cache"; 68 cache-level = <2>; 69 cache-unified; 70 next-level-cache = <&l3_0>; 71 }; 72 }; 73 74 cpu1: cpu@100 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a78c"; 77 reg = <0x0 0x100>; 78 enable-method = "psci"; 79 next-level-cache = <&l2_1>; 80 power-domains = <&cpu_pd1>; 81 power-domain-names = "psci"; 82 capacity-dmips-mhz = <1946>; 83 #cooling-cells = <2>; 84 dynamic-power-coefficient = <472>; 85 qcom,freq-domain = <&cpufreq_hw 0>; 86 operating-points-v2 = <&cpu0_opp_table>; 87 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 88 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 89 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 90 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 91 92 l2_1: l2-cache { 93 compatible = "cache"; 94 cache-level = <2>; 95 cache-unified; 96 next-level-cache = <&l3_0>; 97 }; 98 }; 99 100 cpu2: cpu@200 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a78c"; 103 reg = <0x0 0x200>; 104 enable-method = "psci"; 105 next-level-cache = <&l2_2>; 106 power-domains = <&cpu_pd2>; 107 power-domain-names = "psci"; 108 capacity-dmips-mhz = <1946>; 109 #cooling-cells = <2>; 110 dynamic-power-coefficient = <507>; 111 qcom,freq-domain = <&cpufreq_hw 2>; 112 operating-points-v2 = <&cpu2_opp_table>; 113 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 114 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 115 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 116 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 117 118 l2_2: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 cache-unified; 122 next-level-cache = <&l3_0>; 123 }; 124 }; 125 126 cpu3: cpu@300 { 127 device_type = "cpu"; 128 compatible = "arm,cortex-a78c"; 129 reg = <0x0 0x300>; 130 enable-method = "psci"; 131 next-level-cache = <&l2_3>; 132 power-domains = <&cpu_pd3>; 133 power-domain-names = "psci"; 134 capacity-dmips-mhz = <1946>; 135 #cooling-cells = <2>; 136 dynamic-power-coefficient = <507>; 137 qcom,freq-domain = <&cpufreq_hw 2>; 138 operating-points-v2 = <&cpu2_opp_table>; 139 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 140 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 141 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 142 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 143 144 l2_3: l2-cache { 145 compatible = "cache"; 146 cache-level = <2>; 147 cache-unified; 148 next-level-cache = <&l3_0>; 149 }; 150 }; 151 152 cpu4: cpu@10000 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a55"; 155 reg = <0x0 0x10000>; 156 enable-method = "psci"; 157 next-level-cache = <&l2_4>; 158 power-domains = <&cpu_pd4>; 159 power-domain-names = "psci"; 160 capacity-dmips-mhz = <1024>; 161 #cooling-cells = <2>; 162 dynamic-power-coefficient = <100>; 163 qcom,freq-domain = <&cpufreq_hw 1>; 164 operating-points-v2 = <&cpu4_opp_table>; 165 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 166 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 167 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 168 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 169 170 l2_4: l2-cache { 171 compatible = "cache"; 172 cache-level = <2>; 173 cache-unified; 174 next-level-cache = <&l3_1>; 175 }; 176 }; 177 178 cpu5: cpu@10100 { 179 device_type = "cpu"; 180 compatible = "arm,cortex-a55"; 181 reg = <0x0 0x10100>; 182 enable-method = "psci"; 183 next-level-cache = <&l2_5>; 184 power-domains = <&cpu_pd5>; 185 power-domain-names = "psci"; 186 capacity-dmips-mhz = <1024>; 187 #cooling-cells = <2>; 188 dynamic-power-coefficient = <100>; 189 qcom,freq-domain = <&cpufreq_hw 1>; 190 operating-points-v2 = <&cpu4_opp_table>; 191 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 192 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 193 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 194 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 195 196 l2_5: l2-cache { 197 compatible = "cache"; 198 cache-level = <2>; 199 cache-unified; 200 next-level-cache = <&l3_1>; 201 }; 202 }; 203 204 cpu6: cpu@10200 { 205 device_type = "cpu"; 206 compatible = "arm,cortex-a55"; 207 reg = <0x0 0x10200>; 208 enable-method = "psci"; 209 next-level-cache = <&l2_6>; 210 power-domains = <&cpu_pd6>; 211 power-domain-names = "psci"; 212 capacity-dmips-mhz = <1024>; 213 #cooling-cells = <2>; 214 dynamic-power-coefficient = <100>; 215 qcom,freq-domain = <&cpufreq_hw 1>; 216 operating-points-v2 = <&cpu4_opp_table>; 217 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 218 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 219 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 220 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 221 222 l2_6: l2-cache { 223 compatible = "cache"; 224 cache-level = <2>; 225 cache-unified; 226 next-level-cache = <&l3_1>; 227 }; 228 }; 229 230 cpu7: cpu@10300 { 231 device_type = "cpu"; 232 compatible = "arm,cortex-a55"; 233 reg = <0x0 0x10300>; 234 enable-method = "psci"; 235 next-level-cache = <&l2_7>; 236 power-domains = <&cpu_pd7>; 237 power-domain-names = "psci"; 238 capacity-dmips-mhz = <1024>; 239 #cooling-cells = <2>; 240 dynamic-power-coefficient = <100>; 241 qcom,freq-domain = <&cpufreq_hw 1>; 242 operating-points-v2 = <&cpu4_opp_table>; 243 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 244 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 245 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 246 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 247 248 l2_7: l2-cache { 249 compatible = "cache"; 250 cache-level = <2>; 251 cache-unified; 252 next-level-cache = <&l3_1>; 253 }; 254 }; 255 256 cpu-map { 257 cluster0 { 258 core0 { 259 cpu = <&cpu0>; 260 }; 261 262 core1 { 263 cpu = <&cpu1>; 264 }; 265 266 core2 { 267 cpu = <&cpu2>; 268 }; 269 270 core3 { 271 cpu = <&cpu3>; 272 }; 273 }; 274 275 cluster1 { 276 core0 { 277 cpu = <&cpu4>; 278 }; 279 280 core1 { 281 cpu = <&cpu5>; 282 }; 283 284 core2 { 285 cpu = <&cpu6>; 286 }; 287 288 core3 { 289 cpu = <&cpu7>; 290 }; 291 }; 292 }; 293 294 l3_0: l3-cache-0 { 295 compatible = "cache"; 296 cache-level = <3>; 297 cache-unified; 298 }; 299 300 l3_1: l3-cache-1 { 301 compatible = "cache"; 302 cache-level = <3>; 303 cache-unified; 304 }; 305 306 idle-states { 307 entry-method = "psci"; 308 309 little_cpu_sleep_0: cpu-sleep-0-0 { 310 compatible = "arm,idle-state"; 311 idle-state-name = "silver-power-collapse"; 312 arm,psci-suspend-param = <0x40000003>; 313 entry-latency-us = <449>; 314 exit-latency-us = <801>; 315 min-residency-us = <1574>; 316 local-timer-stop; 317 }; 318 319 little_cpu_sleep_1: cpu-sleep-0-1 { 320 compatible = "arm,idle-state"; 321 idle-state-name = "silver-rail-power-collapse"; 322 arm,psci-suspend-param = <0x40000004>; 323 entry-latency-us = <602>; 324 exit-latency-us = <961>; 325 min-residency-us = <4288>; 326 local-timer-stop; 327 }; 328 329 big_cpu_sleep_0: cpu-sleep-1-0 { 330 compatible = "arm,idle-state"; 331 idle-state-name = "gold-power-collapse"; 332 arm,psci-suspend-param = <0x40000003>; 333 entry-latency-us = <549>; 334 exit-latency-us = <901>; 335 min-residency-us = <1774>; 336 local-timer-stop; 337 }; 338 339 big_cpu_sleep_1: cpu-sleep-1-1 { 340 compatible = "arm,idle-state"; 341 idle-state-name = "gold-rail-power-collapse"; 342 arm,psci-suspend-param = <0x40000004>; 343 entry-latency-us = <702>; 344 exit-latency-us = <1061>; 345 min-residency-us = <4488>; 346 local-timer-stop; 347 }; 348 }; 349 350 domain-idle-states { 351 silver_cluster_sleep: cluster-sleep-0 { 352 compatible = "domain-idle-state"; 353 arm,psci-suspend-param = <0x41000044>; 354 entry-latency-us = <2552>; 355 exit-latency-us = <2848>; 356 min-residency-us = <5908>; 357 }; 358 359 gold_cluster_sleep: cluster-sleep-1 { 360 compatible = "domain-idle-state"; 361 arm,psci-suspend-param = <0x41000044>; 362 entry-latency-us = <2752>; 363 exit-latency-us = <3048>; 364 min-residency-us = <6118>; 365 }; 366 367 system_sleep: domain-sleep { 368 compatible = "domain-idle-state"; 369 arm,psci-suspend-param = <0x42000144>; 370 entry-latency-us = <3263>; 371 exit-latency-us = <6562>; 372 min-residency-us = <9987>; 373 }; 374 }; 375 }; 376 377 cpu0_opp_table: opp-table-cpu0 { 378 compatible = "operating-points-v2"; 379 opp-shared; 380 381 opp-902400000 { 382 opp-hz = /bits/ 64 <902400000>; 383 opp-peak-kBps = <(681600 * 4) (921600 * 32)>; 384 }; 385 386 opp-1017600000 { 387 opp-hz = /bits/ 64 <1017600000>; 388 opp-peak-kBps = <(1017600 * 4) (921600 * 32)>; 389 }; 390 391 opp-1190400000 { 392 opp-hz = /bits/ 64 <1190400000>; 393 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; 394 }; 395 396 opp-1267200000 { 397 opp-hz = /bits/ 64 <1267200000>; 398 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 399 }; 400 401 opp-1344000000 { 402 opp-hz = /bits/ 64 <1344000000>; 403 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; 404 }; 405 406 opp-1420800000 { 407 opp-hz = /bits/ 64 <1420800000>; 408 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; 409 }; 410 411 opp-1497600000 { 412 opp-hz = /bits/ 64 <1497600000>; 413 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; 414 }; 415 416 opp-1574400000 { 417 opp-hz = /bits/ 64 <1574400000>; 418 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 419 }; 420 421 opp-1670400000 { 422 opp-hz = /bits/ 64 <1670400000>; 423 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 424 }; 425 426 opp-1747200000 { 427 opp-hz = /bits/ 64 <1747200000>; 428 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 429 }; 430 431 opp-1824000000 { 432 opp-hz = /bits/ 64 <1824000000>; 433 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 434 }; 435 436 opp-1900800000 { 437 opp-hz = /bits/ 64 <1900800000>; 438 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 439 }; 440 441 opp-1977600000 { 442 opp-hz = /bits/ 64 <1977600000>; 443 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 444 }; 445 446 opp-2054400000 { 447 opp-hz = /bits/ 64 <2054400000>; 448 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 449 }; 450 451 opp-2112000000 { 452 opp-hz = /bits/ 64 <2112000000>; 453 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 454 }; 455 456 }; 457 458 cpu2_opp_table: opp-table-cpu2 { 459 compatible = "operating-points-v2"; 460 opp-shared; 461 462 opp-940800000 { 463 opp-hz = /bits/ 64 <940800000>; 464 opp-peak-kBps = <(681600 * 4) (921600 * 32)>; 465 }; 466 467 opp-1094400000 { 468 opp-hz = /bits/ 64 <1094400000>; 469 opp-peak-kBps = <(1017600 * 4) (921600 * 32)>; 470 }; 471 472 opp-1267200000 { 473 opp-hz = /bits/ 64 <1267200000>; 474 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; 475 }; 476 477 opp-1344000000 { 478 opp-hz = /bits/ 64 <1344000000>; 479 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 480 }; 481 482 opp-1420800000 { 483 opp-hz = /bits/ 64 <1420800000>; 484 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 485 }; 486 487 opp-1497600000 { 488 opp-hz = /bits/ 64 <1497600000>; 489 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; 490 }; 491 492 opp-1574400000 { 493 opp-hz = /bits/ 64 <1574400000>; 494 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; 495 }; 496 497 opp-1632000000 { 498 opp-hz = /bits/ 64 <1632000000>; 499 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; 500 }; 501 502 opp-1708800000 { 503 opp-hz = /bits/ 64 <1708800000>; 504 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 505 }; 506 507 opp-1804800000 { 508 opp-hz = /bits/ 64 <1804800000>; 509 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 510 }; 511 512 opp-1900800000 { 513 opp-hz = /bits/ 64 <1900800000>; 514 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 515 }; 516 517 opp-1977600000 { 518 opp-hz = /bits/ 64 <1977600000>; 519 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 520 }; 521 522 opp-2054400000 { 523 opp-hz = /bits/ 64 <2054400000>; 524 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 525 }; 526 527 opp-2131200000 { 528 opp-hz = /bits/ 64 <2131200000>; 529 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 530 }; 531 532 opp-2208000000 { 533 opp-hz = /bits/ 64 <2208000000>; 534 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 535 }; 536 537 opp-2284800000 { 538 opp-hz = /bits/ 64 <2284800000>; 539 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 540 }; 541 542 opp-2361600000 { 543 opp-hz = /bits/ 64 <2361600000>; 544 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 545 }; 546 547 }; 548 549 cpu4_opp_table: opp-table-cpu4 { 550 compatible = "operating-points-v2"; 551 opp-shared; 552 553 opp-844800000 { 554 opp-hz = /bits/ 64 <844800000>; 555 opp-peak-kBps = <(681600 * 4) (921600 * 32)>; 556 }; 557 558 opp-1113600000 { 559 opp-hz = /bits/ 64 <1113600000>; 560 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; 561 }; 562 563 opp-1209600000 { 564 opp-hz = /bits/ 64 <1209600000>; 565 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 566 }; 567 568 opp-1305600000 { 569 opp-hz = /bits/ 64 <1305600000>; 570 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; 571 }; 572 573 opp-1382400000 { 574 opp-hz = /bits/ 64 <1382400000>; 575 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; 576 }; 577 578 opp-1459200000 { 579 opp-hz = /bits/ 64 <1459200000>; 580 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; 581 }; 582 583 opp-1497600000 { 584 opp-hz = /bits/ 64 <1497600000>; 585 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 586 }; 587 588 opp-1574400000 { 589 opp-hz = /bits/ 64 <1574400000>; 590 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 591 }; 592 593 opp-1651200000 { 594 opp-hz = /bits/ 64 <1651200000>; 595 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 596 }; 597 598 opp-1728000000 { 599 opp-hz = /bits/ 64 <1728000000>; 600 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 601 }; 602 603 opp-1804800000 { 604 opp-hz = /bits/ 64 <1804800000>; 605 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 606 }; 607 608 opp-1881600000 { 609 opp-hz = /bits/ 64 <1881600000>; 610 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 611 }; 612 613 opp-1958400000 { 614 opp-hz = /bits/ 64 <1958400000>; 615 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 616 }; 617 }; 618 619 dummy_eud: dummy-sink { 620 compatible = "arm,coresight-dummy-sink"; 621 622 in-ports { 623 port { 624 eud_in: endpoint { 625 remote-endpoint = <&swao_rep_out1>; 626 }; 627 }; 628 }; 629 }; 630 631 firmware { 632 scm: scm { 633 compatible = "qcom,scm-qcs8300", "qcom,scm"; 634 qcom,dload-mode = <&tcsr 0x13000>; 635 }; 636 }; 637 638 memory@80000000 { 639 device_type = "memory"; 640 /* We expect the bootloader to fill in the size */ 641 reg = <0x0 0x80000000 0x0 0x0>; 642 }; 643 644 clk_virt: interconnect-0 { 645 compatible = "qcom,qcs8300-clk-virt"; 646 #interconnect-cells = <2>; 647 qcom,bcm-voters = <&apps_bcm_voter>; 648 }; 649 650 mc_virt: interconnect-1 { 651 compatible = "qcom,qcs8300-mc-virt"; 652 #interconnect-cells = <2>; 653 qcom,bcm-voters = <&apps_bcm_voter>; 654 }; 655 656 qup_opp_table: opp-table-qup { 657 compatible = "operating-points-v2"; 658 659 opp-120000000 { 660 opp-hz = /bits/ 64 <120000000>; 661 required-opps = <&rpmhpd_opp_svs_l1>; 662 }; 663 }; 664 665 pmu-a55 { 666 compatible = "arm,cortex-a55-pmu"; 667 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 668 }; 669 670 pmu-a78 { 671 compatible = "arm,cortex-a78-pmu"; 672 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 673 }; 674 675 psci { 676 compatible = "arm,psci-1.0"; 677 method = "smc"; 678 679 cpu_pd0: power-domain-cpu0 { 680 #power-domain-cells = <0>; 681 power-domains = <&cluster_pd0>; 682 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 683 }; 684 685 cpu_pd1: power-domain-cpu1 { 686 #power-domain-cells = <0>; 687 power-domains = <&cluster_pd0>; 688 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 689 }; 690 691 cpu_pd2: power-domain-cpu2 { 692 #power-domain-cells = <0>; 693 power-domains = <&cluster_pd0>; 694 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 695 }; 696 697 cpu_pd3: power-domain-cpu3 { 698 #power-domain-cells = <0>; 699 power-domains = <&cluster_pd0>; 700 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 701 }; 702 703 cpu_pd4: power-domain-cpu4 { 704 #power-domain-cells = <0>; 705 power-domains = <&cluster_pd1>; 706 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 707 }; 708 709 cpu_pd5: power-domain-cpu5 { 710 #power-domain-cells = <0>; 711 power-domains = <&cluster_pd1>; 712 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 713 }; 714 715 cpu_pd6: power-domain-cpu6 { 716 #power-domain-cells = <0>; 717 power-domains = <&cluster_pd1>; 718 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 719 }; 720 721 cpu_pd7: power-domain-cpu7 { 722 #power-domain-cells = <0>; 723 power-domains = <&cluster_pd1>; 724 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 725 }; 726 727 cluster_pd0: power-domain-cluster0 { 728 #power-domain-cells = <0>; 729 power-domains = <&system_pd>; 730 domain-idle-states = <&gold_cluster_sleep>; 731 }; 732 733 cluster_pd1: power-domain-cluster1 { 734 #power-domain-cells = <0>; 735 power-domains = <&system_pd>; 736 domain-idle-states = <&silver_cluster_sleep>; 737 }; 738 739 system_pd: power-domain-system { 740 #power-domain-cells = <0>; 741 domain-idle-states = <&system_sleep>; 742 }; 743 }; 744 745 reserved-memory { 746 #address-cells = <2>; 747 #size-cells = <2>; 748 ranges; 749 750 aop_image_mem: aop-image-region@90800000 { 751 reg = <0x0 0x90800000 0x0 0x60000>; 752 no-map; 753 }; 754 755 aop_cmd_db_mem: aop-cmd-db-region@90860000 { 756 compatible = "qcom,cmd-db"; 757 reg = <0x0 0x90860000 0x0 0x20000>; 758 no-map; 759 }; 760 761 smem_mem: smem@90900000 { 762 compatible = "qcom,smem"; 763 reg = <0x0 0x90900000 0x0 0x200000>; 764 no-map; 765 hwlocks = <&tcsr_mutex 3>; 766 }; 767 768 gunyah_md_mem: gunyah-md-region@91a80000 { 769 reg = <0x0 0x91a80000 0x0 0x80000>; 770 no-map; 771 }; 772 773 lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 { 774 reg = <0x0 0x93b00000 0x0 0xf00000>; 775 no-map; 776 }; 777 778 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap-region@94a00000 { 779 reg = <0x0 0x94a00000 0x0 0x800000>; 780 no-map; 781 }; 782 783 camera_mem: camera-region@95200000 { 784 reg = <0x0 0x95200000 0x0 0x500000>; 785 no-map; 786 }; 787 788 adsp_mem: adsp-region@95c00000 { 789 no-map; 790 reg = <0x0 0x95c00000 0x0 0x1e00000>; 791 }; 792 793 q6_adsp_dtb_mem: q6-adsp-dtb-region@97a00000 { 794 reg = <0x0 0x97a00000 0x0 0x80000>; 795 no-map; 796 }; 797 798 q6_gpdsp_dtb_mem: q6-gpdsp-dtb-region@97a80000 { 799 reg = <0x0 0x97a80000 0x0 0x80000>; 800 no-map; 801 }; 802 803 gpdsp_mem: gpdsp-region@97b00000 { 804 reg = <0x0 0x97b00000 0x0 0x1e00000>; 805 no-map; 806 }; 807 808 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@99900000 { 809 reg = <0x0 0x99900000 0x0 0x80000>; 810 no-map; 811 }; 812 813 cdsp_mem: cdsp-region@99980000 { 814 reg = <0x0 0x99980000 0x0 0x1e00000>; 815 no-map; 816 }; 817 818 gpu_microcode_mem: gpu-microcode-region@9b780000 { 819 reg = <0x0 0x9b780000 0x0 0x2000>; 820 no-map; 821 }; 822 823 cvp_mem: cvp-region@9b782000 { 824 reg = <0x0 0x9b782000 0x0 0x700000>; 825 no-map; 826 }; 827 828 video_mem: video-region@9be82000 { 829 reg = <0x0 0x9be82000 0x0 0x700000>; 830 no-map; 831 }; 832 }; 833 834 smp2p-adsp { 835 compatible = "qcom,smp2p"; 836 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 837 IPCC_MPROC_SIGNAL_SMP2P 838 IRQ_TYPE_EDGE_RISING>; 839 mboxes = <&ipcc IPCC_CLIENT_LPASS 840 IPCC_MPROC_SIGNAL_SMP2P>; 841 842 qcom,smem = <443>, <429>; 843 qcom,local-pid = <0>; 844 qcom,remote-pid = <2>; 845 846 smp2p_adsp_in: slave-kernel { 847 qcom,entry-name = "slave-kernel"; 848 interrupt-controller; 849 #interrupt-cells = <2>; 850 }; 851 852 smp2p_adsp_out: master-kernel { 853 qcom,entry-name = "master-kernel"; 854 #qcom,smem-state-cells = <1>; 855 }; 856 }; 857 858 smp2p-cdsp { 859 compatible = "qcom,smp2p"; 860 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 861 IPCC_MPROC_SIGNAL_SMP2P 862 IRQ_TYPE_EDGE_RISING>; 863 mboxes = <&ipcc IPCC_CLIENT_CDSP 864 IPCC_MPROC_SIGNAL_SMP2P>; 865 866 qcom,smem = <94>, <432>; 867 qcom,local-pid = <0>; 868 qcom,remote-pid = <5>; 869 870 smp2p_cdsp_in: slave-kernel { 871 qcom,entry-name = "slave-kernel"; 872 interrupt-controller; 873 #interrupt-cells = <2>; 874 }; 875 876 smp2p_cdsp_out: master-kernel { 877 qcom,entry-name = "master-kernel"; 878 #qcom,smem-state-cells = <1>; 879 }; 880 }; 881 882 smp2p-gpdsp { 883 compatible = "qcom,smp2p"; 884 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 885 IPCC_MPROC_SIGNAL_SMP2P 886 IRQ_TYPE_EDGE_RISING>; 887 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 888 IPCC_MPROC_SIGNAL_SMP2P>; 889 890 qcom,smem = <617>, <616>; 891 qcom,local-pid = <0>; 892 qcom,remote-pid = <17>; 893 894 smp2p_gpdsp_in: slave-kernel { 895 qcom,entry-name = "slave-kernel"; 896 interrupt-controller; 897 #interrupt-cells = <2>; 898 }; 899 900 smp2p_gpdsp_out: master-kernel { 901 qcom,entry-name = "master-kernel"; 902 #qcom,smem-state-cells = <1>; 903 }; 904 }; 905 906 soc: soc@0 { 907 compatible = "simple-bus"; 908 ranges = <0 0 0 0 0x10 0>; 909 #address-cells = <2>; 910 #size-cells = <2>; 911 912 gcc: clock-controller@100000 { 913 compatible = "qcom,qcs8300-gcc"; 914 reg = <0x0 0x00100000 0x0 0xc7018>; 915 #clock-cells = <1>; 916 #reset-cells = <1>; 917 #power-domain-cells = <1>; 918 clocks = <&rpmhcc RPMH_CXO_CLK>, 919 <&sleep_clk>, 920 <&pcie0_phy>, 921 <&pcie1_phy>, 922 <0>, 923 <0>, 924 <0>, 925 <0>, 926 <0>, 927 <0>; 928 }; 929 930 ipcc: mailbox@408000 { 931 compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; 932 reg = <0x0 0x408000 0x0 0x1000>; 933 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 934 interrupt-controller; 935 #interrupt-cells = <3>; 936 #mbox-cells = <2>; 937 }; 938 939 qfprom: efuse@784000 { 940 compatible = "qcom,qcs8300-qfprom", "qcom,qfprom"; 941 reg = <0x0 0x00784000 0x0 0x2410>; 942 #address-cells = <1>; 943 #size-cells = <1>; 944 945 gpu_speed_bin: gpu-speed-bin@240c { 946 reg = <0x240c 0x1>; 947 bits = <0 8>; 948 }; 949 }; 950 951 gpi_dma0: dma-controller@900000 { 952 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 953 reg = <0x0 0x900000 0x0 0x60000>; 954 #dma-cells = <3>; 955 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 967 iommus = <&apps_smmu 0x416 0x0>; 968 dma-channels = <12>; 969 dma-channel-mask = <0xfff>; 970 dma-coherent; 971 status = "disabled"; 972 }; 973 974 qupv3_id_0: geniqup@9c0000 { 975 compatible = "qcom,geni-se-qup"; 976 reg = <0x0 0x9c0000 0x0 0x2000>; 977 ranges; 978 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 979 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 980 clock-names = "m-ahb", 981 "s-ahb"; 982 #address-cells = <2>; 983 #size-cells = <2>; 984 iommus = <&apps_smmu 0x403 0x0>; 985 dma-coherent; 986 status = "disabled"; 987 988 i2c0: i2c@980000 { 989 compatible = "qcom,geni-i2c"; 990 reg = <0x0 0x980000 0x0 0x4000>; 991 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 992 clock-names = "se"; 993 pinctrl-0 = <&qup_i2c0_data_clk>; 994 pinctrl-names = "default"; 995 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 996 #address-cells = <1>; 997 #size-cells = <0>; 998 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 999 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1000 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1001 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1002 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1003 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1004 interconnect-names = "qup-core", 1005 "qup-config", 1006 "qup-memory"; 1007 power-domains = <&rpmhpd RPMHPD_CX>; 1008 required-opps = <&rpmhpd_opp_low_svs>; 1009 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1010 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1011 dma-names = "tx", 1012 "rx"; 1013 status = "disabled"; 1014 }; 1015 1016 spi0: spi@980000 { 1017 compatible = "qcom,geni-spi"; 1018 reg = <0x0 0x980000 0x0 0x4000>; 1019 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1020 clock-names = "se"; 1021 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1022 pinctrl-names = "default"; 1023 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1027 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1028 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1029 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1030 interconnect-names = "qup-core", 1031 "qup-config"; 1032 power-domains = <&rpmhpd RPMHPD_CX>; 1033 operating-points-v2 = <&qup_opp_table>; 1034 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1035 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1036 dma-names = "tx", 1037 "rx"; 1038 status = "disabled"; 1039 }; 1040 1041 uart0: serial@980000 { 1042 compatible = "qcom,geni-uart"; 1043 reg = <0x0 0x980000 0x0 0x4000>; 1044 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1045 clock-names = "se"; 1046 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, 1047 <&qup_uart0_tx>, <&qup_uart0_rx>; 1048 pinctrl-names = "default"; 1049 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1050 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1051 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1052 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1053 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1054 interconnect-names = "qup-core", 1055 "qup-config"; 1056 power-domains = <&rpmhpd RPMHPD_CX>; 1057 operating-points-v2 = <&qup_opp_table>; 1058 status = "disabled"; 1059 }; 1060 1061 i2c1: i2c@984000 { 1062 compatible = "qcom,geni-i2c"; 1063 reg = <0x0 0x984000 0x0 0x4000>; 1064 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1065 clock-names = "se"; 1066 pinctrl-0 = <&qup_i2c1_data_clk>; 1067 pinctrl-names = "default"; 1068 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1072 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1073 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1074 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1075 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1076 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1077 interconnect-names = "qup-core", 1078 "qup-config", 1079 "qup-memory"; 1080 power-domains = <&rpmhpd RPMHPD_CX>; 1081 required-opps = <&rpmhpd_opp_low_svs>; 1082 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1083 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1084 dma-names = "tx", 1085 "rx"; 1086 status = "disabled"; 1087 }; 1088 1089 spi1: spi@984000 { 1090 compatible = "qcom,geni-spi"; 1091 reg = <0x0 0x984000 0x0 0x4000>; 1092 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1093 clock-names = "se"; 1094 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1095 pinctrl-names = "default"; 1096 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1097 #address-cells = <1>; 1098 #size-cells = <0>; 1099 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1100 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1101 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1102 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1103 interconnect-names = "qup-core", 1104 "qup-config"; 1105 power-domains = <&rpmhpd RPMHPD_CX>; 1106 operating-points-v2 = <&qup_opp_table>; 1107 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1108 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1109 dma-names = "tx", 1110 "rx"; 1111 status = "disabled"; 1112 }; 1113 1114 uart1: serial@984000 { 1115 compatible = "qcom,geni-uart"; 1116 reg = <0x0 0x984000 0x0 0x4000>; 1117 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1118 clock-names = "se"; 1119 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, 1120 <&qup_uart1_tx>, <&qup_uart1_rx>; 1121 pinctrl-names = "default"; 1122 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1123 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1124 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1125 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1126 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1127 interconnect-names = "qup-core", 1128 "qup-config"; 1129 power-domains = <&rpmhpd RPMHPD_CX>; 1130 operating-points-v2 = <&qup_opp_table>; 1131 status = "disabled"; 1132 }; 1133 1134 i2c2: i2c@988000 { 1135 compatible = "qcom,geni-i2c"; 1136 reg = <0x0 0x988000 0x0 0x4000>; 1137 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1138 clock-names = "se"; 1139 pinctrl-0 = <&qup_i2c2_data_clk>; 1140 pinctrl-names = "default"; 1141 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1145 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1146 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1147 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1148 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1149 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1150 interconnect-names = "qup-core", 1151 "qup-config", 1152 "qup-memory"; 1153 power-domains = <&rpmhpd RPMHPD_CX>; 1154 required-opps = <&rpmhpd_opp_low_svs>; 1155 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1156 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1157 dma-names = "tx", 1158 "rx"; 1159 status = "disabled"; 1160 }; 1161 1162 spi2: spi@988000 { 1163 compatible = "qcom,geni-spi"; 1164 reg = <0x0 0x988000 0x0 0x4000>; 1165 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1166 clock-names = "se"; 1167 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1168 pinctrl-names = "default"; 1169 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1173 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1174 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1175 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1176 interconnect-names = "qup-core", 1177 "qup-config"; 1178 power-domains = <&rpmhpd RPMHPD_CX>; 1179 operating-points-v2 = <&qup_opp_table>; 1180 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1181 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1182 dma-names = "tx", 1183 "rx"; 1184 status = "disabled"; 1185 }; 1186 1187 uart2: serial@988000 { 1188 compatible = "qcom,geni-uart"; 1189 reg = <0x0 0x988000 0x0 0x4000>; 1190 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1191 clock-names = "se"; 1192 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, 1193 <&qup_uart2_tx>, <&qup_uart2_rx>; 1194 pinctrl-names = "default"; 1195 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1196 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1197 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1198 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1199 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1200 interconnect-names = "qup-core", 1201 "qup-config"; 1202 power-domains = <&rpmhpd RPMHPD_CX>; 1203 operating-points-v2 = <&qup_opp_table>; 1204 status = "disabled"; 1205 }; 1206 1207 i2c3: i2c@98c000 { 1208 compatible = "qcom,geni-i2c"; 1209 reg = <0x0 0x98c000 0x0 0x4000>; 1210 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1211 clock-names = "se"; 1212 pinctrl-0 = <&qup_i2c3_data_clk>; 1213 pinctrl-names = "default"; 1214 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1218 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1219 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1220 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1221 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1222 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1223 interconnect-names = "qup-core", 1224 "qup-config", 1225 "qup-memory"; 1226 power-domains = <&rpmhpd RPMHPD_CX>; 1227 required-opps = <&rpmhpd_opp_low_svs>; 1228 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1229 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1230 dma-names = "tx", 1231 "rx"; 1232 status = "disabled"; 1233 }; 1234 1235 spi3: spi@98c000 { 1236 compatible = "qcom,geni-spi"; 1237 reg = <0x0 0x98c000 0x0 0x4000>; 1238 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1239 clock-names = "se"; 1240 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1241 pinctrl-names = "default"; 1242 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1243 #address-cells = <1>; 1244 #size-cells = <0>; 1245 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1246 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1247 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1248 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1249 interconnect-names = "qup-core", 1250 "qup-config"; 1251 power-domains = <&rpmhpd RPMHPD_CX>; 1252 operating-points-v2 = <&qup_opp_table>; 1253 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1254 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1255 dma-names = "tx", 1256 "rx"; 1257 status = "disabled"; 1258 }; 1259 1260 uart3: serial@98c000 { 1261 compatible = "qcom,geni-uart"; 1262 reg = <0x0 0x98c000 0x0 0x4000>; 1263 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1264 clock-names = "se"; 1265 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, 1266 <&qup_uart3_tx>, <&qup_uart3_rx>; 1267 pinctrl-names = "default"; 1268 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1269 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1270 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1271 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1272 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1273 interconnect-names = "qup-core", 1274 "qup-config"; 1275 power-domains = <&rpmhpd RPMHPD_CX>; 1276 operating-points-v2 = <&qup_opp_table>; 1277 status = "disabled"; 1278 }; 1279 1280 i2c4: i2c@990000 { 1281 compatible = "qcom,geni-i2c"; 1282 reg = <0x0 0x990000 0x0 0x4000>; 1283 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1284 clock-names = "se"; 1285 pinctrl-0 = <&qup_i2c4_data_clk>; 1286 pinctrl-names = "default"; 1287 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1288 #address-cells = <1>; 1289 #size-cells = <0>; 1290 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1291 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1292 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1293 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1294 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1295 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1296 interconnect-names = "qup-core", 1297 "qup-config", 1298 "qup-memory"; 1299 power-domains = <&rpmhpd RPMHPD_CX>; 1300 required-opps = <&rpmhpd_opp_low_svs>; 1301 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1302 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1303 dma-names = "tx", 1304 "rx"; 1305 status = "disabled"; 1306 }; 1307 1308 spi4: spi@990000 { 1309 compatible = "qcom,geni-spi"; 1310 reg = <0x0 0x990000 0x0 0x4000>; 1311 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1312 clock-names = "se"; 1313 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1314 pinctrl-names = "default"; 1315 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1319 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1320 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1321 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1322 interconnect-names = "qup-core", 1323 "qup-config"; 1324 power-domains = <&rpmhpd RPMHPD_CX>; 1325 operating-points-v2 = <&qup_opp_table>; 1326 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1327 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1328 dma-names = "tx", 1329 "rx"; 1330 status = "disabled"; 1331 }; 1332 1333 uart4: serial@990000 { 1334 compatible = "qcom,geni-uart"; 1335 reg = <0x0 0x990000 0x0 0x4000>; 1336 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1337 clock-names = "se"; 1338 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, 1339 <&qup_uart4_tx>, <&qup_uart4_rx>; 1340 pinctrl-names = "default"; 1341 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1342 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1343 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1344 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1345 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1346 interconnect-names = "qup-core", 1347 "qup-config"; 1348 power-domains = <&rpmhpd RPMHPD_CX>; 1349 operating-points-v2 = <&qup_opp_table>; 1350 status = "disabled"; 1351 }; 1352 1353 i2c5: i2c@994000 { 1354 compatible = "qcom,geni-i2c"; 1355 reg = <0x0 0x994000 0x0 0x4000>; 1356 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1357 clock-names = "se"; 1358 pinctrl-0 = <&qup_i2c5_data_clk>; 1359 pinctrl-names = "default"; 1360 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1364 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1365 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1366 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1367 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1368 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1369 interconnect-names = "qup-core", 1370 "qup-config", 1371 "qup-memory"; 1372 power-domains = <&rpmhpd RPMHPD_CX>; 1373 required-opps = <&rpmhpd_opp_low_svs>; 1374 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1375 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1376 dma-names = "tx", 1377 "rx"; 1378 status = "disabled"; 1379 }; 1380 1381 spi5: spi@994000 { 1382 compatible = "qcom,geni-spi"; 1383 reg = <0x0 0x994000 0x0 0x4000>; 1384 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1385 clock-names = "se"; 1386 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1387 pinctrl-names = "default"; 1388 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1389 #address-cells = <1>; 1390 #size-cells = <0>; 1391 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1392 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1393 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1394 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1395 interconnect-names = "qup-core", 1396 "qup-config"; 1397 power-domains = <&rpmhpd RPMHPD_CX>; 1398 operating-points-v2 = <&qup_opp_table>; 1399 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1400 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1401 dma-names = "tx", 1402 "rx"; 1403 status = "disabled"; 1404 }; 1405 1406 uart5: serial@994000 { 1407 compatible = "qcom,geni-uart"; 1408 reg = <0x0 0x994000 0x0 0x4000>; 1409 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1410 clock-names = "se"; 1411 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, 1412 <&qup_uart5_tx>, <&qup_uart5_rx>; 1413 pinctrl-names = "default"; 1414 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1415 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1416 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1417 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1418 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1419 interconnect-names = "qup-core", 1420 "qup-config"; 1421 power-domains = <&rpmhpd RPMHPD_CX>; 1422 operating-points-v2 = <&qup_opp_table>; 1423 status = "disabled"; 1424 }; 1425 1426 i2c6: i2c@998000 { 1427 compatible = "qcom,geni-i2c"; 1428 reg = <0x0 0x998000 0x0 0x4000>; 1429 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1430 clock-names = "se"; 1431 pinctrl-0 = <&qup_i2c6_data_clk>; 1432 pinctrl-names = "default"; 1433 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1434 #address-cells = <1>; 1435 #size-cells = <0>; 1436 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1437 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1438 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1439 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1440 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1441 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1442 interconnect-names = "qup-core", 1443 "qup-config", 1444 "qup-memory"; 1445 power-domains = <&rpmhpd RPMHPD_CX>; 1446 required-opps = <&rpmhpd_opp_low_svs>; 1447 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1448 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1449 dma-names = "tx", 1450 "rx"; 1451 status = "disabled"; 1452 }; 1453 1454 spi6: spi@998000 { 1455 compatible = "qcom,geni-spi"; 1456 reg = <0x0 0x998000 0x0 0x4000>; 1457 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1458 clock-names = "se"; 1459 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1460 pinctrl-names = "default"; 1461 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1462 #address-cells = <1>; 1463 #size-cells = <0>; 1464 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1465 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1466 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1467 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1468 interconnect-names = "qup-core", 1469 "qup-config"; 1470 power-domains = <&rpmhpd RPMHPD_CX>; 1471 operating-points-v2 = <&qup_opp_table>; 1472 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1473 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1474 dma-names = "tx", 1475 "rx"; 1476 status = "disabled"; 1477 }; 1478 1479 uart6: serial@998000 { 1480 compatible = "qcom,geni-uart"; 1481 reg = <0x0 0x998000 0x0 0x4000>; 1482 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1483 clock-names = "se"; 1484 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, 1485 <&qup_uart6_tx>, <&qup_uart6_rx>; 1486 pinctrl-names = "default"; 1487 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1488 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1489 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1490 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1491 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1492 interconnect-names = "qup-core", 1493 "qup-config"; 1494 power-domains = <&rpmhpd RPMHPD_CX>; 1495 operating-points-v2 = <&qup_opp_table>; 1496 status = "disabled"; 1497 }; 1498 1499 uart7: serial@99c000 { 1500 compatible = "qcom,geni-debug-uart"; 1501 reg = <0x0 0x0099c000 0x0 0x4000>; 1502 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1503 clock-names = "se"; 1504 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1505 pinctrl-names = "default"; 1506 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1507 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1508 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1509 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1510 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1511 interconnect-names = "qup-core", 1512 "qup-config"; 1513 power-domains = <&rpmhpd RPMHPD_CX>; 1514 operating-points-v2 = <&qup_opp_table>; 1515 status = "disabled"; 1516 }; 1517 }; 1518 1519 gpi_dma1: dma-controller@a00000 { 1520 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 1521 reg = <0x0 0xa00000 0x0 0x60000>; 1522 #dma-cells = <3>; 1523 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1535 iommus = <&apps_smmu 0x456 0x0>; 1536 dma-channels = <12>; 1537 dma-channel-mask = <0xfff>; 1538 dma-coherent; 1539 status = "disabled"; 1540 }; 1541 1542 qupv3_id_1: geniqup@ac0000 { 1543 compatible = "qcom,geni-se-qup"; 1544 reg = <0x0 0xac0000 0x0 0x2000>; 1545 ranges; 1546 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1547 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1548 clock-names = "m-ahb", 1549 "s-ahb"; 1550 #address-cells = <2>; 1551 #size-cells = <2>; 1552 iommus = <&apps_smmu 0x443 0x0>; 1553 dma-coherent; 1554 status = "disabled"; 1555 1556 i2c8: i2c@a80000 { 1557 compatible = "qcom,geni-i2c"; 1558 reg = <0x0 0xa80000 0x0 0x4000>; 1559 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1560 clock-names = "se"; 1561 pinctrl-0 = <&qup_i2c8_data_clk>; 1562 pinctrl-names = "default"; 1563 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1564 #address-cells = <1>; 1565 #size-cells = <0>; 1566 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1567 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1568 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1569 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1570 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1571 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1572 interconnect-names = "qup-core", 1573 "qup-config", 1574 "qup-memory"; 1575 power-domains = <&rpmhpd RPMHPD_CX>; 1576 required-opps = <&rpmhpd_opp_low_svs>; 1577 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1578 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1579 dma-names = "tx", 1580 "rx"; 1581 status = "disabled"; 1582 }; 1583 1584 spi8: spi@a80000 { 1585 compatible = "qcom,geni-spi"; 1586 reg = <0x0 0xa80000 0x0 0x4000>; 1587 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1588 clock-names = "se"; 1589 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1590 pinctrl-names = "default"; 1591 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1592 #address-cells = <1>; 1593 #size-cells = <0>; 1594 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1595 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1596 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1597 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1598 interconnect-names = "qup-core", 1599 "qup-config"; 1600 power-domains = <&rpmhpd RPMHPD_CX>; 1601 operating-points-v2 = <&qup_opp_table>; 1602 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1603 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1604 dma-names = "tx", 1605 "rx"; 1606 status = "disabled"; 1607 }; 1608 1609 uart8: serial@a80000 { 1610 compatible = "qcom,geni-uart"; 1611 reg = <0x0 0xa80000 0x0 0x4000>; 1612 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1613 clock-names = "se"; 1614 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, 1615 <&qup_uart8_tx>, <&qup_uart8_rx>; 1616 pinctrl-names = "default"; 1617 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1618 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1619 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1620 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1621 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1622 interconnect-names = "qup-core", 1623 "qup-config"; 1624 power-domains = <&rpmhpd RPMHPD_CX>; 1625 operating-points-v2 = <&qup_opp_table>; 1626 status = "disabled"; 1627 }; 1628 1629 i2c9: i2c@a84000 { 1630 compatible = "qcom,geni-i2c"; 1631 reg = <0x0 0xa84000 0x0 0x4000>; 1632 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1633 clock-names = "se"; 1634 pinctrl-0 = <&qup_i2c9_data_clk>; 1635 pinctrl-names = "default"; 1636 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1637 #address-cells = <1>; 1638 #size-cells = <0>; 1639 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1640 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1641 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1642 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1643 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1644 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1645 interconnect-names = "qup-core", 1646 "qup-config", 1647 "qup-memory"; 1648 power-domains = <&rpmhpd RPMHPD_CX>; 1649 required-opps = <&rpmhpd_opp_low_svs>; 1650 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1651 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1652 dma-names = "tx", 1653 "rx"; 1654 status = "disabled"; 1655 }; 1656 1657 spi9: spi@a84000 { 1658 compatible = "qcom,geni-spi"; 1659 reg = <0x0 0xa84000 0x0 0x4000>; 1660 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1661 clock-names = "se"; 1662 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1663 pinctrl-names = "default"; 1664 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1665 #address-cells = <1>; 1666 #size-cells = <0>; 1667 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1668 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1669 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1670 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1671 interconnect-names = "qup-core", 1672 "qup-config"; 1673 power-domains = <&rpmhpd RPMHPD_CX>; 1674 operating-points-v2 = <&qup_opp_table>; 1675 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1676 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1677 dma-names = "tx", 1678 "rx"; 1679 status = "disabled"; 1680 }; 1681 1682 uart9: serial@a84000 { 1683 compatible = "qcom,geni-uart"; 1684 reg = <0x0 0xa84000 0x0 0x4000>; 1685 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1686 clock-names = "se"; 1687 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, 1688 <&qup_uart9_tx>, <&qup_uart9_rx>; 1689 pinctrl-names = "default"; 1690 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1691 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1692 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1693 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1694 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1695 interconnect-names = "qup-core", 1696 "qup-config"; 1697 power-domains = <&rpmhpd RPMHPD_CX>; 1698 operating-points-v2 = <&qup_opp_table>; 1699 status = "disabled"; 1700 }; 1701 1702 i2c10: i2c@a88000 { 1703 compatible = "qcom,geni-i2c"; 1704 reg = <0x0 0xa88000 0x0 0x4000>; 1705 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1706 clock-names = "se"; 1707 pinctrl-0 = <&qup_i2c10_data_clk>; 1708 pinctrl-names = "default"; 1709 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1710 #address-cells = <1>; 1711 #size-cells = <0>; 1712 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1713 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1714 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1715 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1716 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1717 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1718 interconnect-names = "qup-core", 1719 "qup-config", 1720 "qup-memory"; 1721 power-domains = <&rpmhpd RPMHPD_CX>; 1722 required-opps = <&rpmhpd_opp_low_svs>; 1723 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1724 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1725 dma-names = "tx", 1726 "rx"; 1727 status = "disabled"; 1728 }; 1729 1730 spi10: spi@a88000 { 1731 compatible = "qcom,geni-spi"; 1732 reg = <0x0 0xa88000 0x0 0x4000>; 1733 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1734 clock-names = "se"; 1735 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1736 pinctrl-names = "default"; 1737 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1741 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1742 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1743 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1744 interconnect-names = "qup-core", 1745 "qup-config"; 1746 power-domains = <&rpmhpd RPMHPD_CX>; 1747 operating-points-v2 = <&qup_opp_table>; 1748 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1749 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1750 dma-names = "tx", 1751 "rx"; 1752 status = "disabled"; 1753 }; 1754 1755 uart10: serial@a88000 { 1756 compatible = "qcom,geni-uart"; 1757 reg = <0x0 0xa88000 0x0 0x4000>; 1758 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1759 clock-names = "se"; 1760 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, 1761 <&qup_uart10_tx>, <&qup_uart10_rx>; 1762 pinctrl-names = "default"; 1763 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1764 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1765 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1766 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1767 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1768 interconnect-names = "qup-core", 1769 "qup-config"; 1770 power-domains = <&rpmhpd RPMHPD_CX>; 1771 operating-points-v2 = <&qup_opp_table>; 1772 status = "disabled"; 1773 }; 1774 1775 i2c11: i2c@a8c000 { 1776 compatible = "qcom,geni-i2c"; 1777 reg = <0x0 0xa8c000 0x0 0x4000>; 1778 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1779 clock-names = "se"; 1780 pinctrl-0 = <&qup_i2c11_data_clk>; 1781 pinctrl-names = "default"; 1782 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1783 #address-cells = <1>; 1784 #size-cells = <0>; 1785 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1786 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1787 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1788 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1789 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1790 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1791 interconnect-names = "qup-core", 1792 "qup-config", 1793 "qup-memory"; 1794 power-domains = <&rpmhpd RPMHPD_CX>; 1795 required-opps = <&rpmhpd_opp_low_svs>; 1796 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1797 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1798 dma-names = "tx", 1799 "rx"; 1800 status = "disabled"; 1801 }; 1802 1803 uart11: serial@a8c000 { 1804 compatible = "qcom,geni-uart"; 1805 reg = <0x0 0xa8c000 0x0 0x4000>; 1806 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1807 clock-names = "se"; 1808 pinctrl-0 = <&qup_uart11_tx>, <&qup_uart11_rx>; 1809 pinctrl-names = "default"; 1810 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1811 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1812 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1813 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1814 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1815 interconnect-names = "qup-core", 1816 "qup-config"; 1817 power-domains = <&rpmhpd RPMHPD_CX>; 1818 operating-points-v2 = <&qup_opp_table>; 1819 status = "disabled"; 1820 }; 1821 1822 i2c12: i2c@a90000 { 1823 compatible = "qcom,geni-i2c"; 1824 reg = <0x0 0xa90000 0x0 0x4000>; 1825 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1826 clock-names = "se"; 1827 pinctrl-0 = <&qup_i2c12_data_clk>; 1828 pinctrl-names = "default"; 1829 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1830 #address-cells = <1>; 1831 #size-cells = <0>; 1832 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1833 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1834 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1835 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1836 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1837 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1838 interconnect-names = "qup-core", 1839 "qup-config", 1840 "qup-memory"; 1841 power-domains = <&rpmhpd RPMHPD_CX>; 1842 required-opps = <&rpmhpd_opp_low_svs>; 1843 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1844 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1845 dma-names = "tx", 1846 "rx"; 1847 status = "disabled"; 1848 }; 1849 1850 spi12: spi@a90000 { 1851 compatible = "qcom,geni-spi"; 1852 reg = <0x0 0xa90000 0x0 0x4000>; 1853 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1854 clock-names = "se"; 1855 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1856 pinctrl-names = "default"; 1857 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1858 #address-cells = <1>; 1859 #size-cells = <0>; 1860 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1861 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1862 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1863 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1864 interconnect-names = "qup-core", 1865 "qup-config"; 1866 power-domains = <&rpmhpd RPMHPD_CX>; 1867 operating-points-v2 = <&qup_opp_table>; 1868 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1869 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1870 dma-names = "tx", 1871 "rx"; 1872 status = "disabled"; 1873 }; 1874 1875 uart12: serial@a90000 { 1876 compatible = "qcom,geni-uart"; 1877 reg = <0x0 0xa90000 0x0 0x4000>; 1878 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1879 clock-names = "se"; 1880 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, 1881 <&qup_uart12_tx>, <&qup_uart12_rx>; 1882 pinctrl-names = "default"; 1883 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1884 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1885 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1886 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1887 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1888 interconnect-names = "qup-core", 1889 "qup-config"; 1890 power-domains = <&rpmhpd RPMHPD_CX>; 1891 operating-points-v2 = <&qup_opp_table>; 1892 status = "disabled"; 1893 }; 1894 1895 i2c13: i2c@a94000 { 1896 compatible = "qcom,geni-i2c"; 1897 reg = <0x0 0xa94000 0x0 0x4000>; 1898 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1899 clock-names = "se"; 1900 pinctrl-0 = <&qup_i2c13_data_clk>; 1901 pinctrl-names = "default"; 1902 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1903 #address-cells = <1>; 1904 #size-cells = <0>; 1905 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1906 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1907 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1908 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1909 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1910 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1911 interconnect-names = "qup-core", 1912 "qup-config", 1913 "qup-memory"; 1914 power-domains = <&rpmhpd RPMHPD_CX>; 1915 required-opps = <&rpmhpd_opp_low_svs>; 1916 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1917 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1918 dma-names = "tx", 1919 "rx"; 1920 status = "disabled"; 1921 }; 1922 1923 spi13: spi@a94000 { 1924 compatible = "qcom,geni-spi"; 1925 reg = <0x0 0xa94000 0x0 0x4000>; 1926 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1927 clock-names = "se"; 1928 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1929 pinctrl-names = "default"; 1930 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1931 #address-cells = <1>; 1932 #size-cells = <0>; 1933 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1934 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1935 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1936 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1937 interconnect-names = "qup-core", 1938 "qup-config"; 1939 power-domains = <&rpmhpd RPMHPD_CX>; 1940 operating-points-v2 = <&qup_opp_table>; 1941 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1942 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1943 dma-names = "tx", 1944 "rx"; 1945 status = "disabled"; 1946 }; 1947 1948 uart13: serial@a94000 { 1949 compatible = "qcom,geni-uart"; 1950 reg = <0x0 0xa94000 0x0 0x4000>; 1951 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1952 clock-names = "se"; 1953 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, 1954 <&qup_uart13_tx>, <&qup_uart13_rx>; 1955 pinctrl-names = "default"; 1956 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1957 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1958 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1959 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1960 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1961 interconnect-names = "qup-core", 1962 "qup-config"; 1963 power-domains = <&rpmhpd RPMHPD_CX>; 1964 operating-points-v2 = <&qup_opp_table>; 1965 status = "disabled"; 1966 }; 1967 1968 i2c14: i2c@a98000 { 1969 compatible = "qcom,geni-i2c"; 1970 reg = <0x0 0xa98000 0x0 0x4000>; 1971 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1972 clock-names = "se"; 1973 pinctrl-0 = <&qup_i2c14_data_clk>; 1974 pinctrl-names = "default"; 1975 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1976 #address-cells = <1>; 1977 #size-cells = <0>; 1978 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1979 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1980 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1981 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1982 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1983 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1984 interconnect-names = "qup-core", 1985 "qup-config", 1986 "qup-memory"; 1987 power-domains = <&rpmhpd RPMHPD_CX>; 1988 required-opps = <&rpmhpd_opp_low_svs>; 1989 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1990 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1991 dma-names = "tx", 1992 "rx"; 1993 status = "disabled"; 1994 }; 1995 1996 spi14: spi@a98000 { 1997 compatible = "qcom,geni-spi"; 1998 reg = <0x0 0xa98000 0x0 0x4000>; 1999 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2000 clock-names = "se"; 2001 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 2002 pinctrl-names = "default"; 2003 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2004 #address-cells = <1>; 2005 #size-cells = <0>; 2006 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2007 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2008 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2009 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2010 interconnect-names = "qup-core", 2011 "qup-config"; 2012 power-domains = <&rpmhpd RPMHPD_CX>; 2013 operating-points-v2 = <&qup_opp_table>; 2014 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2015 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2016 dma-names = "tx", 2017 "rx"; 2018 status = "disabled"; 2019 }; 2020 2021 uart14: serial@a98000 { 2022 compatible = "qcom,geni-uart"; 2023 reg = <0x0 0xa98000 0x0 0x4000>; 2024 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2025 clock-names = "se"; 2026 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, 2027 <&qup_uart14_tx>, <&qup_uart14_rx>; 2028 pinctrl-names = "default"; 2029 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2030 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2031 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2032 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2033 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2034 interconnect-names = "qup-core", 2035 "qup-config"; 2036 power-domains = <&rpmhpd RPMHPD_CX>; 2037 operating-points-v2 = <&qup_opp_table>; 2038 status = "disabled"; 2039 }; 2040 2041 i2c15: i2c@a9c000 { 2042 compatible = "qcom,geni-i2c"; 2043 reg = <0x0 0xa9c000 0x0 0x4000>; 2044 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2045 clock-names = "se"; 2046 pinctrl-0 = <&qup_i2c15_data_clk>; 2047 pinctrl-names = "default"; 2048 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2049 #address-cells = <1>; 2050 #size-cells = <0>; 2051 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2052 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2053 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2054 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2055 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2056 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2057 interconnect-names = "qup-core", 2058 "qup-config", 2059 "qup-memory"; 2060 power-domains = <&rpmhpd RPMHPD_CX>; 2061 required-opps = <&rpmhpd_opp_low_svs>; 2062 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2063 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2064 dma-names = "tx", 2065 "rx"; 2066 status = "disabled"; 2067 }; 2068 2069 spi15: spi@a9c000 { 2070 compatible = "qcom,geni-spi"; 2071 reg = <0x0 0xa9c000 0x0 0x4000>; 2072 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2073 clock-names = "se"; 2074 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2075 pinctrl-names = "default"; 2076 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2077 #address-cells = <1>; 2078 #size-cells = <0>; 2079 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2080 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2081 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2082 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2083 interconnect-names = "qup-core", 2084 "qup-config"; 2085 power-domains = <&rpmhpd RPMHPD_CX>; 2086 operating-points-v2 = <&qup_opp_table>; 2087 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2088 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2089 dma-names = "tx", 2090 "rx"; 2091 status = "disabled"; 2092 }; 2093 2094 uart15: serial@a9c000 { 2095 compatible = "qcom,geni-uart"; 2096 reg = <0x0 0xa9c000 0x0 0x4000>; 2097 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2098 clock-names = "se"; 2099 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, 2100 <&qup_uart15_tx>, <&qup_uart15_rx>; 2101 pinctrl-names = "default"; 2102 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2103 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2104 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2105 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2106 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2107 interconnect-names = "qup-core", 2108 "qup-config"; 2109 power-domains = <&rpmhpd RPMHPD_CX>; 2110 operating-points-v2 = <&qup_opp_table>; 2111 status = "disabled"; 2112 }; 2113 }; 2114 2115 gpi_dma3: dma-controller@b00000 { 2116 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 2117 reg = <0x0 0xb00000 0x0 0x60000>; 2118 #dma-cells = <3>; 2119 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2120 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 2121 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2122 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>; 2123 iommus = <&apps_smmu 0x56 0x0>; 2124 dma-channels = <4>; 2125 dma-channel-mask = <0xf>; 2126 dma-coherent; 2127 status = "disabled"; 2128 }; 2129 2130 qupv3_id_3: geniqup@bc0000 { 2131 compatible = "qcom,geni-se-qup"; 2132 reg = <0x0 0xbc0000 0x0 0x2000>; 2133 ranges; 2134 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 2135 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 2136 clock-names = "m-ahb", 2137 "s-ahb"; 2138 #address-cells = <2>; 2139 #size-cells = <2>; 2140 iommus = <&apps_smmu 0x43 0x0>; 2141 dma-coherent; 2142 status = "disabled"; 2143 2144 i2c16: i2c@b80000 { 2145 compatible = "qcom,geni-i2c"; 2146 reg = <0x0 0xb80000 0x0 0x4000>; 2147 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2148 clock-names = "se"; 2149 pinctrl-0 = <&qup_i2c16_data_clk>; 2150 pinctrl-names = "default"; 2151 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 2152 #address-cells = <1>; 2153 #size-cells = <0>; 2154 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2155 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2156 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2157 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2158 <&aggre2_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2159 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2160 interconnect-names = "qup-core", 2161 "qup-config", 2162 "qup-memory"; 2163 power-domains = <&rpmhpd RPMHPD_CX>; 2164 required-opps = <&rpmhpd_opp_low_svs>; 2165 dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, 2166 <&gpi_dma3 1 0 QCOM_GPI_I2C>; 2167 dma-names = "tx", 2168 "rx"; 2169 status = "disabled"; 2170 }; 2171 2172 spi16: spi@b80000 { 2173 compatible = "qcom,geni-spi"; 2174 reg = <0x0 0xb80000 0x0 0x4000>; 2175 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2176 clock-names = "se"; 2177 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 2178 pinctrl-names = "default"; 2179 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 2180 #address-cells = <1>; 2181 #size-cells = <0>; 2182 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2183 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2184 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2185 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2186 interconnect-names = "qup-core", 2187 "qup-config"; 2188 power-domains = <&rpmhpd RPMHPD_CX>; 2189 operating-points-v2 = <&qup_opp_table>; 2190 dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>, 2191 <&gpi_dma3 1 0 QCOM_GPI_SPI>; 2192 dma-names = "tx", 2193 "rx"; 2194 status = "disabled"; 2195 }; 2196 2197 uart16: serial@b80000 { 2198 compatible = "qcom,geni-uart"; 2199 reg = <0x0 0xb80000 0x0 0x4000>; 2200 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2201 clock-names = "se"; 2202 pinctrl-0 = <&qup_uart16_cts>, <&qup_uart16_rts>, 2203 <&qup_uart16_tx>, <&qup_uart16_rx>; 2204 pinctrl-names = "default"; 2205 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 2206 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2207 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2208 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2209 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2210 interconnect-names = "qup-core", 2211 "qup-config"; 2212 power-domains = <&rpmhpd RPMHPD_CX>; 2213 operating-points-v2 = <&qup_opp_table>; 2214 status = "disabled"; 2215 }; 2216 }; 2217 2218 rng: rng@10d2000 { 2219 compatible = "qcom,qcs8300-trng", "qcom,trng"; 2220 reg = <0x0 0x010d2000 0x0 0x1000>; 2221 }; 2222 2223 config_noc: interconnect@14c0000 { 2224 compatible = "qcom,qcs8300-config-noc"; 2225 reg = <0x0 0x014c0000 0x0 0x13080>; 2226 #interconnect-cells = <2>; 2227 qcom,bcm-voters = <&apps_bcm_voter>; 2228 }; 2229 2230 system_noc: interconnect@1680000 { 2231 compatible = "qcom,qcs8300-system-noc"; 2232 reg = <0x0 0x01680000 0x0 0x15080>; 2233 #interconnect-cells = <2>; 2234 qcom,bcm-voters = <&apps_bcm_voter>; 2235 }; 2236 2237 aggre1_noc: interconnect@16c0000 { 2238 compatible = "qcom,qcs8300-aggre1-noc"; 2239 reg = <0x0 0x016c0000 0x0 0x17080>; 2240 #interconnect-cells = <2>; 2241 qcom,bcm-voters = <&apps_bcm_voter>; 2242 }; 2243 2244 aggre2_noc: interconnect@1700000 { 2245 compatible = "qcom,qcs8300-aggre2-noc"; 2246 reg = <0x0 0x01700000 0x0 0x1a080>; 2247 #interconnect-cells = <2>; 2248 qcom,bcm-voters = <&apps_bcm_voter>; 2249 }; 2250 2251 pcie_anoc: interconnect@1760000 { 2252 compatible = "qcom,qcs8300-pcie-anoc"; 2253 reg = <0x0 0x01760000 0x0 0xc080>; 2254 #interconnect-cells = <2>; 2255 qcom,bcm-voters = <&apps_bcm_voter>; 2256 }; 2257 2258 gpdsp_anoc: interconnect@1780000 { 2259 compatible = "qcom,qcs8300-gpdsp-anoc"; 2260 reg = <0x0 0x01780000 0x0 0xd080>; 2261 #interconnect-cells = <2>; 2262 qcom,bcm-voters = <&apps_bcm_voter>; 2263 }; 2264 2265 mmss_noc: interconnect@17a0000 { 2266 compatible = "qcom,qcs8300-mmss-noc"; 2267 reg = <0x0 0x017a0000 0x0 0x40000>; 2268 #interconnect-cells = <2>; 2269 qcom,bcm-voters = <&apps_bcm_voter>; 2270 }; 2271 2272 pcie0: pci@1c00000 { 2273 device_type = "pci"; 2274 compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; 2275 reg = <0x0 0x01c00000 0x0 0x3000>, 2276 <0x0 0x40000000 0x0 0xf20>, 2277 <0x0 0x40000f20 0x0 0xa8>, 2278 <0x0 0x40001000 0x0 0x4000>, 2279 <0x0 0x40100000 0x0 0x100000>, 2280 <0x0 0x01c03000 0x0 0x1000>; 2281 reg-names = "parf", 2282 "dbi", 2283 "elbi", 2284 "atu", 2285 "config", 2286 "mhi"; 2287 #address-cells = <3>; 2288 #size-cells = <2>; 2289 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2290 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2291 bus-range = <0x00 0xff>; 2292 2293 dma-coherent; 2294 2295 linux,pci-domain = <0>; 2296 num-lanes = <2>; 2297 2298 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2299 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2300 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2301 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2302 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2303 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2304 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2305 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2306 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2307 interrupt-names = "msi0", 2308 "msi1", 2309 "msi2", 2310 "msi3", 2311 "msi4", 2312 "msi5", 2313 "msi6", 2314 "msi7", 2315 "global"; 2316 2317 #interrupt-cells = <1>; 2318 interrupt-map-mask = <0 0 0 0x7>; 2319 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2320 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2321 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 2322 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 2323 2324 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2325 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2326 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2327 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2328 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 2329 clock-names = "aux", 2330 "cfg", 2331 "bus_master", 2332 "bus_slave", 2333 "slave_q2a"; 2334 2335 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 2336 assigned-clock-rates = <19200000>; 2337 2338 interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 2339 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2340 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2341 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 2342 interconnect-names = "pcie-mem", 2343 "cpu-pcie"; 2344 2345 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, 2346 <0x100 &pcie_smmu 0x0001 0x1>; 2347 2348 resets = <&gcc GCC_PCIE_0_BCR>, 2349 <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; 2350 reset-names = "pci", 2351 "link_down"; 2352 2353 power-domains = <&gcc GCC_PCIE_0_GDSC>; 2354 2355 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 2356 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 2357 2358 operating-points-v2 = <&pcie0_opp_table>; 2359 2360 status = "disabled"; 2361 2362 pcie0_opp_table: opp-table { 2363 compatible = "operating-points-v2"; 2364 2365 /* GEN 1 x1 */ 2366 opp-2500000 { 2367 opp-hz = /bits/ 64 <2500000>; 2368 required-opps = <&rpmhpd_opp_svs_l1>; 2369 opp-peak-kBps = <250000 1>; 2370 }; 2371 2372 /* GEN 1 x2 and GEN 2 x1 */ 2373 opp-5000000 { 2374 opp-hz = /bits/ 64 <5000000>; 2375 required-opps = <&rpmhpd_opp_svs_l1>; 2376 opp-peak-kBps = <500000 1>; 2377 }; 2378 2379 /* GEN 2 x2 */ 2380 opp-10000000 { 2381 opp-hz = /bits/ 64 <10000000>; 2382 required-opps = <&rpmhpd_opp_svs_l1>; 2383 opp-peak-kBps = <1000000 1>; 2384 }; 2385 2386 /* GEN 3 x1 */ 2387 opp-8000000 { 2388 opp-hz = /bits/ 64 <8000000>; 2389 required-opps = <&rpmhpd_opp_svs_l1>; 2390 opp-peak-kBps = <984500 1>; 2391 }; 2392 2393 /* GEN 3 x2 and GEN 4 x1 */ 2394 opp-16000000 { 2395 opp-hz = /bits/ 64 <16000000>; 2396 required-opps = <&rpmhpd_opp_nom>; 2397 opp-peak-kBps = <1969000 1>; 2398 }; 2399 2400 /* GEN 4 x2 */ 2401 opp-32000000 { 2402 opp-hz = /bits/ 64 <32000000>; 2403 required-opps = <&rpmhpd_opp_nom>; 2404 opp-peak-kBps = <3938000 1>; 2405 }; 2406 }; 2407 2408 pcieport0: pcie@0 { 2409 device_type = "pci"; 2410 reg = <0x0 0x0 0x0 0x0 0x0>; 2411 bus-range = <0x01 0xff>; 2412 2413 #address-cells = <3>; 2414 #size-cells = <2>; 2415 ranges; 2416 phys = <&pcie0_phy>; 2417 }; 2418 }; 2419 2420 pcie0_phy: phy@1c04000 { 2421 compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy"; 2422 reg = <0x0 0x01c04000 0x0 0x2000>; 2423 2424 clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, 2425 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2426 <&gcc GCC_PCIE_CLKREF_EN>, 2427 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2428 <&gcc GCC_PCIE_0_PIPE_CLK>, 2429 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; 2430 clock-names = "aux", 2431 "cfg_ahb", 2432 "ref", 2433 "rchng", 2434 "pipe", 2435 "pipediv2"; 2436 2437 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2438 reset-names = "phy"; 2439 2440 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2441 assigned-clock-rates = <100000000>; 2442 2443 #clock-cells = <0>; 2444 clock-output-names = "pcie_0_pipe_clk"; 2445 2446 #phy-cells = <0>; 2447 2448 status = "disabled"; 2449 }; 2450 2451 pcie1: pci@1c10000 { 2452 device_type = "pci"; 2453 compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; 2454 reg = <0x0 0x01c10000 0x0 0x3000>, 2455 <0x0 0x60000000 0x0 0xf20>, 2456 <0x0 0x60000f20 0x0 0xa8>, 2457 <0x0 0x60001000 0x0 0x4000>, 2458 <0x0 0x60100000 0x0 0x100000>, 2459 <0x0 0x01c13000 0x0 0x1000>; 2460 reg-names = "parf", 2461 "dbi", 2462 "elbi", 2463 "atu", 2464 "config", 2465 "mhi"; 2466 #address-cells = <3>; 2467 #size-cells = <2>; 2468 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2469 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; 2470 bus-range = <0x00 0xff>; 2471 2472 dma-coherent; 2473 2474 linux,pci-domain = <1>; 2475 num-lanes = <4>; 2476 2477 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 2478 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2479 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2480 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2481 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2482 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2483 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2484 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2485 <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>; 2486 interrupt-names = "msi0", 2487 "msi1", 2488 "msi2", 2489 "msi3", 2490 "msi4", 2491 "msi5", 2492 "msi6", 2493 "msi7", 2494 "global"; 2495 #interrupt-cells = <1>; 2496 interrupt-map-mask = <0 0 0 0x7>; 2497 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2498 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2499 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2500 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 2501 2502 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2503 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2504 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2505 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2506 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 2507 clock-names = "aux", 2508 "cfg", 2509 "bus_master", 2510 "bus_slave", 2511 "slave_q2a"; 2512 2513 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2514 assigned-clock-rates = <19200000>; 2515 2516 interconnects = <&pcie_anoc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 2517 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2518 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2519 &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2520 interconnect-names = "pcie-mem", "cpu-pcie"; 2521 2522 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, 2523 <0x100 &pcie_smmu 0x0081 0x1>; 2524 2525 resets = <&gcc GCC_PCIE_1_BCR>, 2526 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 2527 reset-names = "pci", 2528 "link_down"; 2529 2530 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2531 2532 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 2533 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 2534 2535 operating-points-v2 = <&pcie1_opp_table>; 2536 2537 status = "disabled"; 2538 2539 pcie1_opp_table: opp-table { 2540 compatible = "operating-points-v2"; 2541 2542 /* GEN 1 x1 */ 2543 opp-2500000 { 2544 opp-hz = /bits/ 64 <2500000>; 2545 required-opps = <&rpmhpd_opp_svs_l1>; 2546 opp-peak-kBps = <250000 1>; 2547 }; 2548 2549 /* GEN 1 x2 and GEN 2 x1 */ 2550 opp-5000000 { 2551 opp-hz = /bits/ 64 <5000000>; 2552 required-opps = <&rpmhpd_opp_svs_l1>; 2553 opp-peak-kBps = <500000 1>; 2554 }; 2555 2556 /* GEN 1 x4 and GEN 2 x2 */ 2557 opp-10000000 { 2558 opp-hz = /bits/ 64 <10000000>; 2559 required-opps = <&rpmhpd_opp_svs_l1>; 2560 opp-peak-kBps = <1000000 1>; 2561 }; 2562 2563 /* GEN 2 x4 */ 2564 opp-20000000 { 2565 opp-hz = /bits/ 64 <20000000>; 2566 required-opps = <&rpmhpd_opp_low_svs>; 2567 opp-peak-kBps = <2000000 1>; 2568 }; 2569 2570 /* GEN 3 x1 */ 2571 opp-8000000 { 2572 opp-hz = /bits/ 64 <8000000>; 2573 required-opps = <&rpmhpd_opp_svs_l1>; 2574 opp-peak-kBps = <984500 1>; 2575 }; 2576 2577 /* GEN 3 x2 and GEN 4 x1 */ 2578 opp-16000000 { 2579 opp-hz = /bits/ 64 <16000000>; 2580 required-opps = <&rpmhpd_opp_nom>; 2581 opp-peak-kBps = <1969000 1>; 2582 }; 2583 2584 /* GEN 3 x4 and GEN 4 x2 */ 2585 opp-32000000 { 2586 opp-hz = /bits/ 64 <32000000>; 2587 required-opps = <&rpmhpd_opp_nom>; 2588 opp-peak-kBps = <3938000 1>; 2589 }; 2590 2591 /* GEN 4 x4 */ 2592 opp-64000000 { 2593 opp-hz = /bits/ 64 <64000000>; 2594 required-opps = <&rpmhpd_opp_nom>; 2595 opp-peak-kBps = <7876000 1>; 2596 }; 2597 }; 2598 2599 pcieport1: pcie@0 { 2600 device_type = "pci"; 2601 reg = <0x0 0x0 0x0 0x0 0x0>; 2602 bus-range = <0x01 0xff>; 2603 2604 #address-cells = <3>; 2605 #size-cells = <2>; 2606 ranges; 2607 phys = <&pcie1_phy>; 2608 }; 2609 }; 2610 2611 pcie1_phy: phy@1c14000 { 2612 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; 2613 reg = <0x0 0x01c14000 0x0 0x4000>; 2614 2615 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 2616 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2617 <&gcc GCC_PCIE_CLKREF_EN>, 2618 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 2619 <&gcc GCC_PCIE_1_PIPE_CLK>, 2620 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; 2621 clock-names = "aux", 2622 "cfg_ahb", 2623 "ref", 2624 "rchng", 2625 "pipe", 2626 "pipediv2"; 2627 2628 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 2629 assigned-clock-rates = <100000000>; 2630 2631 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2632 reset-names = "phy"; 2633 2634 #clock-cells = <0>; 2635 clock-output-names = "pcie_1_pipe_clk"; 2636 2637 #phy-cells = <0>; 2638 2639 status = "disabled"; 2640 }; 2641 2642 ufs_mem_hc: ufs@1d84000 { 2643 compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 2644 reg = <0x0 0x01d84000 0x0 0x3000>; 2645 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2646 phys = <&ufs_mem_phy>; 2647 phy-names = "ufsphy"; 2648 lanes-per-direction = <2>; 2649 #reset-cells = <1>; 2650 resets = <&gcc GCC_UFS_PHY_BCR>; 2651 reset-names = "rst"; 2652 2653 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2654 required-opps = <&rpmhpd_opp_nom>; 2655 2656 iommus = <&apps_smmu 0x100 0x0>; 2657 dma-coherent; 2658 2659 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2660 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2661 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2662 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2663 interconnect-names = "ufs-ddr", 2664 "cpu-ufs"; 2665 2666 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2667 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2668 <&gcc GCC_UFS_PHY_AHB_CLK>, 2669 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2670 <&rpmhcc RPMH_CXO_CLK>, 2671 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2672 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2673 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2674 clock-names = "core_clk", 2675 "bus_aggr_clk", 2676 "iface_clk", 2677 "core_clk_unipro", 2678 "ref_clk", 2679 "tx_lane0_sync_clk", 2680 "rx_lane0_sync_clk", 2681 "rx_lane1_sync_clk"; 2682 freq-table-hz = <75000000 300000000>, 2683 <0 0>, 2684 <0 0>, 2685 <75000000 300000000>, 2686 <0 0>, 2687 <0 0>, 2688 <0 0>, 2689 <0 0>; 2690 qcom,ice = <&ice>; 2691 status = "disabled"; 2692 }; 2693 2694 ufs_mem_phy: phy@1d87000 { 2695 compatible = "qcom,qcs8300-qmp-ufs-phy", "qcom,sa8775p-qmp-ufs-phy"; 2696 reg = <0x0 0x01d87000 0x0 0xe10>; 2697 /* 2698 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 2699 * enables the CXO clock to eDP *and* UFS PHY. 2700 */ 2701 clocks = <&rpmhcc RPMH_CXO_CLK>, 2702 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2703 <&gcc GCC_EDP_REF_CLKREF_EN>; 2704 clock-names = "ref", 2705 "ref_aux", 2706 "qref"; 2707 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2708 2709 resets = <&ufs_mem_hc 0>; 2710 reset-names = "ufsphy"; 2711 2712 #phy-cells = <0>; 2713 status = "disabled"; 2714 }; 2715 2716 cryptobam: dma-controller@1dc4000 { 2717 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2718 reg = <0x0 0x01dc4000 0x0 0x28000>; 2719 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2720 #dma-cells = <1>; 2721 qcom,ee = <0>; 2722 qcom,controlled-remotely; 2723 num-channels = <20>; 2724 qcom,num-ees = <4>; 2725 iommus = <&apps_smmu 0x480 0x00>, 2726 <&apps_smmu 0x481 0x00>; 2727 }; 2728 2729 ice: crypto@1d88000 { 2730 compatible = "qcom,qcs8300-inline-crypto-engine", 2731 "qcom,inline-crypto-engine"; 2732 reg = <0x0 0x01d88000 0x0 0x18000>; 2733 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2734 }; 2735 2736 crypto: crypto@1dfa000 { 2737 compatible = "qcom,qcs8300-qce", "qcom,sm8150-qce", "qcom,qce"; 2738 reg = <0x0 0x01dfa000 0x0 0x6000>; 2739 dmas = <&cryptobam 4>, <&cryptobam 5>; 2740 dma-names = "rx", "tx"; 2741 iommus = <&apps_smmu 0x480 0x0>, 2742 <&apps_smmu 0x481 0x0>; 2743 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS 2744 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2745 interconnect-names = "memory"; 2746 }; 2747 2748 tcsr_mutex: hwlock@1f40000 { 2749 compatible = "qcom,tcsr-mutex"; 2750 reg = <0x0 0x01f40000 0x0 0x20000>; 2751 #hwlock-cells = <1>; 2752 }; 2753 2754 tcsr: syscon@1fc0000 { 2755 compatible = "qcom,qcs8300-tcsr", "syscon"; 2756 reg = <0x0 0x1fc0000 0x0 0x30000>; 2757 }; 2758 2759 remoteproc_adsp: remoteproc@3000000 { 2760 compatible = "qcom,qcs8300-adsp-pas", "qcom,sa8775p-adsp-pas"; 2761 reg = <0x0 0x3000000 0x0 0x00100>; 2762 2763 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2764 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2765 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2766 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2767 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2768 interrupt-names = "wdog", 2769 "fatal", 2770 "ready", 2771 "handover", 2772 "stop-ack"; 2773 2774 clocks = <&rpmhcc RPMH_CXO_CLK>; 2775 clock-names = "xo"; 2776 2777 power-domains = <&rpmhpd RPMHPD_LCX>, 2778 <&rpmhpd RPMHPD_LMX>; 2779 power-domain-names = "lcx", 2780 "lmx"; 2781 2782 memory-region = <&adsp_mem>; 2783 2784 qcom,qmp = <&aoss_qmp>; 2785 2786 qcom,smem-states = <&smp2p_adsp_out 0>; 2787 qcom,smem-state-names = "stop"; 2788 2789 status = "disabled"; 2790 2791 remoteproc_adsp_glink: glink-edge { 2792 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2793 IPCC_MPROC_SIGNAL_GLINK_QMP 2794 IRQ_TYPE_EDGE_RISING>; 2795 mboxes = <&ipcc IPCC_CLIENT_LPASS 2796 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2797 2798 label = "lpass"; 2799 qcom,remote-pid = <2>; 2800 2801 fastrpc { 2802 compatible = "qcom,fastrpc"; 2803 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2804 label = "adsp"; 2805 memory-region = <&adsp_rpc_remote_heap_mem>; 2806 qcom,vmids = <QCOM_SCM_VMID_LPASS 2807 QCOM_SCM_VMID_ADSP_HEAP>; 2808 #address-cells = <1>; 2809 #size-cells = <0>; 2810 2811 compute-cb@3 { 2812 compatible = "qcom,fastrpc-compute-cb"; 2813 reg = <3>; 2814 iommus = <&apps_smmu 0x2003 0x0>; 2815 dma-coherent; 2816 }; 2817 2818 compute-cb@4 { 2819 compatible = "qcom,fastrpc-compute-cb"; 2820 reg = <4>; 2821 iommus = <&apps_smmu 0x2004 0x0>; 2822 dma-coherent; 2823 }; 2824 2825 compute-cb@5 { 2826 compatible = "qcom,fastrpc-compute-cb"; 2827 reg = <5>; 2828 iommus = <&apps_smmu 0x2005 0x0>; 2829 dma-coherent; 2830 }; 2831 }; 2832 2833 gpr { 2834 compatible = "qcom,gpr"; 2835 qcom,glink-channels = "adsp_apps"; 2836 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2837 qcom,intents = <512 20>; 2838 #address-cells = <1>; 2839 #size-cells = <0>; 2840 2841 q6apm: service@1 { 2842 compatible = "qcom,q6apm"; 2843 reg = <GPR_APM_MODULE_IID>; 2844 #sound-dai-cells = <0>; 2845 qcom,protection-domain = "avs/audio", 2846 "msm/adsp/audio_pd"; 2847 2848 q6apmbedai: bedais { 2849 compatible = "qcom,q6apm-lpass-dais"; 2850 #sound-dai-cells = <1>; 2851 }; 2852 2853 q6apmdai: dais { 2854 compatible = "qcom,q6apm-dais"; 2855 iommus = <&apps_smmu 0x2001 0x0>; 2856 }; 2857 }; 2858 2859 q6prm: service@2 { 2860 compatible = "qcom,q6prm"; 2861 reg = <GPR_PRM_MODULE_IID>; 2862 qcom,protection-domain = "avs/audio", 2863 "msm/adsp/audio_pd"; 2864 2865 q6prmcc: clock-controller { 2866 compatible = "qcom,q6prm-lpass-clocks"; 2867 #clock-cells = <2>; 2868 }; 2869 }; 2870 }; 2871 }; 2872 }; 2873 2874 lpass_ag_noc: interconnect@3c40000 { 2875 compatible = "qcom,qcs8300-lpass-ag-noc"; 2876 reg = <0x0 0x03c40000 0x0 0x17200>; 2877 #interconnect-cells = <2>; 2878 qcom,bcm-voters = <&apps_bcm_voter>; 2879 }; 2880 2881 ctcu@4001000 { 2882 compatible = "qcom,qcs8300-ctcu", "qcom,sa8775p-ctcu"; 2883 reg = <0x0 0x04001000 0x0 0x1000>; 2884 2885 clocks = <&aoss_qmp>; 2886 clock-names = "apb"; 2887 2888 in-ports { 2889 #address-cells = <1>; 2890 #size-cells = <0>; 2891 2892 port@0 { 2893 reg = <0>; 2894 2895 ctcu_in0: endpoint { 2896 remote-endpoint = <&etr0_out>; 2897 }; 2898 }; 2899 2900 port@1 { 2901 reg = <1>; 2902 2903 ctcu_in1: endpoint { 2904 remote-endpoint = <&etr1_out>; 2905 }; 2906 }; 2907 }; 2908 }; 2909 2910 stm@4002000 { 2911 compatible = "arm,coresight-stm", "arm,primecell"; 2912 reg = <0x0 0x04002000 0x0 0x1000>, 2913 <0x0 0x16280000 0x0 0x180000>; 2914 reg-names = "stm-base", 2915 "stm-stimulus-base"; 2916 2917 clocks = <&aoss_qmp>; 2918 clock-names = "apb_pclk"; 2919 2920 out-ports { 2921 port { 2922 stm_out: endpoint { 2923 remote-endpoint = <&funnel0_in7>; 2924 }; 2925 }; 2926 }; 2927 }; 2928 2929 tpda@4004000 { 2930 compatible = "qcom,coresight-tpda", "arm,primecell"; 2931 reg = <0x0 0x04004000 0x0 0x1000>; 2932 2933 clocks = <&aoss_qmp>; 2934 clock-names = "apb_pclk"; 2935 2936 in-ports { 2937 #address-cells = <1>; 2938 #size-cells = <0>; 2939 2940 port@0 { 2941 reg = <0>; 2942 2943 swao_rep_out0: endpoint { 2944 remote-endpoint = <&qdss_rep_in>; 2945 }; 2946 }; 2947 2948 port@1 { 2949 reg = <1>; 2950 2951 qdss_tpda_in1: endpoint { 2952 remote-endpoint = <&qdss_tpdm1_out>; 2953 }; 2954 }; 2955 }; 2956 2957 out-ports { 2958 port { 2959 qdss_tpda_out: endpoint { 2960 remote-endpoint = <&funnel0_in6>; 2961 }; 2962 }; 2963 }; 2964 }; 2965 2966 tpdm@400f000 { 2967 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2968 reg = <0x0 0x0400f000 0x0 0x1000>; 2969 2970 clocks = <&aoss_qmp>; 2971 clock-names = "apb_pclk"; 2972 2973 qcom,cmb-element-bits = <32>; 2974 qcom,cmb-msrs-num = <32>; 2975 2976 out-ports { 2977 port { 2978 qdss_tpdm1_out: endpoint { 2979 remote-endpoint = <&qdss_tpda_in1>; 2980 }; 2981 }; 2982 }; 2983 }; 2984 2985 funnel@4041000 { 2986 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2987 reg = <0x0 0x04041000 0x0 0x1000>; 2988 2989 clocks = <&aoss_qmp>; 2990 clock-names = "apb_pclk"; 2991 2992 in-ports { 2993 #address-cells = <1>; 2994 #size-cells = <0>; 2995 2996 port@6 { 2997 reg = <6>; 2998 2999 funnel0_in6: endpoint { 3000 remote-endpoint = <&qdss_tpda_out>; 3001 }; 3002 }; 3003 3004 port@7 { 3005 reg = <7>; 3006 3007 funnel0_in7: endpoint { 3008 remote-endpoint = <&stm_out>; 3009 }; 3010 }; 3011 }; 3012 3013 out-ports { 3014 port { 3015 funnel0_out: endpoint { 3016 remote-endpoint = <&qdss_funnel_in0>; 3017 }; 3018 }; 3019 }; 3020 }; 3021 3022 funnel@4042000 { 3023 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3024 reg = <0x0 0x04042000 0x0 0x1000>; 3025 3026 clocks = <&aoss_qmp>; 3027 clock-names = "apb_pclk"; 3028 3029 in-ports { 3030 #address-cells = <1>; 3031 #size-cells = <0>; 3032 3033 port@4 { 3034 reg = <4>; 3035 3036 funnel1_in4: endpoint { 3037 remote-endpoint = <&apss_funnel1_out>; 3038 }; 3039 }; 3040 3041 port@5 { 3042 reg = <5>; 3043 3044 funnel1_in5: endpoint { 3045 remote-endpoint = <&dlct0_funnel_out>; 3046 }; 3047 }; 3048 3049 port@6 { 3050 reg = <6>; 3051 3052 funnel1_in6: endpoint { 3053 remote-endpoint = <&dlmm_funnel_out>; 3054 }; 3055 }; 3056 3057 port@7 { 3058 reg = <7>; 3059 3060 funnel1_in7: endpoint { 3061 remote-endpoint = <&dlst_ch_funnel_out>; 3062 }; 3063 }; 3064 }; 3065 3066 out-ports { 3067 port { 3068 funnel1_out: endpoint { 3069 remote-endpoint = <&qdss_funnel_in1>; 3070 }; 3071 }; 3072 }; 3073 }; 3074 3075 funnel@4045000 { 3076 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3077 reg = <0x0 0x04045000 0x0 0x1000>; 3078 3079 clocks = <&aoss_qmp>; 3080 clock-names = "apb_pclk"; 3081 3082 in-ports { 3083 #address-cells = <1>; 3084 #size-cells = <0>; 3085 3086 port@0 { 3087 reg = <0>; 3088 3089 qdss_funnel_in0: endpoint { 3090 remote-endpoint = <&funnel0_out>; 3091 }; 3092 }; 3093 3094 port@1 { 3095 reg = <1>; 3096 3097 qdss_funnel_in1: endpoint { 3098 remote-endpoint = <&funnel1_out>; 3099 }; 3100 }; 3101 }; 3102 3103 out-ports { 3104 port { 3105 qdss_funnel_out: endpoint { 3106 remote-endpoint = <&aoss_funnel_in7>; 3107 }; 3108 }; 3109 }; 3110 }; 3111 3112 replicator@4046000 { 3113 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3114 reg = <0x0 0x04046000 0x0 0x1000>; 3115 3116 clocks = <&aoss_qmp>; 3117 clock-names = "apb_pclk"; 3118 3119 in-ports { 3120 port { 3121 qdss_rep_in: endpoint { 3122 remote-endpoint = <&swao_rep_out0>; 3123 }; 3124 }; 3125 }; 3126 3127 out-ports { 3128 port { 3129 qdss_rep_out0: endpoint { 3130 remote-endpoint = <&etr_rep_in>; 3131 }; 3132 }; 3133 }; 3134 }; 3135 3136 tmc@4048000 { 3137 compatible = "arm,coresight-tmc", "arm,primecell"; 3138 reg = <0x0 0x04048000 0x0 0x1000>; 3139 3140 clocks = <&aoss_qmp>; 3141 clock-names = "apb_pclk"; 3142 iommus = <&apps_smmu 0x04c0 0x00>; 3143 3144 arm,scatter-gather; 3145 3146 in-ports { 3147 port { 3148 etr0_in: endpoint { 3149 remote-endpoint = <&etr_rep_out0>; 3150 }; 3151 }; 3152 }; 3153 3154 out-ports { 3155 port { 3156 etr0_out: endpoint { 3157 remote-endpoint = <&ctcu_in0>; 3158 }; 3159 }; 3160 }; 3161 }; 3162 3163 replicator@404e000 { 3164 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3165 reg = <0x0 0x0404e000 0x0 0x1000>; 3166 3167 clocks = <&aoss_qmp>; 3168 clock-names = "apb_pclk"; 3169 3170 in-ports { 3171 port { 3172 etr_rep_in: endpoint { 3173 remote-endpoint = <&qdss_rep_out0>; 3174 }; 3175 }; 3176 }; 3177 3178 out-ports { 3179 #address-cells = <1>; 3180 #size-cells = <0>; 3181 3182 port@0 { 3183 reg = <0>; 3184 3185 etr_rep_out0: endpoint { 3186 remote-endpoint = <&etr0_in>; 3187 }; 3188 }; 3189 3190 port@1 { 3191 reg = <1>; 3192 3193 etr_rep_out1: endpoint { 3194 remote-endpoint = <&etr1_in>; 3195 }; 3196 }; 3197 }; 3198 }; 3199 3200 tmc@404f000 { 3201 compatible = "arm,coresight-tmc", "arm,primecell"; 3202 reg = <0x0 0x0404f000 0x0 0x1000>; 3203 3204 clocks = <&aoss_qmp>; 3205 clock-names = "apb_pclk"; 3206 iommus = <&apps_smmu 0x04a0 0x40>; 3207 3208 arm,scatter-gather; 3209 arm,buffer-size = <0x400000>; 3210 3211 in-ports { 3212 port { 3213 etr1_in: endpoint { 3214 remote-endpoint = <&etr_rep_out1>; 3215 }; 3216 }; 3217 }; 3218 3219 out-ports { 3220 port { 3221 etr1_out: endpoint { 3222 remote-endpoint = <&ctcu_in1>; 3223 }; 3224 }; 3225 }; 3226 }; 3227 3228 tpdm@4841000 { 3229 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3230 reg = <0x0 0x04841000 0x0 0x1000>; 3231 3232 clocks = <&aoss_qmp>; 3233 clock-names = "apb_pclk"; 3234 3235 qcom,cmb-element-bits = <32>; 3236 qcom,cmb-msrs-num = <32>; 3237 3238 out-ports { 3239 port { 3240 prng_tpdm_out: endpoint { 3241 remote-endpoint = <&dlct0_tpda_in19>; 3242 }; 3243 }; 3244 }; 3245 }; 3246 3247 tpdm@4850000 { 3248 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3249 reg = <0x0 0x04850000 0x0 0x1000>; 3250 3251 clocks = <&aoss_qmp>; 3252 clock-names = "apb_pclk"; 3253 3254 qcom,cmb-element-bits = <64>; 3255 qcom,cmb-msrs-num = <32>; 3256 qcom,dsb-element-bits = <32>; 3257 qcom,dsb-msrs-num = <32>; 3258 3259 out-ports { 3260 port { 3261 pimem_tpdm_out: endpoint { 3262 remote-endpoint = <&dlct0_tpda_in25>; 3263 }; 3264 }; 3265 }; 3266 }; 3267 3268 tpdm@4860000 { 3269 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3270 reg = <0x0 0x04860000 0x0 0x1000>; 3271 3272 clocks = <&aoss_qmp>; 3273 clock-names = "apb_pclk"; 3274 3275 qcom,dsb-element-bits = <32>; 3276 qcom,dsb-msrs-num = <32>; 3277 3278 out-ports { 3279 port { 3280 dlst_ch_tpdm0_out: endpoint { 3281 remote-endpoint = <&dlst_ch_tpda_in8>; 3282 }; 3283 }; 3284 }; 3285 }; 3286 3287 tpda@4864000 { 3288 compatible = "qcom,coresight-tpda", "arm,primecell"; 3289 reg = <0x0 0x04864000 0x0 0x1000>; 3290 3291 clocks = <&aoss_qmp>; 3292 clock-names = "apb_pclk"; 3293 3294 in-ports { 3295 #address-cells = <1>; 3296 #size-cells = <0>; 3297 3298 port@8 { 3299 reg = <8>; 3300 3301 dlst_ch_tpda_in8: endpoint { 3302 remote-endpoint = <&dlst_ch_tpdm0_out>; 3303 }; 3304 }; 3305 }; 3306 3307 out-ports { 3308 port { 3309 dlst_ch_tpda_out: endpoint { 3310 remote-endpoint = <&dlst_ch_funnel_in0>; 3311 }; 3312 }; 3313 }; 3314 }; 3315 3316 funnel@4865000 { 3317 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3318 reg = <0x0 0x04865000 0x0 0x1000>; 3319 3320 clocks = <&aoss_qmp>; 3321 clock-names = "apb_pclk"; 3322 3323 in-ports { 3324 #address-cells = <1>; 3325 #size-cells = <0>; 3326 3327 port@0 { 3328 reg = <0>; 3329 3330 dlst_ch_funnel_in0: endpoint { 3331 remote-endpoint = <&dlst_ch_tpda_out>; 3332 }; 3333 }; 3334 3335 port@4 { 3336 reg = <4>; 3337 3338 dlst_ch_funnel_in4: endpoint { 3339 remote-endpoint = <&dlst_funnel_out>; 3340 }; 3341 }; 3342 3343 port@6 { 3344 reg = <6>; 3345 3346 dlst_ch_funnel_in6: endpoint { 3347 remote-endpoint = <&gdsp_funnel_out>; 3348 }; 3349 }; 3350 }; 3351 3352 out-ports { 3353 port { 3354 dlst_ch_funnel_out: endpoint { 3355 remote-endpoint = <&funnel1_in7>; 3356 }; 3357 }; 3358 }; 3359 }; 3360 3361 tpdm@4980000 { 3362 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3363 reg = <0x0 0x04980000 0x0 0x1000>; 3364 3365 clocks = <&aoss_qmp>; 3366 clock-names = "apb_pclk"; 3367 3368 qcom,dsb-element-bits = <32>; 3369 qcom,dsb-msrs-num = <32>; 3370 3371 out-ports { 3372 port { 3373 turing2_tpdm_out: endpoint { 3374 remote-endpoint = <&turing2_funnel_in0>; 3375 }; 3376 }; 3377 }; 3378 }; 3379 3380 funnel@4983000 { 3381 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3382 reg = <0x0 0x04983000 0x0 0x1000>; 3383 3384 clocks = <&aoss_qmp>; 3385 clock-names = "apb_pclk"; 3386 3387 in-ports { 3388 port { 3389 turing2_funnel_in0: endpoint { 3390 remote-endpoint = <&turing2_tpdm_out>; 3391 }; 3392 }; 3393 }; 3394 3395 out-ports { 3396 port { 3397 turing2_funnel_out0: endpoint { 3398 remote-endpoint = <&gdsp_tpda_in5>; 3399 }; 3400 }; 3401 }; 3402 }; 3403 3404 tpdm@4ac0000 { 3405 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3406 reg = <0x0 0x04ac0000 0x0 0x1000>; 3407 3408 clocks = <&aoss_qmp>; 3409 clock-names = "apb_pclk"; 3410 3411 qcom,dsb-element-bits = <32>; 3412 qcom,dsb-msrs-num = <32>; 3413 3414 out-ports { 3415 port { 3416 dlmm_tpdm0_out: endpoint { 3417 remote-endpoint = <&dlmm_tpda_in27>; 3418 }; 3419 }; 3420 }; 3421 }; 3422 3423 tpda@4ac4000 { 3424 compatible = "qcom,coresight-tpda", "arm,primecell"; 3425 reg = <0x0 0x04ac4000 0x0 0x1000>; 3426 3427 clocks = <&aoss_qmp>; 3428 clock-names = "apb_pclk"; 3429 3430 in-ports { 3431 #address-cells = <1>; 3432 #size-cells = <0>; 3433 3434 port@1b { 3435 reg = <27>; 3436 3437 dlmm_tpda_in27: endpoint { 3438 remote-endpoint = <&dlmm_tpdm0_out>; 3439 }; 3440 }; 3441 }; 3442 3443 out-ports { 3444 port { 3445 dlmm_tpda_out: endpoint { 3446 remote-endpoint = <&dlmm_funnel_in0>; 3447 }; 3448 }; 3449 }; 3450 }; 3451 3452 funnel@4ac5000 { 3453 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3454 reg = <0x0 0x04ac5000 0x0 0x1000>; 3455 3456 clocks = <&aoss_qmp>; 3457 clock-names = "apb_pclk"; 3458 3459 in-ports { 3460 port { 3461 dlmm_funnel_in0: endpoint { 3462 remote-endpoint = <&dlmm_tpda_out>; 3463 }; 3464 }; 3465 }; 3466 3467 out-ports { 3468 port { 3469 dlmm_funnel_out: endpoint { 3470 remote-endpoint = <&funnel1_in6>; 3471 }; 3472 }; 3473 }; 3474 }; 3475 3476 tpdm@4ad0000 { 3477 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3478 reg = <0x0 0x04ad0000 0x0 0x1000>; 3479 3480 clocks = <&aoss_qmp>; 3481 clock-names = "apb_pclk"; 3482 3483 qcom,dsb-element-bits = <32>; 3484 qcom,dsb-msrs-num = <32>; 3485 3486 out-ports { 3487 port { 3488 dlct0_tpdm0_out: endpoint { 3489 remote-endpoint = <&dlct0_tpda_in26>; 3490 }; 3491 }; 3492 }; 3493 }; 3494 3495 tpda@4ad3000 { 3496 compatible = "qcom,coresight-tpda", "arm,primecell"; 3497 reg = <0x0 0x04ad3000 0x0 0x1000>; 3498 3499 clocks = <&aoss_qmp>; 3500 clock-names = "apb_pclk"; 3501 3502 in-ports { 3503 #address-cells = <1>; 3504 #size-cells = <0>; 3505 3506 port@13 { 3507 reg = <19>; 3508 3509 dlct0_tpda_in19: endpoint { 3510 remote-endpoint = <&prng_tpdm_out>; 3511 }; 3512 }; 3513 3514 port@19 { 3515 reg = <25>; 3516 3517 dlct0_tpda_in25: endpoint { 3518 remote-endpoint = <&pimem_tpdm_out>; 3519 }; 3520 }; 3521 3522 port@1a { 3523 reg = <26>; 3524 3525 dlct0_tpda_in26: endpoint { 3526 remote-endpoint = <&dlct0_tpdm0_out>; 3527 }; 3528 }; 3529 }; 3530 3531 out-ports { 3532 port { 3533 dlct0_tpda_out: endpoint { 3534 remote-endpoint = <&dlct0_funnel_in0>; 3535 }; 3536 }; 3537 }; 3538 }; 3539 3540 funnel@4ad4000 { 3541 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3542 reg = <0x0 0x04ad4000 0x0 0x1000>; 3543 3544 clocks = <&aoss_qmp>; 3545 clock-names = "apb_pclk"; 3546 3547 in-ports { 3548 #address-cells = <1>; 3549 #size-cells = <0>; 3550 3551 port@0 { 3552 reg = <0>; 3553 3554 dlct0_funnel_in0: endpoint { 3555 remote-endpoint = <&dlct0_tpda_out>; 3556 }; 3557 }; 3558 3559 port@4 { 3560 reg = <4>; 3561 3562 dlct0_funnel_in4: endpoint { 3563 remote-endpoint = <&ddr_funnel5_out>; 3564 }; 3565 }; 3566 }; 3567 3568 out-ports { 3569 port { 3570 dlct0_funnel_out: endpoint { 3571 remote-endpoint = <&funnel1_in5>; 3572 }; 3573 }; 3574 }; 3575 }; 3576 3577 funnel@4b04000 { 3578 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3579 reg = <0x0 0x04b04000 0x0 0x1000>; 3580 3581 clocks = <&aoss_qmp>; 3582 clock-names = "apb_pclk"; 3583 3584 in-ports { 3585 #address-cells = <1>; 3586 #size-cells = <0>; 3587 3588 port@6 { 3589 reg = <6>; 3590 3591 aoss_funnel_in6: endpoint { 3592 remote-endpoint = <&aoss_tpda_out>; 3593 }; 3594 }; 3595 3596 port@7 { 3597 reg = <7>; 3598 3599 aoss_funnel_in7: endpoint { 3600 remote-endpoint = <&qdss_funnel_out>; 3601 }; 3602 }; 3603 }; 3604 3605 out-ports { 3606 port { 3607 aoss_funnel_out: endpoint { 3608 remote-endpoint = <&etf0_in>; 3609 }; 3610 }; 3611 }; 3612 }; 3613 3614 tmc_etf: tmc@4b05000 { 3615 compatible = "arm,coresight-tmc", "arm,primecell"; 3616 reg = <0x0 0x04b05000 0x0 0x1000>; 3617 3618 clocks = <&aoss_qmp>; 3619 clock-names = "apb_pclk"; 3620 3621 in-ports { 3622 port { 3623 etf0_in: endpoint { 3624 remote-endpoint = <&aoss_funnel_out>; 3625 }; 3626 }; 3627 }; 3628 3629 out-ports { 3630 port { 3631 etf0_out: endpoint { 3632 remote-endpoint = <&swao_rep_in>; 3633 }; 3634 }; 3635 }; 3636 }; 3637 3638 replicator@4b06000 { 3639 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3640 reg = <0x0 0x04b06000 0x0 0x1000>; 3641 3642 clocks = <&aoss_qmp>; 3643 clock-names = "apb_pclk"; 3644 3645 in-ports { 3646 port { 3647 swao_rep_in: endpoint { 3648 remote-endpoint = <&etf0_out>; 3649 }; 3650 }; 3651 }; 3652 3653 out-ports { 3654 #address-cells = <1>; 3655 #size-cells = <0>; 3656 3657 port@1 { 3658 reg = <1>; 3659 3660 swao_rep_out1: endpoint { 3661 remote-endpoint = <&eud_in>; 3662 }; 3663 }; 3664 }; 3665 }; 3666 3667 tpda@4b08000 { 3668 compatible = "qcom,coresight-tpda", "arm,primecell"; 3669 reg = <0x0 0x04b08000 0x0 0x1000>; 3670 3671 clocks = <&aoss_qmp>; 3672 clock-names = "apb_pclk"; 3673 3674 in-ports { 3675 #address-cells = <1>; 3676 #size-cells = <0>; 3677 3678 port@0 { 3679 reg = <0>; 3680 3681 aoss_tpda_in0: endpoint { 3682 remote-endpoint = <&aoss_tpdm0_out>; 3683 }; 3684 }; 3685 3686 port@1 { 3687 reg = <1>; 3688 3689 aoss_tpda_in1: endpoint { 3690 remote-endpoint = <&aoss_tpdm1_out>; 3691 }; 3692 }; 3693 3694 port@2 { 3695 reg = <2>; 3696 3697 aoss_tpda_in2: endpoint { 3698 remote-endpoint = <&aoss_tpdm2_out>; 3699 }; 3700 }; 3701 3702 port@3 { 3703 reg = <3>; 3704 3705 aoss_tpda_in3: endpoint { 3706 remote-endpoint = <&aoss_tpdm3_out>; 3707 }; 3708 }; 3709 3710 port@4 { 3711 reg = <4>; 3712 3713 aoss_tpda_in4: endpoint { 3714 remote-endpoint = <&aoss_tpdm4_out>; 3715 }; 3716 }; 3717 }; 3718 3719 out-ports { 3720 port { 3721 aoss_tpda_out: endpoint { 3722 remote-endpoint = <&aoss_funnel_in6>; 3723 }; 3724 }; 3725 }; 3726 }; 3727 3728 tpdm@4b09000 { 3729 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3730 reg = <0x0 0x04b09000 0x0 0x1000>; 3731 3732 clocks = <&aoss_qmp>; 3733 clock-names = "apb_pclk"; 3734 3735 qcom,cmb-element-bits = <64>; 3736 qcom,cmb-msrs-num = <32>; 3737 3738 out-ports { 3739 port { 3740 aoss_tpdm0_out: endpoint { 3741 remote-endpoint = <&aoss_tpda_in0>; 3742 }; 3743 }; 3744 }; 3745 }; 3746 3747 tpdm@4b0a000 { 3748 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3749 reg = <0x0 0x04b0a000 0x0 0x1000>; 3750 3751 clocks = <&aoss_qmp>; 3752 clock-names = "apb_pclk"; 3753 3754 qcom,cmb-element-bits = <64>; 3755 qcom,cmb-msrs-num = <32>; 3756 3757 out-ports { 3758 port { 3759 aoss_tpdm1_out: endpoint { 3760 remote-endpoint = <&aoss_tpda_in1>; 3761 }; 3762 }; 3763 }; 3764 }; 3765 3766 tpdm@4b0b000 { 3767 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3768 reg = <0x0 0x04b0b000 0x0 0x1000>; 3769 3770 clocks = <&aoss_qmp>; 3771 clock-names = "apb_pclk"; 3772 3773 qcom,cmb-element-bits = <64>; 3774 qcom,cmb-msrs-num = <32>; 3775 3776 out-ports { 3777 port { 3778 aoss_tpdm2_out: endpoint { 3779 remote-endpoint = <&aoss_tpda_in2>; 3780 }; 3781 }; 3782 }; 3783 }; 3784 3785 tpdm@4b0c000 { 3786 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3787 reg = <0x0 0x04b0c000 0x0 0x1000>; 3788 3789 clocks = <&aoss_qmp>; 3790 clock-names = "apb_pclk"; 3791 3792 qcom,cmb-element-bits = <64>; 3793 qcom,cmb-msrs-num = <32>; 3794 3795 out-ports { 3796 port { 3797 aoss_tpdm3_out: endpoint { 3798 remote-endpoint = <&aoss_tpda_in3>; 3799 }; 3800 }; 3801 }; 3802 }; 3803 3804 tpdm@4b0d000 { 3805 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3806 reg = <0x0 0x04b0d000 0x0 0x1000>; 3807 3808 clocks = <&aoss_qmp>; 3809 clock-names = "apb_pclk"; 3810 3811 qcom,dsb-element-bits = <32>; 3812 qcom,dsb-msrs-num = <32>; 3813 3814 out-ports { 3815 port { 3816 aoss_tpdm4_out: endpoint { 3817 remote-endpoint = <&aoss_tpda_in4>; 3818 }; 3819 }; 3820 }; 3821 }; 3822 3823 cti@4b13000 { 3824 compatible = "arm,coresight-cti", "arm,primecell"; 3825 reg = <0x0 0x04b13000 0x0 0x1000>; 3826 3827 clocks = <&aoss_qmp>; 3828 clock-names = "apb_pclk"; 3829 }; 3830 3831 tpdm@4b80000 { 3832 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3833 reg = <0x0 0x04b80000 0x0 0x1000>; 3834 3835 clocks = <&aoss_qmp>; 3836 clock-names = "apb_pclk"; 3837 3838 qcom,dsb-element-bits = <32>; 3839 qcom,dsb-msrs-num = <32>; 3840 3841 out-ports { 3842 port { 3843 turing0_tpdm0_out: endpoint { 3844 remote-endpoint = <&turing0_tpda_in0>; 3845 }; 3846 }; 3847 }; 3848 }; 3849 3850 tpda@4b86000 { 3851 compatible = "qcom,coresight-tpda", "arm,primecell"; 3852 reg = <0x0 0x04b86000 0x0 0x1000>; 3853 3854 clocks = <&aoss_qmp>; 3855 clock-names = "apb_pclk"; 3856 3857 in-ports { 3858 port { 3859 turing0_tpda_in0: endpoint { 3860 remote-endpoint = <&turing0_tpdm0_out>; 3861 }; 3862 }; 3863 }; 3864 3865 out-ports { 3866 port { 3867 turing0_tpda_out: endpoint { 3868 remote-endpoint = <&turing0_funnel_in0>; 3869 }; 3870 }; 3871 }; 3872 }; 3873 3874 funnel@4b87000 { 3875 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3876 reg = <0x0 0x04b87000 0x0 0x1000>; 3877 3878 clocks = <&aoss_qmp>; 3879 clock-names = "apb_pclk"; 3880 3881 in-ports { 3882 port { 3883 turing0_funnel_in0: endpoint { 3884 remote-endpoint = <&turing0_tpda_out>; 3885 }; 3886 }; 3887 }; 3888 3889 out-ports { 3890 port { 3891 turing0_funnel_out: endpoint { 3892 remote-endpoint = <&gdsp_funnel_in4>; 3893 }; 3894 }; 3895 }; 3896 }; 3897 3898 cti@4b8b000 { 3899 compatible = "arm,coresight-cti", "arm,primecell"; 3900 reg = <0x0 0x04b8b000 0x0 0x1000>; 3901 3902 clocks = <&aoss_qmp>; 3903 clock-names = "apb_pclk"; 3904 }; 3905 3906 tpdm@4c40000 { 3907 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3908 reg = <0x0 0x04c40000 0x0 0x1000>; 3909 3910 clocks = <&aoss_qmp>; 3911 clock-names = "apb_pclk"; 3912 3913 qcom,dsb-element-bits = <32>; 3914 qcom,dsb-msrs-num = <32>; 3915 3916 out-ports { 3917 port { 3918 gdsp_tpdm0_out: endpoint { 3919 remote-endpoint = <&gdsp_tpda_in8>; 3920 }; 3921 }; 3922 }; 3923 }; 3924 3925 tpda@4c44000 { 3926 compatible = "qcom,coresight-tpda", "arm,primecell"; 3927 reg = <0x0 0x04c44000 0x0 0x1000>; 3928 3929 clocks = <&aoss_qmp>; 3930 clock-names = "apb_pclk"; 3931 3932 in-ports { 3933 #address-cells = <1>; 3934 #size-cells = <0>; 3935 3936 port@5 { 3937 reg = <5>; 3938 3939 gdsp_tpda_in5: endpoint { 3940 remote-endpoint = <&turing2_funnel_out0>; 3941 }; 3942 }; 3943 3944 port@8 { 3945 reg = <8>; 3946 3947 gdsp_tpda_in8: endpoint { 3948 remote-endpoint = <&gdsp_tpdm0_out>; 3949 }; 3950 }; 3951 }; 3952 3953 out-ports { 3954 port { 3955 gdsp_tpda_out: endpoint { 3956 remote-endpoint = <&gdsp_funnel_in0>; 3957 }; 3958 }; 3959 }; 3960 }; 3961 3962 funnel@4c45000 { 3963 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3964 reg = <0x0 0x04c45000 0x0 0x1000>; 3965 3966 clocks = <&aoss_qmp>; 3967 clock-names = "apb_pclk"; 3968 3969 in-ports { 3970 #address-cells = <1>; 3971 #size-cells = <0>; 3972 3973 port@0 { 3974 reg = <0>; 3975 3976 gdsp_funnel_in0: endpoint { 3977 remote-endpoint = <&gdsp_tpda_out>; 3978 }; 3979 }; 3980 3981 port@4 { 3982 reg = <4>; 3983 3984 gdsp_funnel_in4: endpoint { 3985 remote-endpoint = <&turing0_funnel_out>; 3986 }; 3987 }; 3988 }; 3989 3990 out-ports { 3991 port { 3992 gdsp_funnel_out: endpoint { 3993 remote-endpoint = <&dlst_ch_funnel_in6>; 3994 }; 3995 }; 3996 }; 3997 }; 3998 3999 tpdm@4c50000 { 4000 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4001 reg = <0x0 0x04c50000 0x0 0x1000>; 4002 4003 clocks = <&aoss_qmp>; 4004 clock-names = "apb_pclk"; 4005 4006 qcom,dsb-element-bits = <32>; 4007 qcom,dsb-msrs-num = <32>; 4008 4009 out-ports { 4010 port { 4011 dlst_tpdm0_out: endpoint { 4012 remote-endpoint = <&dlst_tpda_in8>; 4013 }; 4014 }; 4015 }; 4016 }; 4017 4018 tpda@4c54000 { 4019 compatible = "qcom,coresight-tpda", "arm,primecell"; 4020 reg = <0x0 0x04c54000 0x0 0x1000>; 4021 4022 clocks = <&aoss_qmp>; 4023 clock-names = "apb_pclk"; 4024 4025 in-ports { 4026 #address-cells = <1>; 4027 #size-cells = <0>; 4028 4029 port@8 { 4030 reg = <8>; 4031 4032 dlst_tpda_in8: endpoint { 4033 remote-endpoint = <&dlst_tpdm0_out>; 4034 }; 4035 }; 4036 }; 4037 4038 out-ports { 4039 port { 4040 dlst_tpda_out: endpoint { 4041 remote-endpoint = <&dlst_funnel_in0>; 4042 }; 4043 }; 4044 }; 4045 }; 4046 4047 funnel@4c55000 { 4048 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4049 reg = <0x0 0x04c55000 0x0 0x1000>; 4050 4051 clocks = <&aoss_qmp>; 4052 clock-names = "apb_pclk"; 4053 4054 in-ports { 4055 port { 4056 dlst_funnel_in0: endpoint { 4057 remote-endpoint = <&dlst_tpda_out>; 4058 }; 4059 }; 4060 }; 4061 4062 out-ports { 4063 port { 4064 dlst_funnel_out: endpoint { 4065 remote-endpoint = <&dlst_ch_funnel_in4>; 4066 }; 4067 }; 4068 }; 4069 }; 4070 4071 tpdm@4e00000 { 4072 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4073 reg = <0x0 0x04e00000 0x0 0x1000>; 4074 4075 clocks = <&aoss_qmp>; 4076 clock-names = "apb_pclk"; 4077 4078 qcom,dsb-element-bits = <32>; 4079 qcom,dsb-msrs-num = <32>; 4080 qcom,cmb-element-bits = <32>; 4081 qcom,cmb-msrs-num = <32>; 4082 4083 out-ports { 4084 port { 4085 ddr_tpdm3_out: endpoint { 4086 remote-endpoint = <&ddr_tpda_in4>; 4087 }; 4088 }; 4089 }; 4090 }; 4091 4092 tpda@4e03000 { 4093 compatible = "qcom,coresight-tpda", "arm,primecell"; 4094 reg = <0x0 0x04e03000 0x0 0x1000>; 4095 4096 clocks = <&aoss_qmp>; 4097 clock-names = "apb_pclk"; 4098 4099 in-ports { 4100 #address-cells = <1>; 4101 #size-cells = <0>; 4102 4103 port@0 { 4104 reg = <0>; 4105 4106 ddr_tpda_in0: endpoint { 4107 remote-endpoint = <&ddr_funnel0_out0>; 4108 }; 4109 }; 4110 4111 port@1 { 4112 reg = <1>; 4113 4114 ddr_tpda_in1: endpoint { 4115 remote-endpoint = <&ddr_funnel1_out0>; 4116 }; 4117 }; 4118 4119 port@4 { 4120 reg = <4>; 4121 4122 ddr_tpda_in4: endpoint { 4123 remote-endpoint = <&ddr_tpdm3_out>; 4124 }; 4125 }; 4126 }; 4127 4128 out-ports { 4129 port { 4130 ddr_tpda_out: endpoint { 4131 remote-endpoint = <&ddr_funnel5_in0>; 4132 }; 4133 }; 4134 }; 4135 }; 4136 4137 funnel@4e04000 { 4138 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4139 reg = <0x0 0x04e04000 0x0 0x1000>; 4140 4141 clocks = <&aoss_qmp>; 4142 clock-names = "apb_pclk"; 4143 4144 in-ports { 4145 port { 4146 ddr_funnel5_in0: endpoint { 4147 remote-endpoint = <&ddr_tpda_out>; 4148 }; 4149 }; 4150 }; 4151 4152 out-ports { 4153 port { 4154 ddr_funnel5_out: endpoint { 4155 remote-endpoint = <&dlct0_funnel_in4>; 4156 }; 4157 }; 4158 }; 4159 }; 4160 4161 tpdm@4e10000 { 4162 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4163 reg = <0x0 0x04e10000 0x0 0x1000>; 4164 4165 clocks = <&aoss_qmp>; 4166 clock-names = "apb_pclk"; 4167 4168 qcom,dsb-element-bits = <32>; 4169 qcom,dsb-msrs-num = <32>; 4170 4171 out-ports { 4172 port { 4173 ddr_tpdm0_out: endpoint { 4174 remote-endpoint = <&ddr_funnel0_in0>; 4175 }; 4176 }; 4177 }; 4178 }; 4179 4180 funnel@4e12000 { 4181 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4182 reg = <0x0 0x04e12000 0x0 0x1000>; 4183 4184 clocks = <&aoss_qmp>; 4185 clock-names = "apb_pclk"; 4186 4187 in-ports { 4188 port { 4189 ddr_funnel0_in0: endpoint { 4190 remote-endpoint = <&ddr_tpdm0_out>; 4191 }; 4192 }; 4193 }; 4194 4195 out-ports { 4196 port { 4197 ddr_funnel0_out0: endpoint { 4198 remote-endpoint = <&ddr_tpda_in0>; 4199 }; 4200 }; 4201 }; 4202 }; 4203 4204 tpdm@4e20000 { 4205 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4206 reg = <0x0 0x04e20000 0x0 0x1000>; 4207 4208 clocks = <&aoss_qmp>; 4209 clock-names = "apb_pclk"; 4210 4211 qcom,dsb-element-bits = <32>; 4212 qcom,dsb-msrs-num = <32>; 4213 4214 out-ports { 4215 port { 4216 ddr_tpdm1_out: endpoint { 4217 remote-endpoint = <&ddr_funnel1_in0>; 4218 }; 4219 }; 4220 }; 4221 }; 4222 4223 funnel@4e22000 { 4224 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4225 reg = <0x0 0x04e22000 0x0 0x1000>; 4226 4227 clocks = <&aoss_qmp>; 4228 clock-names = "apb_pclk"; 4229 4230 in-ports { 4231 port { 4232 ddr_funnel1_in0: endpoint { 4233 remote-endpoint = <&ddr_tpdm1_out>; 4234 }; 4235 }; 4236 }; 4237 4238 out-ports { 4239 port { 4240 ddr_funnel1_out0: endpoint { 4241 remote-endpoint = <&ddr_tpda_in1>; 4242 }; 4243 }; 4244 }; 4245 }; 4246 4247 etm@6040000 { 4248 compatible = "arm,primecell"; 4249 reg = <0x0 0x06040000 0x0 0x1000>; 4250 cpu = <&cpu0>; 4251 4252 clocks = <&aoss_qmp>; 4253 clock-names = "apb_pclk"; 4254 4255 arm,coresight-loses-context-with-cpu; 4256 qcom,skip-power-up; 4257 4258 out-ports { 4259 port { 4260 etm0_out: endpoint { 4261 remote-endpoint = <&apss_funnel0_in0>; 4262 }; 4263 }; 4264 }; 4265 }; 4266 4267 etm@6140000 { 4268 compatible = "arm,primecell"; 4269 reg = <0x0 0x06140000 0x0 0x1000>; 4270 cpu = <&cpu1>; 4271 4272 clocks = <&aoss_qmp>; 4273 clock-names = "apb_pclk"; 4274 4275 arm,coresight-loses-context-with-cpu; 4276 qcom,skip-power-up; 4277 4278 out-ports { 4279 port { 4280 etm1_out: endpoint { 4281 remote-endpoint = <&apss_funnel0_in1>; 4282 }; 4283 }; 4284 }; 4285 }; 4286 4287 etm@6240000 { 4288 compatible = "arm,primecell"; 4289 reg = <0x0 0x06240000 0x0 0x1000>; 4290 cpu = <&cpu2>; 4291 4292 clocks = <&aoss_qmp>; 4293 clock-names = "apb_pclk"; 4294 4295 arm,coresight-loses-context-with-cpu; 4296 qcom,skip-power-up; 4297 4298 out-ports { 4299 port { 4300 etm2_out: endpoint { 4301 remote-endpoint = <&apss_funnel0_in2>; 4302 }; 4303 }; 4304 }; 4305 }; 4306 4307 etm@6340000 { 4308 compatible = "arm,primecell"; 4309 reg = <0x0 0x06340000 0x0 0x1000>; 4310 cpu = <&cpu3>; 4311 4312 clocks = <&aoss_qmp>; 4313 clock-names = "apb_pclk"; 4314 4315 arm,coresight-loses-context-with-cpu; 4316 qcom,skip-power-up; 4317 4318 out-ports { 4319 port { 4320 etm3_out: endpoint { 4321 remote-endpoint = <&apss_funnel0_in3>; 4322 }; 4323 }; 4324 }; 4325 }; 4326 4327 etm@6440000 { 4328 compatible = "arm,primecell"; 4329 reg = <0x0 0x06440000 0x0 0x1000>; 4330 cpu = <&cpu4>; 4331 4332 clocks = <&aoss_qmp>; 4333 clock-names = "apb_pclk"; 4334 4335 arm,coresight-loses-context-with-cpu; 4336 qcom,skip-power-up; 4337 4338 out-ports { 4339 port { 4340 etm4_out: endpoint { 4341 remote-endpoint = <&apss_funnel0_in4>; 4342 }; 4343 }; 4344 }; 4345 }; 4346 4347 etm@6540000 { 4348 compatible = "arm,primecell"; 4349 reg = <0x0 0x06540000 0x0 0x1000>; 4350 cpu = <&cpu5>; 4351 4352 clocks = <&aoss_qmp>; 4353 clock-names = "apb_pclk"; 4354 4355 arm,coresight-loses-context-with-cpu; 4356 qcom,skip-power-up; 4357 4358 out-ports { 4359 port { 4360 etm5_out: endpoint { 4361 remote-endpoint = <&apss_funnel0_in5>; 4362 }; 4363 }; 4364 }; 4365 }; 4366 4367 etm@6640000 { 4368 compatible = "arm,primecell"; 4369 reg = <0x0 0x06640000 0x0 0x1000>; 4370 cpu = <&cpu6>; 4371 4372 clocks = <&aoss_qmp>; 4373 clock-names = "apb_pclk"; 4374 4375 arm,coresight-loses-context-with-cpu; 4376 qcom,skip-power-up; 4377 4378 out-ports { 4379 port { 4380 etm6_out: endpoint { 4381 remote-endpoint = <&apss_funnel0_in6>; 4382 }; 4383 }; 4384 }; 4385 }; 4386 4387 etm@6740000 { 4388 compatible = "arm,primecell"; 4389 reg = <0x0 0x06740000 0x0 0x1000>; 4390 cpu = <&cpu7>; 4391 4392 clocks = <&aoss_qmp>; 4393 clock-names = "apb_pclk"; 4394 4395 arm,coresight-loses-context-with-cpu; 4396 qcom,skip-power-up; 4397 4398 out-ports { 4399 port { 4400 etm7_out: endpoint { 4401 remote-endpoint = <&apss_funnel0_in7>; 4402 }; 4403 }; 4404 }; 4405 }; 4406 4407 funnel@6800000 { 4408 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4409 reg = <0x0 0x06800000 0x0 0x1000>; 4410 4411 clocks = <&aoss_qmp>; 4412 clock-names = "apb_pclk"; 4413 4414 in-ports { 4415 #address-cells = <1>; 4416 #size-cells = <0>; 4417 4418 port@0 { 4419 reg = <0>; 4420 4421 apss_funnel0_in0: endpoint { 4422 remote-endpoint = <&etm0_out>; 4423 }; 4424 }; 4425 4426 port@1 { 4427 reg = <1>; 4428 4429 apss_funnel0_in1: endpoint { 4430 remote-endpoint = <&etm1_out>; 4431 }; 4432 }; 4433 4434 port@2 { 4435 reg = <2>; 4436 4437 apss_funnel0_in2: endpoint { 4438 remote-endpoint = <&etm2_out>; 4439 }; 4440 }; 4441 4442 port@3 { 4443 reg = <3>; 4444 4445 apss_funnel0_in3: endpoint { 4446 remote-endpoint = <&etm3_out>; 4447 }; 4448 }; 4449 4450 port@4 { 4451 reg = <4>; 4452 4453 apss_funnel0_in4: endpoint { 4454 remote-endpoint = <&etm4_out>; 4455 }; 4456 }; 4457 4458 port@5 { 4459 reg = <5>; 4460 4461 apss_funnel0_in5: endpoint { 4462 remote-endpoint = <&etm5_out>; 4463 }; 4464 }; 4465 4466 port@6 { 4467 reg = <6>; 4468 4469 apss_funnel0_in6: endpoint { 4470 remote-endpoint = <&etm6_out>; 4471 }; 4472 }; 4473 4474 port@7 { 4475 reg = <7>; 4476 4477 apss_funnel0_in7: endpoint { 4478 remote-endpoint = <&etm7_out>; 4479 }; 4480 }; 4481 }; 4482 4483 out-ports { 4484 port { 4485 apss_funnel0_out: endpoint { 4486 remote-endpoint = <&apss_funnel1_in0>; 4487 }; 4488 }; 4489 }; 4490 }; 4491 4492 funnel@6810000 { 4493 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4494 reg = <0x0 0x06810000 0x0 0x1000>; 4495 4496 clocks = <&aoss_qmp>; 4497 clock-names = "apb_pclk"; 4498 4499 in-ports { 4500 #address-cells = <1>; 4501 #size-cells = <0>; 4502 4503 port@0 { 4504 reg = <0>; 4505 4506 apss_funnel1_in0: endpoint { 4507 remote-endpoint = <&apss_funnel0_out>; 4508 }; 4509 }; 4510 4511 port@3 { 4512 reg = <3>; 4513 4514 apss_funnel1_in3: endpoint { 4515 remote-endpoint = <&apss_tpda_out>; 4516 }; 4517 }; 4518 }; 4519 4520 out-ports { 4521 port { 4522 apss_funnel1_out: endpoint { 4523 remote-endpoint = <&funnel1_in4>; 4524 }; 4525 }; 4526 }; 4527 }; 4528 4529 cti@682b000 { 4530 compatible = "arm,coresight-cti", "arm,primecell"; 4531 reg = <0x0 0x0682b000 0x0 0x1000>; 4532 4533 clocks = <&aoss_qmp>; 4534 clock-names = "apb_pclk"; 4535 }; 4536 4537 tpdm@6860000 { 4538 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4539 reg = <0x0 0x06860000 0x0 0x1000>; 4540 4541 clocks = <&aoss_qmp>; 4542 clock-names = "apb_pclk"; 4543 4544 qcom,cmb-element-bits = <64>; 4545 qcom,cmb-msrs-num = <32>; 4546 4547 out-ports { 4548 port { 4549 apss_tpdm3_out: endpoint { 4550 remote-endpoint = <&apss_tpda_in3>; 4551 }; 4552 }; 4553 }; 4554 }; 4555 4556 tpdm@6861000 { 4557 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4558 reg = <0x0 0x06861000 0x0 0x1000>; 4559 4560 clocks = <&aoss_qmp>; 4561 clock-names = "apb_pclk"; 4562 4563 qcom,dsb-element-bits = <32>; 4564 qcom,dsb-msrs-num = <32>; 4565 4566 out-ports { 4567 port { 4568 apss_tpdm4_out: endpoint { 4569 remote-endpoint = <&apss_tpda_in4>; 4570 }; 4571 }; 4572 }; 4573 }; 4574 4575 tpda@6863000 { 4576 compatible = "qcom,coresight-tpda", "arm,primecell"; 4577 reg = <0x0 0x06863000 0x0 0x1000>; 4578 4579 clocks = <&aoss_qmp>; 4580 clock-names = "apb_pclk"; 4581 4582 in-ports { 4583 #address-cells = <1>; 4584 #size-cells = <0>; 4585 4586 port@0 { 4587 reg = <0>; 4588 4589 apss_tpda_in0: endpoint { 4590 remote-endpoint = <&apss_tpdm0_out>; 4591 }; 4592 }; 4593 4594 port@1 { 4595 reg = <1>; 4596 4597 apss_tpda_in1: endpoint { 4598 remote-endpoint = <&apss_tpdm1_out>; 4599 }; 4600 }; 4601 4602 port@2 { 4603 reg = <2>; 4604 4605 apss_tpda_in2: endpoint { 4606 remote-endpoint = <&apss_tpdm2_out>; 4607 }; 4608 }; 4609 4610 port@3 { 4611 reg = <3>; 4612 4613 apss_tpda_in3: endpoint { 4614 remote-endpoint = <&apss_tpdm3_out>; 4615 }; 4616 }; 4617 4618 port@4 { 4619 reg = <4>; 4620 4621 apss_tpda_in4: endpoint { 4622 remote-endpoint = <&apss_tpdm4_out>; 4623 }; 4624 }; 4625 }; 4626 4627 out-ports { 4628 port { 4629 apss_tpda_out: endpoint { 4630 remote-endpoint = <&apss_funnel1_in3>; 4631 }; 4632 }; 4633 }; 4634 }; 4635 4636 tpdm@68a0000 { 4637 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4638 reg = <0x0 0x068a0000 0x0 0x1000>; 4639 4640 clocks = <&aoss_qmp>; 4641 clock-names = "apb_pclk"; 4642 4643 qcom,cmb-element-bits = <32>; 4644 qcom,cmb-msrs-num = <32>; 4645 4646 out-ports { 4647 port { 4648 apss_tpdm1_out: endpoint { 4649 remote-endpoint = <&apss_tpda_in1>; 4650 }; 4651 }; 4652 }; 4653 }; 4654 4655 tpdm@68b0000 { 4656 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4657 reg = <0x0 0x068b0000 0x0 0x1000>; 4658 4659 clocks = <&aoss_qmp>; 4660 clock-names = "apb_pclk"; 4661 4662 qcom,cmb-element-bits = <32>; 4663 qcom,cmb-msrs-num = <32>; 4664 4665 out-ports { 4666 port { 4667 apss_tpdm0_out: endpoint { 4668 remote-endpoint = <&apss_tpda_in0>; 4669 }; 4670 }; 4671 }; 4672 }; 4673 4674 tpdm@68c0000 { 4675 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4676 reg = <0x0 0x068c0000 0x0 0x1000>; 4677 4678 clocks = <&aoss_qmp>; 4679 clock-names = "apb_pclk"; 4680 4681 qcom,dsb-element-bits = <32>; 4682 qcom,dsb-msrs-num = <32>; 4683 4684 out-ports { 4685 port { 4686 apss_tpdm2_out: endpoint { 4687 remote-endpoint = <&apss_tpda_in2>; 4688 }; 4689 }; 4690 }; 4691 }; 4692 4693 cti@68e0000 { 4694 compatible = "arm,coresight-cti", "arm,primecell"; 4695 reg = <0x0 0x068e0000 0x0 0x1000>; 4696 4697 clocks = <&aoss_qmp>; 4698 clock-names = "apb_pclk"; 4699 }; 4700 4701 cti@68f0000 { 4702 compatible = "arm,coresight-cti", "arm,primecell"; 4703 reg = <0x0 0x068f0000 0x0 0x1000>; 4704 4705 clocks = <&aoss_qmp>; 4706 clock-names = "apb_pclk"; 4707 }; 4708 4709 cti@6900000 { 4710 compatible = "arm,coresight-cti", "arm,primecell"; 4711 reg = <0x0 0x06900000 0x0 0x1000>; 4712 4713 clocks = <&aoss_qmp>; 4714 clock-names = "apb_pclk"; 4715 }; 4716 4717 sdhc_1: mmc@87c4000 { 4718 compatible = "qcom,qcs8300-sdhci", "qcom,sdhci-msm-v5"; 4719 reg = <0x0 0x087c4000 0x0 0x1000>, 4720 <0x0 0x087c5000 0x0 0x1000>; 4721 reg-names = "hc", 4722 "cqhci"; 4723 4724 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 4725 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>; 4726 interrupt-names = "hc_irq", 4727 "pwr_irq"; 4728 4729 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 4730 <&gcc GCC_SDCC1_APPS_CLK>, 4731 <&rpmhcc RPMH_CXO_CLK>; 4732 clock-names = "iface", 4733 "core", 4734 "xo"; 4735 4736 resets = <&gcc GCC_SDCC1_BCR>; 4737 4738 power-domains = <&rpmhpd RPMHPD_CX>; 4739 operating-points-v2 = <&sdhc1_opp_table>; 4740 iommus = <&apps_smmu 0x0 0x0>; 4741 interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS 4742 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4743 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4744 &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4745 interconnect-names = "sdhc-ddr", 4746 "cpu-sdhc"; 4747 4748 qcom,dll-config = <0x000f64ee>; 4749 qcom,ddr-config = <0x80040868>; 4750 supports-cqe; 4751 dma-coherent; 4752 4753 status = "disabled"; 4754 4755 sdhc1_opp_table: opp-table { 4756 compatible = "operating-points-v2"; 4757 4758 opp-50000000 { 4759 opp-hz = /bits/ 64 <50000000>; 4760 required-opps = <&rpmhpd_opp_low_svs>; 4761 }; 4762 4763 opp-100000000 { 4764 opp-hz = /bits/ 64 <100000000>; 4765 required-opps = <&rpmhpd_opp_svs>; 4766 }; 4767 4768 opp-200000000 { 4769 opp-hz = /bits/ 64 <200000000>; 4770 required-opps = <&rpmhpd_opp_svs_l1>; 4771 }; 4772 4773 opp-384000000 { 4774 opp-hz = /bits/ 64 <384000000>; 4775 required-opps = <&rpmhpd_opp_nom>; 4776 }; 4777 }; 4778 }; 4779 4780 usb_1_hsphy: phy@8904000 { 4781 compatible = "qcom,qcs8300-usb-hs-phy", 4782 "qcom,usb-snps-hs-7nm-phy"; 4783 reg = <0x0 0x08904000 0x0 0x400>; 4784 4785 clocks = <&rpmhcc RPMH_CXO_CLK>; 4786 clock-names = "ref"; 4787 4788 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 4789 4790 #phy-cells = <0>; 4791 4792 status = "disabled"; 4793 }; 4794 4795 usb_2_hsphy: phy@8906000 { 4796 compatible = "qcom,qcs8300-usb-hs-phy", 4797 "qcom,usb-snps-hs-7nm-phy"; 4798 reg = <0x0 0x08906000 0x0 0x400>; 4799 4800 clocks = <&rpmhcc RPMH_CXO_CLK>; 4801 clock-names = "ref"; 4802 4803 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 4804 4805 #phy-cells = <0>; 4806 4807 status = "disabled"; 4808 }; 4809 4810 usb_qmpphy: phy@8907000 { 4811 compatible = "qcom,qcs8300-qmp-usb3-uni-phy"; 4812 reg = <0x0 0x08907000 0x0 0x2000>; 4813 4814 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4815 <&gcc GCC_USB_CLKREF_EN>, 4816 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4817 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4818 clock-names = "aux", 4819 "ref", 4820 "com_aux", 4821 "pipe"; 4822 4823 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4824 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 4825 reset-names = "phy", "phy_phy"; 4826 4827 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4828 4829 #clock-cells = <0>; 4830 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 4831 4832 #phy-cells = <0>; 4833 4834 status = "disabled"; 4835 }; 4836 4837 serdes0: phy@8909000 { 4838 compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy"; 4839 reg = <0x0 0x08909000 0x0 0x00000e10>; 4840 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 4841 clock-names = "sgmi_ref"; 4842 #phy-cells = <0>; 4843 status = "disabled"; 4844 }; 4845 4846 refgen: regulator@891c000 { 4847 compatible = "qcom,qcs8300-refgen-regulator", 4848 "qcom,sm8250-refgen-regulator"; 4849 reg = <0x0 0x0891c000 0x0 0x84>; 4850 }; 4851 4852 gpu: gpu@3d00000 { 4853 compatible = "qcom,adreno-623.0", "qcom,adreno"; 4854 reg = <0x0 0x03d00000 0x0 0x40000>, 4855 <0x0 0x03d9e000 0x0 0x1000>, 4856 <0x0 0x03d61000 0x0 0x800>; 4857 reg-names = "kgsl_3d0_reg_memory", 4858 "cx_mem", 4859 "cx_dbgc"; 4860 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4861 iommus = <&adreno_smmu 0 0xc00>, 4862 <&adreno_smmu 1 0xc00>; 4863 operating-points-v2 = <&gpu_opp_table>; 4864 qcom,gmu = <&gmu>; 4865 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 4866 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4867 interconnect-names = "gfx-mem"; 4868 #cooling-cells = <2>; 4869 4870 nvmem-cells = <&gpu_speed_bin>; 4871 nvmem-cell-names = "speed_bin"; 4872 4873 status = "disabled"; 4874 4875 gpu_zap_shader: zap-shader { 4876 memory-region = <&gpu_microcode_mem>; 4877 }; 4878 4879 gpu_opp_table: opp-table { 4880 compatible = "operating-points-v2"; 4881 4882 opp-877000000 { 4883 opp-hz = /bits/ 64 <877000000>; 4884 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4885 opp-peak-kBps = <12484375>; 4886 opp-supported-hw = <0x1>; 4887 }; 4888 4889 opp-780000000 { 4890 opp-hz = /bits/ 64 <780000000>; 4891 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4892 opp-peak-kBps = <10687500>; 4893 opp-supported-hw = <0x1>; 4894 }; 4895 4896 opp-599000000 { 4897 opp-hz = /bits/ 64 <599000000>; 4898 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4899 opp-peak-kBps = <8171875>; 4900 opp-supported-hw = <0x3>; 4901 }; 4902 4903 opp-479000000 { 4904 opp-hz = /bits/ 64 <479000000>; 4905 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4906 opp-peak-kBps = <5285156>; 4907 opp-supported-hw = <0x3>; 4908 }; 4909 }; 4910 }; 4911 4912 gmu: gmu@3d6a000 { 4913 compatible = "qcom,adreno-gmu-623.0", "qcom,adreno-gmu"; 4914 reg = <0x0 0x03d6a000 0x0 0x34000>, 4915 <0x0 0x03de0000 0x0 0x10000>, 4916 <0x0 0x0b290000 0x0 0x10000>; 4917 reg-names = "gmu", "rscc", "gmu_pdc"; 4918 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4919 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4920 interrupt-names = "hfi", "gmu"; 4921 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4922 <&gpucc GPU_CC_CXO_CLK>, 4923 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4924 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4925 <&gpucc GPU_CC_AHB_CLK>, 4926 <&gpucc GPU_CC_HUB_CX_INT_CLK>; 4927 clock-names = "gmu", 4928 "cxo", 4929 "axi", 4930 "memnoc", 4931 "ahb", 4932 "hub"; 4933 power-domains = <&gpucc GPU_CC_CX_GDSC>, 4934 <&gpucc GPU_CC_GX_GDSC>; 4935 power-domain-names = "cx", 4936 "gx"; 4937 iommus = <&adreno_smmu 5 0xc00>; 4938 operating-points-v2 = <&gmu_opp_table>; 4939 4940 gmu_opp_table: opp-table { 4941 compatible = "operating-points-v2"; 4942 4943 opp-500000000 { 4944 opp-hz = /bits/ 64 <500000000>; 4945 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4946 }; 4947 }; 4948 }; 4949 4950 gpucc: clock-controller@3d90000 { 4951 compatible = "qcom,qcs8300-gpucc"; 4952 reg = <0x0 0x03d90000 0x0 0xa000>; 4953 clocks = <&rpmhcc RPMH_CXO_CLK>, 4954 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 4955 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 4956 clock-names = "bi_tcxo", 4957 "gcc_gpu_gpll0_clk_src", 4958 "gcc_gpu_gpll0_div_clk_src"; 4959 #clock-cells = <1>; 4960 #reset-cells = <1>; 4961 #power-domain-cells = <1>; 4962 }; 4963 4964 adreno_smmu: iommu@3da0000 { 4965 compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu", 4966 "qcom,smmu-500", "arm,mmu-500"; 4967 reg = <0x0 0x3da0000 0x0 0x20000>; 4968 #iommu-cells = <2>; 4969 #global-interrupts = <2>; 4970 4971 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 4972 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 4973 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 4974 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 4975 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 4976 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 4977 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 4978 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 4979 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 4980 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 4981 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 4982 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 4983 4984 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4985 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 4986 <&gpucc GPU_CC_AHB_CLK>, 4987 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 4988 <&gpucc GPU_CC_CX_GMU_CLK>, 4989 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4990 <&gpucc GPU_CC_HUB_AON_CLK>; 4991 4992 clock-names = "gcc_gpu_memnoc_gfx_clk", 4993 "gcc_gpu_snoc_dvm_gfx_clk", 4994 "gpu_cc_ahb_clk", 4995 "gpu_cc_hlos1_vote_gpu_smmu_clk", 4996 "gpu_cc_cx_gmu_clk", 4997 "gpu_cc_hub_cx_int_clk", 4998 "gpu_cc_hub_aon_clk"; 4999 power-domains = <&gpucc GPU_CC_CX_GDSC>; 5000 dma-coherent; 5001 }; 5002 5003 pmu@9091000 { 5004 compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 5005 reg = <0x0 0x9091000 0x0 0x1000>; 5006 5007 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>; 5008 5009 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 5010 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5011 5012 operating-points-v2 = <&llcc_bwmon_opp_table>; 5013 5014 llcc_bwmon_opp_table: opp-table { 5015 compatible = "operating-points-v2"; 5016 5017 opp-0 { 5018 opp-peak-kBps = <762000>; 5019 }; 5020 5021 opp-1 { 5022 opp-peak-kBps = <1720000>; 5023 }; 5024 5025 opp-2 { 5026 opp-peak-kBps = <2086000>; 5027 }; 5028 5029 opp-3 { 5030 opp-peak-kBps = <2601000>; 5031 }; 5032 5033 opp-4 { 5034 opp-peak-kBps = <2929000>; 5035 }; 5036 5037 opp-5 { 5038 opp-peak-kBps = <5931000>; 5039 }; 5040 5041 opp-6 { 5042 opp-peak-kBps = <6515000>; 5043 }; 5044 5045 opp-7 { 5046 opp-peak-kBps = <7984000>; 5047 }; 5048 5049 opp-8 { 5050 opp-peak-kBps = <10437000>; 5051 }; 5052 5053 opp-9 { 5054 opp-peak-kBps = <12195000>; 5055 }; 5056 }; 5057 }; 5058 5059 pmu@90b5400 { 5060 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; 5061 reg = <0x0 0x90b5400 0x0 0x600>; 5062 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5063 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5064 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 5065 5066 operating-points-v2 = <&cpu_bwmon_opp_table>; 5067 5068 cpu_bwmon_opp_table: opp-table { 5069 compatible = "operating-points-v2"; 5070 5071 opp-0 { 5072 opp-peak-kBps = <9155000>; 5073 }; 5074 5075 opp-1 { 5076 opp-peak-kBps = <12298000>; 5077 }; 5078 5079 opp-2 { 5080 opp-peak-kBps = <14236000>; 5081 }; 5082 5083 opp-3 { 5084 opp-peak-kBps = <16265000>; 5085 }; 5086 }; 5087 }; 5088 5089 pmu@90b6400 { 5090 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; 5091 reg = <0x0 0x90b6400 0x0 0x600>; 5092 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5093 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5094 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 5095 5096 operating-points-v2 = <&cpu_bwmon_opp_table>; 5097 }; 5098 5099 dc_noc: interconnect@90e0000 { 5100 compatible = "qcom,qcs8300-dc-noc"; 5101 reg = <0x0 0x090e0000 0x0 0x5080>; 5102 #interconnect-cells = <2>; 5103 qcom,bcm-voters = <&apps_bcm_voter>; 5104 }; 5105 5106 gem_noc: interconnect@9100000 { 5107 compatible = "qcom,qcs8300-gem-noc"; 5108 reg = <0x0 0x9100000 0x0 0xf7080>; 5109 #interconnect-cells = <2>; 5110 qcom,bcm-voters = <&apps_bcm_voter>; 5111 }; 5112 5113 llcc: system-cache-controller@9200000 { 5114 compatible = "qcom,qcs8300-llcc"; 5115 reg = <0x0 0x09200000 0x0 0x80000>, 5116 <0x0 0x09300000 0x0 0x80000>, 5117 <0x0 0x09400000 0x0 0x80000>, 5118 <0x0 0x09500000 0x0 0x80000>, 5119 <0x0 0x09a00000 0x0 0x80000>; 5120 reg-names = "llcc0_base", 5121 "llcc1_base", 5122 "llcc2_base", 5123 "llcc3_base", 5124 "llcc_broadcast_base"; 5125 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 5126 }; 5127 5128 usb_1: usb@a600000 { 5129 compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3"; 5130 reg = <0x0 0x0a600000 0x0 0xfc100>; 5131 5132 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 5133 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 5134 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 5135 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 5136 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 5137 clock-names = "cfg_noc", 5138 "core", 5139 "iface", 5140 "sleep", 5141 "mock_utmi"; 5142 5143 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5144 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 5145 assigned-clock-rates = <19200000>, <200000000>; 5146 5147 interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 5148 <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 5149 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 5150 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 5151 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 5152 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 5153 interrupt-names = "dwc_usb3", 5154 "pwr_event", 5155 "hs_phy_irq", 5156 "dp_hs_phy_irq", 5157 "dm_hs_phy_irq", 5158 "ss_phy_irq"; 5159 5160 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 5161 required-opps = <&rpmhpd_opp_nom>; 5162 5163 resets = <&gcc GCC_USB30_PRIM_BCR>; 5164 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 5165 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5166 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 5167 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; 5168 interconnect-names = "usb-ddr", "apps-usb"; 5169 5170 iommus = <&apps_smmu 0x80 0x0>; 5171 phys = <&usb_1_hsphy>, <&usb_qmpphy>; 5172 phy-names = "usb2-phy", "usb3-phy"; 5173 snps,dis_enblslpm_quirk; 5174 snps,dis-u1-entry-quirk; 5175 snps,dis-u2-entry-quirk; 5176 snps,dis_u2_susphy_quirk; 5177 snps,dis_u3_susphy_quirk; 5178 5179 wakeup-source; 5180 5181 status = "disabled"; 5182 }; 5183 5184 usb_2: usb@a400000 { 5185 compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3"; 5186 reg = <0x0 0x0a400000 0x0 0xfc100>; 5187 5188 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 5189 <&gcc GCC_USB20_MASTER_CLK>, 5190 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 5191 <&gcc GCC_USB20_SLEEP_CLK>, 5192 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 5193 clock-names = "cfg_noc", 5194 "core", 5195 "iface", 5196 "sleep", 5197 "mock_utmi"; 5198 5199 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 5200 <&gcc GCC_USB20_MASTER_CLK>; 5201 assigned-clock-rates = <19200000>, <120000000>; 5202 5203 interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 5204 <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 5205 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 5206 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 5207 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 5208 interrupt-names = "dwc_usb3", 5209 "pwr_event", 5210 "hs_phy_irq", 5211 "dp_hs_phy_irq", 5212 "dm_hs_phy_irq"; 5213 5214 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 5215 required-opps = <&rpmhpd_opp_nom>; 5216 5217 resets = <&gcc GCC_USB20_PRIM_BCR>; 5218 5219 interconnects = <&aggre1_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 5220 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5221 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 5222 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; 5223 interconnect-names = "usb-ddr", "apps-usb"; 5224 5225 iommus = <&apps_smmu 0x20 0x0>; 5226 5227 phys = <&usb_2_hsphy>; 5228 phy-names = "usb2-phy"; 5229 maximum-speed = "high-speed"; 5230 5231 snps,dis-u1-entry-quirk; 5232 snps,dis-u2-entry-quirk; 5233 snps,dis_u2_susphy_quirk; 5234 snps,dis_u3_susphy_quirk; 5235 snps,dis_enblslpm_quirk; 5236 5237 qcom,select-utmi-as-pipe-clk; 5238 wakeup-source; 5239 5240 status = "disabled"; 5241 }; 5242 5243 iris: video-codec@aa00000 { 5244 compatible = "qcom,qcs8300-iris"; 5245 5246 reg = <0x0 0x0aa00000 0x0 0xf0000>; 5247 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 5248 5249 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 5250 <&videocc VIDEO_CC_MVS0_GDSC>, 5251 <&rpmhpd RPMHPD_MX>, 5252 <&rpmhpd RPMHPD_MMCX>; 5253 power-domain-names = "venus", 5254 "vcodec0", 5255 "mxc", 5256 "mmcx"; 5257 5258 operating-points-v2 = <&iris_opp_table>; 5259 5260 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 5261 <&videocc VIDEO_CC_MVS0C_CLK>, 5262 <&videocc VIDEO_CC_MVS0_CLK>; 5263 clock-names = "iface", 5264 "core", 5265 "vcodec0_core"; 5266 5267 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5268 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5269 <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 5270 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5271 interconnect-names = "cpu-cfg", 5272 "video-mem"; 5273 5274 memory-region = <&video_mem>; 5275 5276 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 5277 reset-names = "bus"; 5278 5279 iommus = <&apps_smmu 0x0880 0x0400>, 5280 <&apps_smmu 0x0887 0x0400>; 5281 dma-coherent; 5282 5283 status = "disabled"; 5284 5285 iris_opp_table: opp-table { 5286 compatible = "operating-points-v2"; 5287 5288 opp-366000000 { 5289 opp-hz = /bits/ 64 <366000000>; 5290 required-opps = <&rpmhpd_opp_svs_l1>, 5291 <&rpmhpd_opp_svs_l1>; 5292 }; 5293 5294 opp-444000000 { 5295 opp-hz = /bits/ 64 <444000000>; 5296 required-opps = <&rpmhpd_opp_nom>, 5297 <&rpmhpd_opp_nom>; 5298 }; 5299 5300 opp-533000000 { 5301 opp-hz = /bits/ 64 <533000000>; 5302 required-opps = <&rpmhpd_opp_turbo>, 5303 <&rpmhpd_opp_turbo>; 5304 }; 5305 5306 opp-560000000 { 5307 opp-hz = /bits/ 64 <560000000>; 5308 required-opps = <&rpmhpd_opp_turbo_l1>, 5309 <&rpmhpd_opp_turbo_l1>; 5310 }; 5311 }; 5312 }; 5313 5314 videocc: clock-controller@abf0000 { 5315 compatible = "qcom,qcs8300-videocc"; 5316 reg = <0x0 0x0abf0000 0x0 0x10000>; 5317 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 5318 <&rpmhcc RPMH_CXO_CLK>, 5319 <&rpmhcc RPMH_CXO_CLK_A>, 5320 <&sleep_clk>; 5321 power-domains = <&rpmhpd RPMHPD_MMCX>; 5322 #clock-cells = <1>; 5323 #reset-cells = <1>; 5324 #power-domain-cells = <1>; 5325 }; 5326 5327 camss: isp@ac78000 { 5328 compatible = "qcom,qcs8300-camss"; 5329 5330 reg = <0x0 0xac78000 0x0 0x1000>, 5331 <0x0 0xac7a000 0x0 0xf00>, 5332 <0x0 0xac7c000 0x0 0xf00>, 5333 <0x0 0xac84000 0x0 0xf00>, 5334 <0x0 0xac88000 0x0 0xf00>, 5335 <0x0 0xac8c000 0x0 0xf00>, 5336 <0x0 0xac90000 0x0 0xf00>, 5337 <0x0 0xac94000 0x0 0xf00>, 5338 <0x0 0xac9c000 0x0 0x2000>, 5339 <0x0 0xac9e000 0x0 0x2000>, 5340 <0x0 0xaca0000 0x0 0x2000>, 5341 <0x0 0xacac000 0x0 0x400>, 5342 <0x0 0xacad000 0x0 0x400>, 5343 <0x0 0xacae000 0x0 0x400>, 5344 <0x0 0xac4d000 0x0 0xf000>, 5345 <0x0 0xac60000 0x0 0xf000>, 5346 <0x0 0xac85000 0x0 0xd00>, 5347 <0x0 0xac89000 0x0 0xd00>, 5348 <0x0 0xac8d000 0x0 0xd00>, 5349 <0x0 0xac91000 0x0 0xd00>, 5350 <0x0 0xac95000 0x0 0xd00>; 5351 reg-names = "csid_wrapper", 5352 "csid0", 5353 "csid1", 5354 "csid_lite0", 5355 "csid_lite1", 5356 "csid_lite2", 5357 "csid_lite3", 5358 "csid_lite4", 5359 "csiphy0", 5360 "csiphy1", 5361 "csiphy2", 5362 "tpg0", 5363 "tpg1", 5364 "tpg2", 5365 "vfe0", 5366 "vfe1", 5367 "vfe_lite0", 5368 "vfe_lite1", 5369 "vfe_lite2", 5370 "vfe_lite3", 5371 "vfe_lite4"; 5372 5373 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 5374 <&camcc CAM_CC_CORE_AHB_CLK>, 5375 <&camcc CAM_CC_CPAS_AHB_CLK>, 5376 <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, 5377 <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, 5378 <&camcc CAM_CC_CPAS_IFE_0_CLK>, 5379 <&camcc CAM_CC_CPAS_IFE_1_CLK>, 5380 <&camcc CAM_CC_CSID_CLK>, 5381 <&camcc CAM_CC_CSIPHY0_CLK>, 5382 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 5383 <&camcc CAM_CC_CSIPHY1_CLK>, 5384 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 5385 <&camcc CAM_CC_CSIPHY2_CLK>, 5386 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 5387 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, 5388 <&gcc GCC_CAMERA_HF_AXI_CLK>, 5389 <&gcc GCC_CAMERA_SF_AXI_CLK>, 5390 <&camcc CAM_CC_ICP_AHB_CLK>, 5391 <&camcc CAM_CC_IFE_0_CLK>, 5392 <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, 5393 <&camcc CAM_CC_IFE_1_CLK>, 5394 <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, 5395 <&camcc CAM_CC_IFE_LITE_CLK>, 5396 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 5397 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 5398 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 5399 clock-names = "camnoc_axi", 5400 "core_ahb", 5401 "cpas_ahb", 5402 "cpas_fast_ahb_clk", 5403 "cpas_vfe_lite", 5404 "cpas_vfe0", 5405 "cpas_vfe1", 5406 "csid", 5407 "csiphy0", 5408 "csiphy0_timer", 5409 "csiphy1", 5410 "csiphy1_timer", 5411 "csiphy2", 5412 "csiphy2_timer", 5413 "csiphy_rx", 5414 "gcc_axi_hf", 5415 "gcc_axi_sf", 5416 "icp_ahb", 5417 "vfe0", 5418 "vfe0_fast_ahb", 5419 "vfe1", 5420 "vfe1_fast_ahb", 5421 "vfe_lite", 5422 "vfe_lite_ahb", 5423 "vfe_lite_cphy_rx", 5424 "vfe_lite_csid"; 5425 5426 interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>, 5427 <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>, 5428 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 5429 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 5430 <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, 5431 <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, 5432 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 5433 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 5434 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 5435 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 5436 <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>, 5437 <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>, 5438 <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>, 5439 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 5440 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 5441 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 5442 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, 5443 <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, 5444 <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, 5445 <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>; 5446 interrupt-names = "csid0", 5447 "csid1", 5448 "csid_lite0", 5449 "csid_lite1", 5450 "csid_lite2", 5451 "csid_lite3", 5452 "csid_lite4", 5453 "csiphy0", 5454 "csiphy1", 5455 "csiphy2", 5456 "tpg0", 5457 "tpg1", 5458 "tpg2", 5459 "vfe0", 5460 "vfe1", 5461 "vfe_lite0", 5462 "vfe_lite1", 5463 "vfe_lite2", 5464 "vfe_lite3", 5465 "vfe_lite4"; 5466 5467 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5468 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5469 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 5470 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5471 interconnect-names = "ahb", 5472 "hf_0"; 5473 5474 iommus = <&apps_smmu 0x2400 0x20>; 5475 5476 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5477 power-domain-names = "top"; 5478 5479 status = "disabled"; 5480 5481 ports { 5482 #address-cells = <1>; 5483 #size-cells = <0>; 5484 5485 port@0 { 5486 reg = <0>; 5487 }; 5488 5489 port@1 { 5490 reg = <1>; 5491 }; 5492 5493 port@2 { 5494 reg = <2>; 5495 }; 5496 }; 5497 }; 5498 5499 camcc: clock-controller@ade0000 { 5500 compatible = "qcom,qcs8300-camcc"; 5501 reg = <0x0 0x0ade0000 0x0 0x20000>; 5502 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 5503 <&rpmhcc RPMH_CXO_CLK>, 5504 <&rpmhcc RPMH_CXO_CLK_A>, 5505 <&sleep_clk>; 5506 power-domains = <&rpmhpd RPMHPD_MMCX>; 5507 #clock-cells = <1>; 5508 #reset-cells = <1>; 5509 #power-domain-cells = <1>; 5510 }; 5511 5512 mdss: display-subsystem@ae00000 { 5513 compatible = "qcom,qcs8300-mdss"; 5514 reg = <0x0 0x0ae00000 0x0 0x1000>; 5515 reg-names = "mdss"; 5516 5517 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 5518 5519 clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 5520 <&gcc GCC_DISP_HF_AXI_CLK>, 5521 <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>; 5522 5523 resets = <&dispcc MDSS_DISP_CC_MDSS_CORE_BCR>; 5524 5525 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 5526 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5527 <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS 5528 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5529 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5530 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5531 interconnect-names = "mdp0-mem", 5532 "mdp1-mem", 5533 "cpu-cfg"; 5534 5535 power-domains = <&dispcc MDSS_DISP_CC_MDSS_CORE_GDSC>; 5536 5537 iommus = <&apps_smmu 0x1000 0x402>; 5538 5539 interrupt-controller; 5540 #interrupt-cells = <1>; 5541 5542 #address-cells = <2>; 5543 #size-cells = <2>; 5544 ranges; 5545 5546 status = "disabled"; 5547 5548 mdss_mdp: display-controller@ae01000 { 5549 compatible = "qcom,qcs8300-dpu", "qcom,sa8775p-dpu"; 5550 reg = <0x0 0x0ae01000 0x0 0x8f000>, 5551 <0x0 0x0aeb0000 0x0 0x2008>; 5552 reg-names = "mdp", "vbif"; 5553 5554 interrupts-extended = <&mdss 0>; 5555 5556 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5557 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 5558 <&dispcc MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, 5559 <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>, 5560 <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; 5561 clock-names = "nrt_bus", 5562 "iface", 5563 "lut", 5564 "core", 5565 "vsync"; 5566 5567 assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; 5568 assigned-clock-rates = <19200000>; 5569 5570 operating-points-v2 = <&mdp_opp_table>; 5571 power-domains = <&rpmhpd RPMHPD_MMCX>; 5572 5573 ports { 5574 #address-cells = <1>; 5575 #size-cells = <0>; 5576 5577 port@0 { 5578 reg = <0>; 5579 5580 dpu_intf0_out: endpoint { 5581 remote-endpoint = <&mdss_dp0_in>; 5582 }; 5583 }; 5584 }; 5585 5586 mdp_opp_table: opp-table { 5587 compatible = "operating-points-v2"; 5588 5589 opp-375000000 { 5590 opp-hz = /bits/ 64 <375000000>; 5591 required-opps = <&rpmhpd_opp_svs_l1>; 5592 }; 5593 5594 opp-500000000 { 5595 opp-hz = /bits/ 64 <500000000>; 5596 required-opps = <&rpmhpd_opp_nom>; 5597 }; 5598 5599 opp-575000000 { 5600 opp-hz = /bits/ 64 <575000000>; 5601 required-opps = <&rpmhpd_opp_turbo>; 5602 }; 5603 5604 opp-650000000 { 5605 opp-hz = /bits/ 64 <650000000>; 5606 required-opps = <&rpmhpd_opp_turbo_l1>; 5607 }; 5608 }; 5609 }; 5610 5611 mdss_dp0_phy: phy@aec2a00 { 5612 compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy"; 5613 5614 reg = <0x0 0x0aec2a00 0x0 0x19c>, 5615 <0x0 0x0aec2200 0x0 0xec>, 5616 <0x0 0x0aec2600 0x0 0xec>, 5617 <0x0 0x0aec2000 0x0 0x1c8>; 5618 5619 clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5620 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>; 5621 clock-names = "aux", 5622 "cfg_ahb"; 5623 5624 power-domains = <&rpmhpd RPMHPD_MX>; 5625 5626 #clock-cells = <1>; 5627 #phy-cells = <0>; 5628 5629 status = "disabled"; 5630 }; 5631 5632 mdss_dp0: displayport-controller@af54000 { 5633 compatible = "qcom,qcs8300-dp", "qcom,sa8775p-dp"; 5634 5635 reg = <0x0 0x0af54000 0x0 0x200>, 5636 <0x0 0x0af54200 0x0 0x200>, 5637 <0x0 0x0af55000 0x0 0xc00>, 5638 <0x0 0x0af56000 0x0 0x09c>, 5639 <0x0 0x0af57000 0x0 0x09c>, 5640 <0x0 0x0af58000 0x0 0x09c>, 5641 <0x0 0x0af59000 0x0 0x09c>, 5642 <0x0 0x0af5a000 0x0 0x23c>, 5643 <0x0 0x0af5b000 0x0 0x23c>; 5644 5645 interrupts-extended = <&mdss 12>; 5646 5647 clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 5648 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5649 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, 5650 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5651 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 5652 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, 5653 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, 5654 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; 5655 clock-names = "core_iface", 5656 "core_aux", 5657 "ctrl_link", 5658 "ctrl_link_iface", 5659 "stream_pixel", 5660 "stream_1_pixel", 5661 "stream_2_pixel", 5662 "stream_3_pixel"; 5663 assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5664 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 5665 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, 5666 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, 5667 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; 5668 assigned-clock-parents = <&mdss_dp0_phy 0>, 5669 <&mdss_dp0_phy 1>, 5670 <&mdss_dp0_phy 1>, 5671 <&mdss_dp0_phy 1>, 5672 <&mdss_dp0_phy 1>; 5673 phys = <&mdss_dp0_phy>; 5674 phy-names = "dp"; 5675 5676 operating-points-v2 = <&dp_opp_table>; 5677 power-domains = <&rpmhpd RPMHPD_MMCX>; 5678 5679 #sound-dai-cells = <0>; 5680 5681 status = "disabled"; 5682 5683 ports { 5684 #address-cells = <1>; 5685 #size-cells = <0>; 5686 5687 port@0 { 5688 reg = <0>; 5689 5690 mdss_dp0_in: endpoint { 5691 remote-endpoint = <&dpu_intf0_out>; 5692 }; 5693 }; 5694 5695 port@1 { 5696 reg = <1>; 5697 5698 mdss_dp0_out: endpoint { }; 5699 }; 5700 }; 5701 5702 dp_opp_table: opp-table { 5703 compatible = "operating-points-v2"; 5704 5705 opp-160000000 { 5706 opp-hz = /bits/ 64 <160000000>; 5707 required-opps = <&rpmhpd_opp_low_svs>; 5708 }; 5709 5710 opp-270000000 { 5711 opp-hz = /bits/ 64 <270000000>; 5712 required-opps = <&rpmhpd_opp_svs>; 5713 }; 5714 5715 opp-540000000 { 5716 opp-hz = /bits/ 64 <540000000>; 5717 required-opps = <&rpmhpd_opp_svs_l1>; 5718 }; 5719 5720 opp-810000000 { 5721 opp-hz = /bits/ 64 <810000000>; 5722 required-opps = <&rpmhpd_opp_nom>; 5723 }; 5724 }; 5725 }; 5726 }; 5727 5728 dispcc: clock-controller@af00000 { 5729 compatible = "qcom,sa8775p-dispcc0"; 5730 reg = <0x0 0x0af00000 0x0 0x20000>; 5731 clocks = <&gcc GCC_DISP_AHB_CLK>, 5732 <&rpmhcc RPMH_CXO_CLK>, 5733 <&rpmhcc RPMH_CXO_CLK_A>, 5734 <&sleep_clk>, 5735 <&mdss_dp0_phy 0>, 5736 <&mdss_dp0_phy 1>, 5737 <0>, <0>, 5738 <0>, <0>, <0>, <0>; 5739 power-domains = <&rpmhpd RPMHPD_MMCX>; 5740 #clock-cells = <1>; 5741 #reset-cells = <1>; 5742 #power-domain-cells = <1>; 5743 }; 5744 5745 pdc: interrupt-controller@b220000 { 5746 compatible = "qcom,qcs8300-pdc", "qcom,pdc"; 5747 reg = <0x0 0xb220000 0x0 0x30000>, 5748 <0x0 0x17c000f0 0x0 0x64>; 5749 interrupt-parent = <&intc>; 5750 #interrupt-cells = <2>; 5751 interrupt-controller; 5752 qcom,pdc-ranges = <0 480 40>, 5753 <40 140 14>, 5754 <54 263 1>, 5755 <55 306 4>, 5756 <59 312 3>, 5757 <62 374 2>, 5758 <64 434 2>, 5759 <66 438 2>, 5760 <70 520 1>, 5761 <73 523 1>, 5762 <118 568 6>, 5763 <124 609 3>, 5764 <159 638 1>, 5765 <160 720 3>, 5766 <169 728 30>, 5767 <199 416 2>, 5768 <201 449 1>, 5769 <202 89 1>, 5770 <203 451 1>, 5771 <204 462 1>, 5772 <205 264 1>, 5773 <206 579 1>, 5774 <207 653 1>, 5775 <208 656 1>, 5776 <209 659 1>, 5777 <210 122 1>, 5778 <211 699 1>, 5779 <212 705 1>, 5780 <213 450 1>, 5781 <214 643 2>, 5782 <216 646 5>, 5783 <221 390 5>, 5784 <226 700 2>, 5785 <228 440 1>, 5786 <229 663 1>, 5787 <230 524 2>, 5788 <232 612 3>, 5789 <235 723 5>; 5790 }; 5791 5792 tsens2: thermal-sensor@c251000 { 5793 compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; 5794 reg = <0x0 0x0c251000 0x0 0x1000>, 5795 <0x0 0x0c224000 0x0 0x1000>; 5796 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, 5797 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 5798 interrupt-names = "uplow", "critical"; 5799 #qcom,sensors = <10>; 5800 #thermal-sensor-cells = <1>; 5801 }; 5802 5803 tsens3: thermal-sensor@c252000 { 5804 compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; 5805 reg = <0x0 0x0c252000 0x0 0x1000>, 5806 <0x0 0x0c225000 0x0 0x1000>; 5807 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, 5808 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 5809 interrupt-names = "uplow", "critical"; 5810 #qcom,sensors = <10>; 5811 #thermal-sensor-cells = <1>; 5812 }; 5813 5814 tsens0: thermal-sensor@c263000 { 5815 compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; 5816 reg = <0x0 0x0c263000 0x0 0x1000>, 5817 <0x0 0x0c222000 0x0 0x1000>; 5818 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5819 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5820 interrupt-names = "uplow", "critical"; 5821 #qcom,sensors = <10>; 5822 #thermal-sensor-cells = <1>; 5823 }; 5824 5825 tsens1: thermal-sensor@c265000 { 5826 compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; 5827 reg = <0x0 0x0c265000 0x0 0x1000>, 5828 <0x0 0x0c223000 0x0 0x1000>; 5829 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5830 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5831 interrupt-names = "uplow", "critical"; 5832 #qcom,sensors = <10>; 5833 #thermal-sensor-cells = <1>; 5834 }; 5835 5836 aoss_qmp: power-management@c300000 { 5837 compatible = "qcom,qcs8300-aoss-qmp", "qcom,aoss-qmp"; 5838 reg = <0x0 0x0c300000 0x0 0x400>; 5839 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 5840 IPCC_MPROC_SIGNAL_GLINK_QMP 5841 IRQ_TYPE_EDGE_RISING>; 5842 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5843 #clock-cells = <0>; 5844 }; 5845 5846 sram@c3f0000 { 5847 compatible = "qcom,rpmh-stats"; 5848 reg = <0x0 0x0c3f0000 0x0 0x400>; 5849 }; 5850 5851 spmi_bus: spmi@c440000 { 5852 compatible = "qcom,spmi-pmic-arb"; 5853 reg = <0x0 0x0c440000 0x0 0x1100>, 5854 <0x0 0x0c600000 0x0 0x2000000>, 5855 <0x0 0x0e600000 0x0 0x100000>, 5856 <0x0 0x0e700000 0x0 0xa0000>, 5857 <0x0 0x0c40a000 0x0 0x26000>; 5858 reg-names = "core", 5859 "chnls", 5860 "obsrvr", 5861 "intr", 5862 "cnfg"; 5863 qcom,channel = <0>; 5864 qcom,ee = <0>; 5865 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5866 interrupt-names = "periph_irq"; 5867 interrupt-controller; 5868 #interrupt-cells = <4>; 5869 #address-cells = <2>; 5870 #size-cells = <0>; 5871 }; 5872 5873 tlmm: pinctrl@f100000 { 5874 compatible = "qcom,qcs8300-tlmm"; 5875 reg = <0x0 0x0f100000 0x0 0x300000>; 5876 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5877 gpio-controller; 5878 #gpio-cells = <2>; 5879 gpio-ranges = <&tlmm 0 0 134>; 5880 interrupt-controller; 5881 #interrupt-cells = <2>; 5882 wakeup-parent = <&pdc>; 5883 5884 hs0_mi2s_active: hs0-mi2s-active-state { 5885 pins = "gpio106", "gpio107", "gpio108", "gpio109"; 5886 function = "hs0_mi2s"; 5887 drive-strength = <8>; 5888 bias-disable; 5889 }; 5890 5891 mi2s1_active: mi2s1-active-state { 5892 data0-pins { 5893 pins = "gpio100"; 5894 function = "mi2s1_data0"; 5895 drive-strength = <8>; 5896 bias-disable; 5897 }; 5898 5899 data1-pins { 5900 pins = "gpio101"; 5901 function = "mi2s1_data1"; 5902 drive-strength = <8>; 5903 bias-disable; 5904 }; 5905 5906 sclk-pins { 5907 pins = "gpio98"; 5908 function = "mi2s1_sck"; 5909 drive-strength = <8>; 5910 bias-disable; 5911 }; 5912 5913 ws-pins { 5914 pins = "gpio99"; 5915 function = "mi2s1_ws"; 5916 drive-strength = <8>; 5917 bias-disable; 5918 }; 5919 }; 5920 5921 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 5922 pins = "gpio17", "gpio18"; 5923 function = "qup0_se0"; 5924 }; 5925 5926 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 5927 pins = "gpio19", "gpio20"; 5928 function = "qup0_se1"; 5929 }; 5930 5931 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 5932 pins = "gpio33", "gpio34"; 5933 function = "qup0_se2"; 5934 }; 5935 5936 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 5937 pins = "gpio25", "gpio26"; 5938 function = "qup0_se3"; 5939 }; 5940 5941 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 5942 pins = "gpio29", "gpio30"; 5943 function = "qup0_se4"; 5944 }; 5945 5946 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 5947 pins = "gpio21", "gpio22"; 5948 function = "qup0_se5"; 5949 }; 5950 5951 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 5952 pins = "gpio80", "gpio81"; 5953 function = "qup0_se6"; 5954 }; 5955 5956 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 5957 pins = "gpio37", "gpio38"; 5958 function = "qup1_se0"; 5959 }; 5960 5961 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 5962 pins = "gpio39", "gpio40"; 5963 function = "qup1_se1"; 5964 }; 5965 5966 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 5967 pins = "gpio84", "gpio85"; 5968 function = "qup1_se2"; 5969 }; 5970 5971 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 5972 pins = "gpio41", "gpio42"; 5973 function = "qup1_se3"; 5974 }; 5975 5976 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 5977 pins = "gpio45", "gpio46"; 5978 function = "qup1_se4"; 5979 }; 5980 5981 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5982 pins = "gpio49", "gpio50"; 5983 function = "qup1_se5"; 5984 }; 5985 5986 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5987 pins = "gpio89", "gpio90"; 5988 function = "qup1_se6"; 5989 }; 5990 5991 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5992 pins = "gpio91", "gpio92"; 5993 function = "qup1_se7"; 5994 }; 5995 5996 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 5997 pins = "gpio10", "gpio11"; 5998 function = "qup2_se0"; 5999 }; 6000 6001 qup_spi0_data_clk: qup-spi0-data-clk-state { 6002 pins = "gpio17", "gpio18", "gpio19"; 6003 function = "qup0_se0"; 6004 }; 6005 6006 qup_spi0_cs: qup-spi0-cs-state { 6007 pins = "gpio20"; 6008 function = "qup0_se0"; 6009 }; 6010 6011 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 6012 pins = "gpio20"; 6013 function = "gpio"; 6014 }; 6015 6016 qup_spi1_data_clk: qup-spi1-data-clk-state { 6017 pins = "gpio19", "gpio20", "gpio17"; 6018 function = "qup0_se1"; 6019 }; 6020 6021 qup_spi1_cs: qup-spi1-cs-state { 6022 pins = "gpio18"; 6023 function = "qup0_se1"; 6024 }; 6025 6026 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 6027 pins = "gpio18"; 6028 function = "gpio"; 6029 }; 6030 6031 qup_spi2_data_clk: qup-spi2-data-clk-state { 6032 pins = "gpio33", "gpio34", "gpio35"; 6033 function = "qup0_se2"; 6034 }; 6035 6036 qup_spi2_cs: qup-spi2-cs-state { 6037 pins = "gpio36"; 6038 function = "qup0_se2"; 6039 }; 6040 6041 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 6042 pins = "gpio36"; 6043 function = "gpio"; 6044 }; 6045 6046 qup_spi3_data_clk: qup-spi3-data-clk-state { 6047 pins = "gpio25", "gpio26", "gpio27"; 6048 function = "qup0_se3"; 6049 }; 6050 6051 qup_spi3_cs: qup-spi3-cs-state { 6052 pins = "gpio28"; 6053 function = "qup0_se3"; 6054 }; 6055 6056 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 6057 pins = "gpio28"; 6058 function = "gpio"; 6059 }; 6060 6061 qup_spi4_data_clk: qup-spi4-data-clk-state { 6062 pins = "gpio29", "gpio30", "gpio31"; 6063 function = "qup0_se4"; 6064 }; 6065 6066 qup_spi4_cs: qup-spi4-cs-state { 6067 pins = "gpio32"; 6068 function = "qup0_se4"; 6069 }; 6070 6071 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 6072 pins = "gpio32"; 6073 function = "gpio"; 6074 }; 6075 6076 qup_spi5_data_clk: qup-spi5-data-clk-state { 6077 pins = "gpio21", "gpio22", "gpio23"; 6078 function = "qup0_se5"; 6079 }; 6080 6081 qup_spi5_cs: qup-spi5-cs-state { 6082 pins = "gpio24"; 6083 function = "qup0_se5"; 6084 }; 6085 6086 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 6087 pins = "gpio24"; 6088 function = "gpio"; 6089 }; 6090 6091 qup_spi6_data_clk: qup-spi6-data-clk-state { 6092 pins = "gpio80", "gpio81", "gpio82"; 6093 function = "qup0_se6"; 6094 }; 6095 6096 qup_spi6_cs: qup-spi6-cs-state { 6097 pins = "gpio83"; 6098 function = "qup0_se6"; 6099 }; 6100 6101 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 6102 pins = "gpio83"; 6103 function = "gpio"; 6104 }; 6105 6106 qup_spi8_data_clk: qup-spi8-data-clk-state { 6107 pins = "gpio37", "gpio38", "gpio39"; 6108 function = "qup1_se0"; 6109 }; 6110 6111 qup_spi8_cs: qup-spi8-cs-state { 6112 pins = "gpio40"; 6113 function = "qup1_se0"; 6114 }; 6115 6116 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 6117 pins = "gpio40"; 6118 function = "gpio"; 6119 }; 6120 6121 qup_spi9_data_clk: qup-spi9-data-clk-state { 6122 pins = "gpio39", "gpio40", "gpio37"; 6123 function = "qup1_se1"; 6124 }; 6125 6126 qup_spi9_cs: qup-spi9-cs-state { 6127 pins = "gpio38"; 6128 function = "qup1_se1"; 6129 }; 6130 6131 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 6132 pins = "gpio38"; 6133 function = "gpio"; 6134 }; 6135 6136 qup_spi10_data_clk: qup-spi10-data-clk-state { 6137 pins = "gpio84", "gpio85", "gpio86"; 6138 function = "qup1_se2"; 6139 }; 6140 6141 qup_spi10_cs: qup-spi10-cs-state { 6142 pins = "gpio87"; 6143 function = "qup1_se2"; 6144 }; 6145 6146 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 6147 pins = "gpio87"; 6148 function = "gpio"; 6149 }; 6150 6151 qup_spi12_data_clk: qup-spi12-data-clk-state { 6152 pins = "gpio45", "gpio46", "gpio47"; 6153 function = "qup1_se4"; 6154 }; 6155 6156 qup_spi12_cs: qup-spi12-cs-state { 6157 pins = "gpio48"; 6158 function = "qup1_se4"; 6159 }; 6160 6161 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 6162 pins = "gpio48"; 6163 function = "gpio"; 6164 }; 6165 6166 qup_spi13_data_clk: qup-spi13-data-clk-state { 6167 pins = "gpio49", "gpio50", "gpio51"; 6168 function = "qup1_se5"; 6169 }; 6170 6171 qup_spi13_cs: qup-spi13-cs-state { 6172 pins = "gpio52"; 6173 function = "qup1_se5"; 6174 }; 6175 6176 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 6177 pins = "gpio52"; 6178 function = "gpio"; 6179 }; 6180 6181 qup_spi14_data_clk: qup-spi14-data-clk-state { 6182 pins = "gpio89", "gpio90", "gpio91"; 6183 function = "qup1_se6"; 6184 }; 6185 6186 qup_spi14_cs: qup-spi14-cs-state { 6187 pins = "gpio92"; 6188 function = "qup1_se6"; 6189 }; 6190 6191 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 6192 pins = "gpio92"; 6193 function = "gpio"; 6194 }; 6195 6196 qup_spi15_data_clk: qup-spi15-data-clk-state { 6197 pins = "gpio91", "gpio92", "gpio89"; 6198 function = "qup1_se7"; 6199 }; 6200 6201 qup_spi15_cs: qup-spi15-cs-state { 6202 pins = "gpio90"; 6203 function = "qup1_se7"; 6204 }; 6205 6206 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 6207 pins = "gpio90"; 6208 function = "gpio"; 6209 }; 6210 6211 qup_spi16_data_clk: qup-spi16-data-clk-state { 6212 pins = "gpio10", "gpio11", "gpio12"; 6213 function = "qup2_se0"; 6214 }; 6215 6216 qup_spi16_cs: qup-spi16-cs-state { 6217 pins = "gpio13"; 6218 function = "qup2_se0"; 6219 }; 6220 6221 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { 6222 pins = "gpio13"; 6223 function = "gpio"; 6224 }; 6225 6226 qup_uart0_cts: qup-uart0-cts-state { 6227 pins = "gpio17"; 6228 function = "qup0_se0"; 6229 }; 6230 6231 qup_uart0_rts: qup-uart0-rts-state { 6232 pins = "gpio18"; 6233 function = "qup0_se0"; 6234 }; 6235 6236 qup_uart0_tx: qup-uart0-tx-state { 6237 pins = "gpio19"; 6238 function = "qup0_se0"; 6239 }; 6240 6241 qup_uart0_rx: qup-uart0-rx-state { 6242 pins = "gpio20"; 6243 function = "qup0_se0"; 6244 }; 6245 6246 qup_uart1_cts: qup-uart1-cts-state { 6247 pins = "gpio19"; 6248 function = "qup0_se1"; 6249 }; 6250 6251 qup_uart1_rts: qup-uart1-rts-state { 6252 pins = "gpio20"; 6253 function = "qup0_se1"; 6254 }; 6255 6256 qup_uart1_tx: qup-uart1-tx-state { 6257 pins = "gpio17"; 6258 function = "qup0_se1"; 6259 }; 6260 6261 qup_uart1_rx: qup-uart1-rx-state { 6262 pins = "gpio18"; 6263 function = "qup0_se1"; 6264 }; 6265 6266 qup_uart2_cts: qup-uart2-cts-state { 6267 pins = "gpio33"; 6268 function = "qup0_se2"; 6269 }; 6270 6271 qup_uart2_rts: qup-uart2-rts-state { 6272 pins = "gpio34"; 6273 function = "qup0_se2"; 6274 }; 6275 6276 qup_uart2_tx: qup-uart2-tx-state { 6277 pins = "gpio35"; 6278 function = "qup0_se2"; 6279 }; 6280 6281 qup_uart2_rx: qup-uart2-rx-state { 6282 pins = "gpio36"; 6283 function = "qup0_se2"; 6284 }; 6285 6286 qup_uart3_cts: qup-uart3-cts-state { 6287 pins = "gpio25"; 6288 function = "qup0_se3"; 6289 }; 6290 6291 qup_uart3_rts: qup-uart3-rts-state { 6292 pins = "gpio26"; 6293 function = "qup0_se3"; 6294 }; 6295 6296 qup_uart3_tx: qup-uart3-tx-state { 6297 pins = "gpio27"; 6298 function = "qup0_se3"; 6299 }; 6300 6301 qup_uart3_rx: qup-uart3-rx-state { 6302 pins = "gpio28"; 6303 function = "qup0_se3"; 6304 }; 6305 6306 qup_uart4_cts: qup-uart4-cts-state { 6307 pins = "gpio29"; 6308 function = "qup0_se4"; 6309 }; 6310 6311 qup_uart4_rts: qup-uart4-rts-state { 6312 pins = "gpio30"; 6313 function = "qup0_se4"; 6314 }; 6315 6316 qup_uart4_tx: qup-uart4-tx-state { 6317 pins = "gpio31"; 6318 function = "qup0_se4"; 6319 }; 6320 6321 qup_uart4_rx: qup-uart4-rx-state { 6322 pins = "gpio32"; 6323 function = "qup0_se4"; 6324 }; 6325 6326 qup_uart5_cts: qup-uart5-cts-state { 6327 pins = "gpio21"; 6328 function = "qup0_se5"; 6329 }; 6330 6331 qup_uart5_rts: qup-uart5-rts-state { 6332 pins = "gpio22"; 6333 function = "qup0_se5"; 6334 }; 6335 6336 qup_uart5_tx: qup-uart5-tx-state { 6337 pins = "gpio23"; 6338 function = "qup0_se5"; 6339 }; 6340 6341 qup_uart5_rx: qup-uart5-rx-state { 6342 pins = "gpio23"; 6343 function = "qup0_se5"; 6344 }; 6345 6346 qup_uart6_cts: qup-uart6-cts-state { 6347 pins = "gpio80"; 6348 function = "qup0_se6"; 6349 }; 6350 6351 qup_uart6_rts: qup-uart6-rts-state { 6352 pins = "gpio81"; 6353 function = "qup0_se6"; 6354 }; 6355 6356 qup_uart6_tx: qup-uart6-tx-state { 6357 pins = "gpio82"; 6358 function = "qup0_se6"; 6359 }; 6360 6361 qup_uart6_rx: qup-uart6-rx-state { 6362 pins = "gpio83"; 6363 function = "qup0_se6"; 6364 }; 6365 6366 qup_uart7_tx: qup-uart7-tx-state { 6367 pins = "gpio43"; 6368 function = "qup0_se7"; 6369 }; 6370 6371 qup_uart7_rx: qup-uart7-rx-state { 6372 pins = "gpio44"; 6373 function = "qup0_se7"; 6374 }; 6375 6376 qup_uart8_cts: qup-uart8-cts-state { 6377 pins = "gpio37"; 6378 function = "qup1_se0"; 6379 }; 6380 6381 qup_uart8_rts: qup-uart8-rts-state { 6382 pins = "gpio38"; 6383 function = "qup1_se0"; 6384 }; 6385 6386 qup_uart8_tx: qup-uart8-tx-state { 6387 pins = "gpio39"; 6388 function = "qup1_se0"; 6389 }; 6390 6391 qup_uart8_rx: qup-uart8-rx-state { 6392 pins = "gpio40"; 6393 function = "qup1_se0"; 6394 }; 6395 6396 qup_uart9_cts: qup-uart9-cts-state { 6397 pins = "gpio39"; 6398 function = "qup1_se1"; 6399 }; 6400 6401 qup_uart9_rts: qup-uart9-rts-state { 6402 pins = "gpio40"; 6403 function = "qup1_se1"; 6404 }; 6405 6406 qup_uart9_tx: qup-uart9-tx-state { 6407 pins = "gpio37"; 6408 function = "qup1_se1"; 6409 }; 6410 6411 qup_uart9_rx: qup-uart9-rx-state { 6412 pins = "gpio38"; 6413 function = "qup1_se1"; 6414 }; 6415 6416 qup_uart10_cts: qup-uart10-cts-state { 6417 pins = "gpio84"; 6418 function = "qup1_se2"; 6419 }; 6420 6421 qup_uart10_rts: qup-uart10-rts-state { 6422 pins = "gpio85"; 6423 function = "qup1_se2"; 6424 }; 6425 6426 qup_uart10_tx: qup-uart10-tx-state { 6427 pins = "gpio86"; 6428 function = "qup1_se2"; 6429 }; 6430 6431 qup_uart10_rx: qup-uart10-rx-state { 6432 pins = "gpio87"; 6433 function = "qup1_se2"; 6434 }; 6435 6436 qup_uart11_tx: qup-uart11-tx-state { 6437 pins = "gpio41"; 6438 function = "qup1_se3"; 6439 }; 6440 6441 qup_uart11_rx: qup-uart11-rx-state { 6442 pins = "gpio42"; 6443 function = "qup1_se3"; 6444 }; 6445 6446 qup_uart12_cts: qup-uart12-cts-state { 6447 pins = "gpio45"; 6448 function = "qup1_se4"; 6449 }; 6450 6451 qup_uart12_rts: qup-uart12-rts-state { 6452 pins = "gpio46"; 6453 function = "qup1_se4"; 6454 }; 6455 6456 qup_uart12_tx: qup-uart12-tx-state { 6457 pins = "gpio47"; 6458 function = "qup1_se4"; 6459 }; 6460 6461 qup_uart12_rx: qup-uart12-rx-state { 6462 pins = "gpio48"; 6463 function = "qup1_se4"; 6464 }; 6465 6466 qup_uart13_cts: qup-uart13-cts-state { 6467 pins = "gpio49"; 6468 function = "qup1_se5"; 6469 }; 6470 6471 qup_uart13_rts: qup-uart13-rts-state { 6472 pins = "gpio50"; 6473 function = "qup1_se5"; 6474 }; 6475 6476 qup_uart13_tx: qup-uart13-tx-state { 6477 pins = "gpio51"; 6478 function = "qup1_se5"; 6479 }; 6480 6481 qup_uart13_rx: qup-uart13-rx-state { 6482 pins = "gpio52"; 6483 function = "qup1_se5"; 6484 }; 6485 6486 qup_uart14_cts: qup-uart14-cts-state { 6487 pins = "gpio89"; 6488 function = "qup1_se6"; 6489 }; 6490 6491 qup_uart14_rts: qup-uart14-rts-state { 6492 pins = "gpio90"; 6493 function = "qup1_se6"; 6494 }; 6495 6496 qup_uart14_tx: qup-uart14-tx-state { 6497 pins = "gpio91"; 6498 function = "qup1_se6"; 6499 }; 6500 6501 qup_uart14_rx: qup-uart14-rx-state { 6502 pins = "gpio92"; 6503 function = "qup1_se6"; 6504 }; 6505 6506 qup_uart15_cts: qup-uart15-cts-state { 6507 pins = "gpio91"; 6508 function = "qup1_se7"; 6509 }; 6510 6511 qup_uart15_rts: qup-uart15-rts-state { 6512 pins = "gpio92"; 6513 function = "qup1_se7"; 6514 }; 6515 6516 qup_uart15_tx: qup-uart15-tx-state { 6517 pins = "gpio89"; 6518 function = "qup1_se7"; 6519 }; 6520 6521 qup_uart15_rx: qup-uart15-rx-state { 6522 pins = "gpio90"; 6523 function = "qup1_se7"; 6524 }; 6525 6526 qup_uart16_cts: qup-uart16-cts-state { 6527 pins = "gpio10"; 6528 function = "qup2_se0"; 6529 }; 6530 6531 qup_uart16_rts: qup-uart16-rts-state { 6532 pins = "gpio11"; 6533 function = "qup2_se0"; 6534 }; 6535 6536 qup_uart16_tx: qup-uart16-tx-state { 6537 pins = "gpio12"; 6538 function = "qup2_se0"; 6539 }; 6540 6541 qup_uart16_rx: qup-uart16-rx-state { 6542 pins = "gpio13"; 6543 function = "qup2_se0"; 6544 }; 6545 6546 sdc1_state_on: sdc1-on-state { 6547 clk-pins { 6548 pins = "sdc1_clk"; 6549 drive-strength = <16>; 6550 bias-disable; 6551 }; 6552 6553 cmd-pins { 6554 pins = "sdc1_cmd"; 6555 drive-strength = <10>; 6556 bias-pull-up; 6557 }; 6558 6559 data-pins { 6560 pins = "sdc1_data"; 6561 drive-strength = <10>; 6562 bias-pull-up; 6563 }; 6564 6565 rclk-pins { 6566 pins = "sdc1_rclk"; 6567 bias-pull-down; 6568 }; 6569 }; 6570 6571 sdc1_state_off: sdc1-off-state { 6572 clk-pins { 6573 pins = "sdc1_clk"; 6574 drive-strength = <2>; 6575 bias-bus-hold; 6576 }; 6577 6578 cmd-pins { 6579 pins = "sdc1_cmd"; 6580 drive-strength = <2>; 6581 bias-bus-hold; 6582 }; 6583 6584 data-pins { 6585 pins = "sdc1_data"; 6586 drive-strength = <2>; 6587 bias-bus-hold; 6588 }; 6589 6590 rclk-pins { 6591 pins = "sdc1_rclk"; 6592 bias-bus-hold; 6593 }; 6594 }; 6595 }; 6596 6597 sram: sram@146d8000 { 6598 compatible = "qcom,qcs8300-imem", "syscon", "simple-mfd"; 6599 reg = <0x0 0x146d8000 0x0 0x1000>; 6600 ranges = <0x0 0x0 0x146d8000 0x1000>; 6601 6602 #address-cells = <1>; 6603 #size-cells = <1>; 6604 6605 pil-reloc@94c { 6606 compatible = "qcom,pil-reloc-info"; 6607 reg = <0x94c 0xc8>; 6608 }; 6609 }; 6610 6611 apps_smmu: iommu@15000000 { 6612 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 6613 6614 reg = <0x0 0x15000000 0x0 0x100000>; 6615 #iommu-cells = <2>; 6616 #global-interrupts = <2>; 6617 dma-coherent; 6618 6619 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 6620 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 6621 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 6622 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 6623 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 6624 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 6625 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 6626 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 6627 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 6628 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 6629 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 6630 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 6631 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 6632 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 6633 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 6634 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 6635 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 6636 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 6637 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 6638 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 6639 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 6640 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 6641 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 6642 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 6643 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 6644 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 6645 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 6646 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 6647 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 6648 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 6649 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 6650 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 6651 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 6652 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 6653 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 6654 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 6655 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 6656 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 6657 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 6658 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 6659 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 6660 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 6661 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 6662 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 6663 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 6664 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 6665 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 6666 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 6667 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 6668 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 6669 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 6670 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 6671 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 6672 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 6673 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 6674 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 6675 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 6676 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 6677 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 6678 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 6679 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 6680 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 6681 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 6682 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 6683 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 6684 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 6685 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 6686 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 6687 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 6688 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 6689 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 6690 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 6691 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 6692 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 6693 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 6694 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 6695 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 6696 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 6697 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 6698 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 6699 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 6700 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 6701 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 6702 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 6703 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 6704 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 6705 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 6706 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 6707 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 6708 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 6709 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 6710 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 6711 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 6712 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 6713 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 6714 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 6715 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 6716 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 6717 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 6718 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 6719 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 6720 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 6721 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 6722 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 6723 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 6724 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 6725 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 6726 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 6727 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 6728 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 6729 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 6730 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 6731 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 6732 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 6733 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 6734 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 6735 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 6736 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 6737 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 6738 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 6739 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 6740 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 6741 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 6742 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 6743 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 6744 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 6745 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 6746 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 6747 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 6748 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>; 6749 }; 6750 6751 pcie_smmu: iommu@15200000 { 6752 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 6753 reg = <0x0 0x15200000 0x0 0x80000>; 6754 #iommu-cells = <2>; 6755 #global-interrupts = <2>; 6756 dma-coherent; 6757 6758 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 6759 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 6760 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 6761 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 6762 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 6763 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 6764 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 6765 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 6766 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 6767 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 6768 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 6769 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 6770 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 6771 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 6772 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 6773 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 6774 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 6775 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 6776 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 6777 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 6778 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 6779 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 6780 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 6781 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 6782 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 6783 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 6784 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 6785 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 6786 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 6787 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 6788 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 6789 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 6790 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 6791 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 6792 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 6793 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 6794 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 6795 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 6796 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 6797 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 6798 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 6799 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 6800 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 6801 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 6802 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 6803 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 6804 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 6805 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 6806 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 6807 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 6808 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 6809 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 6810 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 6811 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 6812 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 6813 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 6814 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 6815 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 6816 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 6817 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 6818 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 6819 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 6820 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 6821 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 6822 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 6823 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 6824 }; 6825 6826 intc: interrupt-controller@17a00000 { 6827 compatible = "arm,gic-v3"; 6828 reg = <0x0 0x17a00000 0x0 0x10000>, 6829 <0x0 0x17a60000 0x0 0x100000>; 6830 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 6831 #interrupt-cells = <3>; 6832 interrupt-controller; 6833 #redistributor-regions = <1>; 6834 redistributor-stride = <0x0 0x20000>; 6835 }; 6836 6837 watchdog@17c10000 { 6838 compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt"; 6839 reg = <0x0 0x17c10000 0x0 0x1000>; 6840 clocks = <&sleep_clk>; 6841 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 6842 }; 6843 6844 timer@17c20000 { 6845 compatible = "arm,armv7-timer-mem"; 6846 reg = <0x0 0x17c20000 0x0 0x1000>; 6847 ranges = <0x0 0x0 0x0 0x20000000>; 6848 #address-cells = <1>; 6849 #size-cells = <1>; 6850 6851 frame@17c21000 { 6852 reg = <0x17c21000 0x1000>, 6853 <0x17c22000 0x1000>; 6854 frame-number = <0>; 6855 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6856 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6857 }; 6858 6859 frame@17c23000 { 6860 reg = <0x17c23000 0x1000>; 6861 frame-number = <1>; 6862 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6863 status = "disabled"; 6864 }; 6865 6866 frame@17c25000 { 6867 reg = <0x17c25000 0x1000>; 6868 frame-number = <2>; 6869 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6870 status = "disabled"; 6871 }; 6872 6873 frame@17c27000 { 6874 reg = <0x17c27000 0x1000>; 6875 frame-number = <3>; 6876 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6877 status = "disabled"; 6878 }; 6879 6880 frame@17c29000 { 6881 reg = <0x17c29000 0x1000>; 6882 frame-number = <4>; 6883 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6884 status = "disabled"; 6885 }; 6886 6887 frame@17c2b000 { 6888 reg = <0x17c2b000 0x1000>; 6889 frame-number = <5>; 6890 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6891 status = "disabled"; 6892 }; 6893 6894 frame@17c2d000 { 6895 reg = <0x17c2d000 0x1000>; 6896 frame-number = <6>; 6897 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6898 status = "disabled"; 6899 }; 6900 }; 6901 6902 apps_rsc: rsc@18200000 { 6903 compatible = "qcom,rpmh-rsc"; 6904 reg = <0x0 0x18200000 0x0 0x10000>, 6905 <0x0 0x18210000 0x0 0x10000>, 6906 <0x0 0x18220000 0x0 0x10000>; 6907 reg-names = "drv-0", 6908 "drv-1", 6909 "drv-2"; 6910 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 6911 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 6912 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 6913 6914 power-domains = <&system_pd>; 6915 label = "apps_rsc"; 6916 6917 qcom,tcs-offset = <0xd00>; 6918 qcom,drv-id = <2>; 6919 qcom,tcs-config = <ACTIVE_TCS 2>, 6920 <SLEEP_TCS 3>, 6921 <WAKE_TCS 3>, 6922 <CONTROL_TCS 0>; 6923 6924 apps_bcm_voter: bcm-voter { 6925 compatible = "qcom,bcm-voter"; 6926 }; 6927 6928 rpmhcc: clock-controller { 6929 compatible = "qcom,sa8775p-rpmh-clk"; 6930 #clock-cells = <1>; 6931 clocks = <&xo_board_clk>; 6932 clock-names = "xo"; 6933 }; 6934 6935 rpmhpd: power-controller { 6936 compatible = "qcom,qcs8300-rpmhpd"; 6937 #power-domain-cells = <1>; 6938 operating-points-v2 = <&rpmhpd_opp_table>; 6939 6940 rpmhpd_opp_table: opp-table { 6941 compatible = "operating-points-v2"; 6942 6943 rpmhpd_opp_ret: opp-0 { 6944 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6945 }; 6946 6947 rpmhpd_opp_min_svs: opp-1 { 6948 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 6949 }; 6950 6951 rpmhpd_opp_low_svs: opp-2 { 6952 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6953 }; 6954 6955 rpmhpd_opp_svs: opp-3 { 6956 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6957 }; 6958 6959 rpmhpd_opp_svs_l1: opp-4 { 6960 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6961 }; 6962 6963 rpmhpd_opp_nom: opp-5 { 6964 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6965 }; 6966 6967 rpmhpd_opp_nom_l1: opp-6 { 6968 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6969 }; 6970 6971 rpmhpd_opp_nom_l2: opp-7 { 6972 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 6973 }; 6974 6975 rpmhpd_opp_turbo: opp-8 { 6976 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6977 }; 6978 6979 rpmhpd_opp_turbo_l1: opp-9 { 6980 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6981 }; 6982 }; 6983 }; 6984 }; 6985 6986 epss_l3_cl0: interconnect@18590000 { 6987 compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3", 6988 "qcom,epss-l3"; 6989 reg = <0x0 0x18590000 0x0 0x1000>; 6990 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6991 clock-names = "xo", "alternate"; 6992 #interconnect-cells = <1>; 6993 }; 6994 6995 cpufreq_hw: cpufreq@18591000 { 6996 compatible = "qcom,qcs8300-cpufreq-epss", "qcom,cpufreq-epss"; 6997 reg = <0x0 0x18591000 0x0 0x1000>, 6998 <0x0 0x18593000 0x0 0x1000>, 6999 <0x0 0x18594000 0x0 0x1000>; 7000 reg-names = "freq-domain0", 7001 "freq-domain1", 7002 "freq-domain2"; 7003 7004 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 7005 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 7006 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 7007 interrupt-names = "dcvsh-irq-0", 7008 "dcvsh-irq-1", 7009 "dcvsh-irq-2"; 7010 7011 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 7012 clock-names = "xo", "alternate"; 7013 7014 #freq-domain-cells = <1>; 7015 }; 7016 7017 epss_l3_cl1: interconnect@18592000 { 7018 compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3", 7019 "qcom,epss-l3"; 7020 reg = <0x0 0x18592000 0x0 0x1000>; 7021 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 7022 clock-names = "xo", "alternate"; 7023 #interconnect-cells = <1>; 7024 }; 7025 7026 remoteproc_gpdsp: remoteproc@20c00000 { 7027 compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas"; 7028 reg = <0x0 0x20c00000 0x0 0x10000>; 7029 7030 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 7031 <&smp2p_gpdsp_in 0 0>, 7032 <&smp2p_gpdsp_in 1 0>, 7033 <&smp2p_gpdsp_in 2 0>, 7034 <&smp2p_gpdsp_in 3 0>; 7035 interrupt-names = "wdog", 7036 "fatal", 7037 "ready", 7038 "handover", 7039 "stop-ack"; 7040 7041 clocks = <&rpmhcc RPMH_CXO_CLK>; 7042 clock-names = "xo"; 7043 7044 power-domains = <&rpmhpd RPMHPD_CX>, 7045 <&rpmhpd RPMHPD_MXC>; 7046 power-domain-names = "cx", 7047 "mxc"; 7048 7049 interconnects = <&gpdsp_anoc MASTER_DSP0 QCOM_ICC_TAG_ALWAYS 7050 &config_noc SLAVE_CLK_CTL QCOM_ICC_TAG_ALWAYS>; 7051 7052 memory-region = <&gpdsp_mem>; 7053 7054 qcom,qmp = <&aoss_qmp>; 7055 7056 qcom,smem-states = <&smp2p_gpdsp_out 0>; 7057 qcom,smem-state-names = "stop"; 7058 7059 status = "disabled"; 7060 7061 glink-edge { 7062 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 7063 IPCC_MPROC_SIGNAL_GLINK_QMP 7064 IRQ_TYPE_EDGE_RISING>; 7065 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 7066 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7067 7068 label = "gpdsp"; 7069 qcom,remote-pid = <17>; 7070 }; 7071 }; 7072 7073 ethernet0: ethernet@23040000 { 7074 compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos"; 7075 reg = <0x0 0x23040000 0x0 0x00010000>, 7076 <0x0 0x23056000 0x0 0x00000100>; 7077 reg-names = "stmmaceth", "rgmii"; 7078 7079 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 7080 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; 7081 interrupt-names = "macirq", "sfty"; 7082 7083 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 7084 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 7085 <&gcc GCC_EMAC0_PTP_CLK>, 7086 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 7087 clock-names = "stmmaceth", 7088 "pclk", 7089 "ptp_ref", 7090 "phyaux"; 7091 power-domains = <&gcc GCC_EMAC0_GDSC>; 7092 7093 phys = <&serdes0>; 7094 phy-names = "serdes"; 7095 7096 iommus = <&apps_smmu 0x120 0xf>; 7097 dma-coherent; 7098 7099 snps,tso; 7100 snps,pbl = <32>; 7101 rx-fifo-depth = <16384>; 7102 tx-fifo-depth = <20480>; 7103 7104 status = "disabled"; 7105 }; 7106 7107 nspa_noc: interconnect@260c0000 { 7108 compatible = "qcom,qcs8300-nspa-noc"; 7109 reg = <0x0 0x260c0000 0x0 0x16080>; 7110 #interconnect-cells = <2>; 7111 qcom,bcm-voters = <&apps_bcm_voter>; 7112 }; 7113 7114 remoteproc_cdsp: remoteproc@26300000 { 7115 compatible = "qcom,qcs8300-cdsp-pas", "qcom,sa8775p-cdsp0-pas"; 7116 reg = <0x0 0x26300000 0x0 0x10000>; 7117 7118 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 7119 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 7120 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 7121 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 7122 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 7123 interrupt-names = "wdog", 7124 "fatal", 7125 "ready", 7126 "handover", 7127 "stop-ack"; 7128 7129 clocks = <&rpmhcc RPMH_CXO_CLK>; 7130 clock-names = "xo"; 7131 7132 power-domains = <&rpmhpd RPMHPD_CX>, 7133 <&rpmhpd RPMHPD_MXC>, 7134 <&rpmhpd RPMHPD_NSP0>; 7135 7136 power-domain-names = "cx", 7137 "mxc", 7138 "nsp"; 7139 7140 interconnects = <&nspa_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 7141 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 7142 7143 memory-region = <&cdsp_mem>; 7144 7145 qcom,qmp = <&aoss_qmp>; 7146 7147 qcom,smem-states = <&smp2p_cdsp_out 0>; 7148 qcom,smem-state-names = "stop"; 7149 7150 status = "disabled"; 7151 7152 glink-edge { 7153 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 7154 IPCC_MPROC_SIGNAL_GLINK_QMP 7155 IRQ_TYPE_EDGE_RISING>; 7156 mboxes = <&ipcc IPCC_CLIENT_CDSP 7157 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7158 7159 label = "cdsp"; 7160 qcom,remote-pid = <5>; 7161 7162 fastrpc { 7163 compatible = "qcom,fastrpc"; 7164 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7165 label = "cdsp"; 7166 #address-cells = <1>; 7167 #size-cells = <0>; 7168 7169 compute-cb@1 { 7170 compatible = "qcom,fastrpc-compute-cb"; 7171 reg = <1>; 7172 iommus = <&apps_smmu 0x19c1 0x0440>, 7173 <&apps_smmu 0x1961 0x0400>; 7174 dma-coherent; 7175 }; 7176 7177 compute-cb@2 { 7178 compatible = "qcom,fastrpc-compute-cb"; 7179 reg = <2>; 7180 iommus = <&apps_smmu 0x19c2 0x0440>, 7181 <&apps_smmu 0x1962 0x0400>; 7182 dma-coherent; 7183 }; 7184 7185 compute-cb@3 { 7186 compatible = "qcom,fastrpc-compute-cb"; 7187 reg = <3>; 7188 iommus = <&apps_smmu 0x19c3 0x0440>, 7189 <&apps_smmu 0x1963 0x0400>; 7190 dma-coherent; 7191 }; 7192 7193 compute-cb@4 { 7194 compatible = "qcom,fastrpc-compute-cb"; 7195 reg = <4>; 7196 iommus = <&apps_smmu 0x19c4 0x0440>, 7197 <&apps_smmu 0x1964 0x0400>; 7198 dma-coherent; 7199 }; 7200 }; 7201 }; 7202 }; 7203 }; 7204 7205 thermal_zones: thermal-zones { 7206 aoss-0-thermal { 7207 thermal-sensors = <&tsens0 0>; 7208 7209 trips { 7210 aoss0-critical { 7211 temperature = <125000>; 7212 hysteresis = <1000>; 7213 type = "critical"; 7214 }; 7215 }; 7216 }; 7217 7218 cpu-0-0-0-thermal { 7219 thermal-sensors = <&tsens0 1>; 7220 7221 trips { 7222 cpu-critical { 7223 temperature = <125000>; 7224 hysteresis = <1000>; 7225 type = "critical"; 7226 }; 7227 }; 7228 }; 7229 7230 cpu-0-1-0-thermal { 7231 thermal-sensors = <&tsens0 2>; 7232 7233 trips { 7234 cpu-critical { 7235 temperature = <125000>; 7236 hysteresis = <1000>; 7237 type = "critical"; 7238 }; 7239 }; 7240 }; 7241 7242 cpu-0-2-0-thermal { 7243 thermal-sensors = <&tsens0 3>; 7244 7245 trips { 7246 cpu-critical { 7247 temperature = <125000>; 7248 hysteresis = <1000>; 7249 type = "critical"; 7250 }; 7251 }; 7252 }; 7253 7254 cpu-0-3-0-thermal { 7255 thermal-sensors = <&tsens0 4>; 7256 7257 trips { 7258 cpu-critical { 7259 temperature = <125000>; 7260 hysteresis = <1000>; 7261 type = "critical"; 7262 }; 7263 }; 7264 }; 7265 7266 gpuss-0-thermal { 7267 thermal-sensors = <&tsens0 5>; 7268 7269 trips { 7270 gpuss0_alert0: trip-point0 { 7271 temperature = <115000>; 7272 hysteresis = <5000>; 7273 type = "passive"; 7274 }; 7275 7276 gpuss0-critical { 7277 temperature = <125000>; 7278 hysteresis = <1000>; 7279 type = "critical"; 7280 }; 7281 }; 7282 7283 cooling-maps { 7284 map0 { 7285 trip = <&gpuss0_alert0>; 7286 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7287 }; 7288 }; 7289 }; 7290 7291 audio-thermal { 7292 thermal-sensors = <&tsens0 6>; 7293 7294 trips { 7295 audio-critical { 7296 temperature = <125000>; 7297 hysteresis = <1000>; 7298 type = "critical"; 7299 }; 7300 }; 7301 }; 7302 7303 camss-0-thermal { 7304 thermal-sensors = <&tsens0 7>; 7305 7306 trips { 7307 camss-critical { 7308 temperature = <125000>; 7309 hysteresis = <1000>; 7310 type = "critical"; 7311 }; 7312 }; 7313 }; 7314 7315 pcie-0-thermal { 7316 thermal-sensors = <&tsens0 8>; 7317 7318 trips { 7319 pcie-critical { 7320 temperature = <125000>; 7321 hysteresis = <1000>; 7322 type = "critical"; 7323 }; 7324 }; 7325 }; 7326 7327 cpuss-0-0-thermal { 7328 thermal-sensors = <&tsens0 9>; 7329 7330 trips { 7331 cpuss0-critical { 7332 temperature = <125000>; 7333 hysteresis = <1000>; 7334 type = "critical"; 7335 }; 7336 }; 7337 }; 7338 7339 aoss-1-thermal { 7340 thermal-sensors = <&tsens1 0>; 7341 7342 trips { 7343 aoss1-critical { 7344 temperature = <125000>; 7345 hysteresis = <1000>; 7346 type = "critical"; 7347 }; 7348 }; 7349 }; 7350 7351 cpu-0-0-1-thermal { 7352 thermal-sensors = <&tsens1 1>; 7353 7354 trips { 7355 cpu-critical { 7356 temperature = <125000>; 7357 hysteresis = <1000>; 7358 type = "critical"; 7359 }; 7360 }; 7361 }; 7362 7363 cpu-0-1-1-thermal { 7364 thermal-sensors = <&tsens1 2>; 7365 7366 trips { 7367 cpu-critical { 7368 temperature = <125000>; 7369 hysteresis = <1000>; 7370 type = "critical"; 7371 }; 7372 }; 7373 }; 7374 7375 cpu-0-2-1-thermal { 7376 thermal-sensors = <&tsens1 3>; 7377 7378 trips { 7379 cpu-critical { 7380 temperature = <125000>; 7381 hysteresis = <1000>; 7382 type = "critical"; 7383 }; 7384 }; 7385 }; 7386 7387 cpu-0-3-1-thermal { 7388 thermal-sensors = <&tsens1 4>; 7389 7390 trips { 7391 cpu-critical { 7392 temperature = <125000>; 7393 hysteresis = <1000>; 7394 type = "critical"; 7395 }; 7396 }; 7397 }; 7398 7399 gpuss-1-thermal { 7400 thermal-sensors = <&tsens1 5>; 7401 7402 trips { 7403 gpuss1_alert0: trip-point0 { 7404 temperature = <115000>; 7405 hysteresis = <5000>; 7406 type = "passive"; 7407 }; 7408 7409 gpuss1-critical { 7410 temperature = <125000>; 7411 hysteresis = <1000>; 7412 type = "critical"; 7413 }; 7414 }; 7415 7416 cooling-maps { 7417 map0 { 7418 trip = <&gpuss1_alert0>; 7419 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7420 }; 7421 }; 7422 }; 7423 7424 video-thermal { 7425 thermal-sensors = <&tsens1 6>; 7426 7427 trips { 7428 video-critical { 7429 temperature = <125000>; 7430 hysteresis = <1000>; 7431 type = "critical"; 7432 }; 7433 }; 7434 }; 7435 7436 camss-1-thermal { 7437 thermal-sensors = <&tsens1 7>; 7438 7439 trips { 7440 camss1-critical { 7441 temperature = <125000>; 7442 hysteresis = <1000>; 7443 type = "critical"; 7444 }; 7445 }; 7446 }; 7447 7448 pcie-1-thermal { 7449 thermal-sensors = <&tsens1 8>; 7450 7451 trips { 7452 pcie-critical { 7453 temperature = <125000>; 7454 hysteresis = <1000>; 7455 type = "critical"; 7456 }; 7457 }; 7458 }; 7459 7460 cpuss-0-1-thermal { 7461 thermal-sensors = <&tsens1 9>; 7462 7463 trips { 7464 cpuss0-critical { 7465 temperature = <125000>; 7466 hysteresis = <1000>; 7467 type = "critical"; 7468 }; 7469 }; 7470 }; 7471 7472 aoss-2-thermal { 7473 thermal-sensors = <&tsens2 0>; 7474 7475 trips { 7476 aoss2-critical { 7477 temperature = <125000>; 7478 hysteresis = <1000>; 7479 type = "critical"; 7480 }; 7481 }; 7482 }; 7483 7484 cpu-1-0-0-thermal { 7485 thermal-sensors = <&tsens2 1>; 7486 7487 trips { 7488 cpu-critical { 7489 temperature = <125000>; 7490 hysteresis = <1000>; 7491 type = "critical"; 7492 }; 7493 }; 7494 }; 7495 7496 cpu-1-1-0-thermal { 7497 thermal-sensors = <&tsens2 2>; 7498 7499 trips { 7500 cpu-critical { 7501 temperature = <125000>; 7502 hysteresis = <1000>; 7503 type = "critical"; 7504 }; 7505 }; 7506 }; 7507 7508 cpu-1-2-0-thermal { 7509 thermal-sensors = <&tsens2 3>; 7510 7511 trips { 7512 cpu-critical { 7513 temperature = <125000>; 7514 hysteresis = <1000>; 7515 type = "critical"; 7516 }; 7517 }; 7518 }; 7519 7520 cpu-1-3-0-thermal { 7521 thermal-sensors = <&tsens2 4>; 7522 7523 trips { 7524 cpu-critical { 7525 temperature = <125000>; 7526 hysteresis = <1000>; 7527 type = "critical"; 7528 }; 7529 }; 7530 }; 7531 7532 nsp-0-0-0-thermal { 7533 thermal-sensors = <&tsens2 5>; 7534 7535 trips { 7536 nsp-critical { 7537 temperature = <125000>; 7538 hysteresis = <1000>; 7539 type = "critical"; 7540 }; 7541 }; 7542 }; 7543 7544 nsp-0-1-0-thermal { 7545 thermal-sensors = <&tsens2 6>; 7546 7547 trips { 7548 nsp-critical { 7549 temperature = <125000>; 7550 hysteresis = <1000>; 7551 type = "critical"; 7552 }; 7553 }; 7554 }; 7555 7556 nsp-0-2-0-thermal { 7557 thermal-sensors = <&tsens2 7>; 7558 7559 trips { 7560 nsp-critical { 7561 temperature = <125000>; 7562 hysteresis = <1000>; 7563 type = "critical"; 7564 }; 7565 }; 7566 }; 7567 7568 ddrss-0-thermal { 7569 thermal-sensors = <&tsens2 8>; 7570 7571 trips { 7572 ddrss-critical { 7573 temperature = <125000>; 7574 hysteresis = <1000>; 7575 type = "critical"; 7576 }; 7577 }; 7578 }; 7579 7580 cpuss-1-0-thermal { 7581 thermal-sensors = <&tsens2 9>; 7582 7583 trips { 7584 cpuss1-critical { 7585 temperature = <125000>; 7586 hysteresis = <1000>; 7587 type = "critical"; 7588 }; 7589 }; 7590 }; 7591 7592 aoss-3-thermal { 7593 thermal-sensors = <&tsens3 0>; 7594 7595 trips { 7596 aoss3-critical { 7597 temperature = <125000>; 7598 hysteresis = <1000>; 7599 type = "critical"; 7600 }; 7601 }; 7602 }; 7603 7604 cpu-1-0-1-thermal { 7605 thermal-sensors = <&tsens3 1>; 7606 7607 trips { 7608 cpu-critical { 7609 temperature = <125000>; 7610 hysteresis = <1000>; 7611 type = "critical"; 7612 }; 7613 }; 7614 }; 7615 7616 cpu-1-1-1-thermal { 7617 thermal-sensors = <&tsens3 2>; 7618 7619 trips { 7620 cpu-critical { 7621 temperature = <125000>; 7622 hysteresis = <1000>; 7623 type = "critical"; 7624 }; 7625 }; 7626 }; 7627 7628 cpu-1-2-1-thermal { 7629 thermal-sensors = <&tsens3 3>; 7630 7631 trips { 7632 cpu-critical { 7633 temperature = <125000>; 7634 hysteresis = <1000>; 7635 type = "critical"; 7636 }; 7637 }; 7638 }; 7639 7640 cpu-1-3-1-thermal { 7641 thermal-sensors = <&tsens3 4>; 7642 7643 trips { 7644 cpu-critical { 7645 temperature = <125000>; 7646 hysteresis = <1000>; 7647 type = "critical"; 7648 }; 7649 }; 7650 }; 7651 7652 nsp-0-0-1-thermal { 7653 thermal-sensors = <&tsens3 5>; 7654 7655 trips { 7656 nsp-critical { 7657 temperature = <125000>; 7658 hysteresis = <1000>; 7659 type = "critical"; 7660 }; 7661 }; 7662 }; 7663 7664 nsp-0-1-1-thermal { 7665 thermal-sensors = <&tsens3 6>; 7666 7667 trips { 7668 nsp-critical { 7669 temperature = <125000>; 7670 hysteresis = <1000>; 7671 type = "critical"; 7672 }; 7673 }; 7674 }; 7675 7676 nsp-0-2-1-thermal { 7677 thermal-sensors = <&tsens3 7>; 7678 7679 trips { 7680 nsp-critical { 7681 temperature = <125000>; 7682 hysteresis = <1000>; 7683 type = "critical"; 7684 }; 7685 }; 7686 }; 7687 7688 ddrss-1-thermal { 7689 thermal-sensors = <&tsens3 8>; 7690 7691 trips { 7692 ddrss-critical { 7693 temperature = <125000>; 7694 hysteresis = <1000>; 7695 type = "critical"; 7696 }; 7697 }; 7698 }; 7699 7700 cpuss-1-1-thermal { 7701 thermal-sensors = <&tsens3 9>; 7702 7703 trips { 7704 cpuss1-critical { 7705 temperature = <125000>; 7706 hysteresis = <1000>; 7707 type = "critical"; 7708 }; 7709 }; 7710 }; 7711 }; 7712 7713 timer { 7714 compatible = "arm,armv8-timer"; 7715 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 7716 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 7717 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 7718 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 7719 }; 7720}; 7721