1 /*
2 * Cluster Power Controller emulation
3 *
4 * Copyright (c) 2016 Imagination Technologies
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "cpu.h"
23 #include "qemu/log.h"
24 #include "qemu/module.h"
25 #include "hw/sysbus.h"
26 #include "migration/vmstate.h"
27
28 #include "hw/misc/mips_cpc.h"
29 #include "hw/qdev-properties.h"
30
cpc_vp_run_mask(MIPSCPCState * cpc)31 static inline uint64_t cpc_vp_run_mask(MIPSCPCState *cpc)
32 {
33 return (1ULL << cpc->num_vp) - 1;
34 }
35
mips_cpu_reset_async_work(CPUState * cs,run_on_cpu_data data)36 static void mips_cpu_reset_async_work(CPUState *cs, run_on_cpu_data data)
37 {
38 MIPSCPCState *cpc = (MIPSCPCState *) data.host_ptr;
39
40 cpu_reset(cs);
41 cs->halted = 0;
42 cpc->vp_running |= 1ULL << cs->cpu_index;
43 }
44
cpc_run_vp(MIPSCPCState * cpc,uint64_t vp_run)45 static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
46 {
47 CPUState *cs = first_cpu;
48
49 CPU_FOREACH(cs) {
50 uint64_t i = 1ULL << cs->cpu_index;
51 if (i & vp_run & ~cpc->vp_running) {
52 /*
53 * To avoid racing with a CPU we are just kicking off.
54 * We do the final bit of preparation for the work in
55 * the target CPUs context.
56 */
57 async_safe_run_on_cpu(cs, mips_cpu_reset_async_work,
58 RUN_ON_CPU_HOST_PTR(cpc));
59 }
60 }
61 }
62
cpc_stop_vp(MIPSCPCState * cpc,uint64_t vp_stop)63 static void cpc_stop_vp(MIPSCPCState *cpc, uint64_t vp_stop)
64 {
65 CPUState *cs = first_cpu;
66
67 CPU_FOREACH(cs) {
68 uint64_t i = 1ULL << cs->cpu_index;
69 if (i & vp_stop & cpc->vp_running) {
70 cpu_interrupt(cs, CPU_INTERRUPT_HALT);
71 cpc->vp_running &= ~i;
72 }
73 }
74 }
75
cpc_write(void * opaque,hwaddr offset,uint64_t data,unsigned size)76 static void cpc_write(void *opaque, hwaddr offset, uint64_t data,
77 unsigned size)
78 {
79 MIPSCPCState *s = opaque;
80
81 switch (offset) {
82 case CPC_CL_BASE_OFS + CPC_VP_RUN_OFS:
83 case CPC_CO_BASE_OFS + CPC_VP_RUN_OFS:
84 cpc_run_vp(s, data & cpc_vp_run_mask(s));
85 break;
86 case CPC_CL_BASE_OFS + CPC_VP_STOP_OFS:
87 case CPC_CO_BASE_OFS + CPC_VP_STOP_OFS:
88 cpc_stop_vp(s, data & cpc_vp_run_mask(s));
89 break;
90 default:
91 qemu_log_mask(LOG_UNIMP,
92 "%s: Bad offset 0x%x\n", __func__, (int)offset);
93 break;
94 }
95 }
96
cpc_read(void * opaque,hwaddr offset,unsigned size)97 static uint64_t cpc_read(void *opaque, hwaddr offset, unsigned size)
98 {
99 MIPSCPCState *s = opaque;
100
101 switch (offset) {
102 case CPC_CL_BASE_OFS + CPC_VP_RUNNING_OFS:
103 case CPC_CO_BASE_OFS + CPC_VP_RUNNING_OFS:
104 return s->vp_running;
105 default:
106 qemu_log_mask(LOG_UNIMP,
107 "%s: Bad offset 0x%x\n", __func__, (int)offset);
108 return 0;
109 }
110 }
111
112 static const MemoryRegionOps cpc_ops = {
113 .read = cpc_read,
114 .write = cpc_write,
115 .endianness = DEVICE_NATIVE_ENDIAN,
116 .impl = {
117 .max_access_size = 8,
118 },
119 };
120
mips_cpc_init(Object * obj)121 static void mips_cpc_init(Object *obj)
122 {
123 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
124 MIPSCPCState *s = MIPS_CPC(obj);
125
126 memory_region_init_io(&s->mr, OBJECT(s), &cpc_ops, s, "mips-cpc",
127 CPC_ADDRSPACE_SZ);
128 sysbus_init_mmio(sbd, &s->mr);
129 }
130
mips_cpc_realize(DeviceState * dev,Error ** errp)131 static void mips_cpc_realize(DeviceState *dev, Error **errp)
132 {
133 MIPSCPCState *s = MIPS_CPC(dev);
134
135 if (s->vp_start_running > cpc_vp_run_mask(s)) {
136 error_setg(errp,
137 "incorrect vp_start_running 0x%" PRIx64 " for num_vp = %d",
138 s->vp_running, s->num_vp);
139 return;
140 }
141 }
142
mips_cpc_reset(DeviceState * dev)143 static void mips_cpc_reset(DeviceState *dev)
144 {
145 MIPSCPCState *s = MIPS_CPC(dev);
146
147 /* Reflect the fact that all VPs are halted on reset */
148 s->vp_running = 0;
149
150 /* Put selected VPs into run state */
151 cpc_run_vp(s, s->vp_start_running);
152 }
153
154 static const VMStateDescription vmstate_mips_cpc = {
155 .name = "mips-cpc",
156 .version_id = 0,
157 .minimum_version_id = 0,
158 .fields = (const VMStateField[]) {
159 VMSTATE_UINT64(vp_running, MIPSCPCState),
160 VMSTATE_END_OF_LIST()
161 },
162 };
163
164 static const Property mips_cpc_properties[] = {
165 DEFINE_PROP_UINT32("num-vp", MIPSCPCState, num_vp, 0x1),
166 DEFINE_PROP_UINT64("vp-start-running", MIPSCPCState, vp_start_running, 0x1),
167 };
168
mips_cpc_class_init(ObjectClass * klass,const void * data)169 static void mips_cpc_class_init(ObjectClass *klass, const void *data)
170 {
171 DeviceClass *dc = DEVICE_CLASS(klass);
172
173 dc->realize = mips_cpc_realize;
174 device_class_set_legacy_reset(dc, mips_cpc_reset);
175 dc->vmsd = &vmstate_mips_cpc;
176 device_class_set_props(dc, mips_cpc_properties);
177 }
178
179 static const TypeInfo mips_cpc_info = {
180 .name = TYPE_MIPS_CPC,
181 .parent = TYPE_SYS_BUS_DEVICE,
182 .instance_size = sizeof(MIPSCPCState),
183 .instance_init = mips_cpc_init,
184 .class_init = mips_cpc_class_init,
185 };
186
mips_cpc_register_types(void)187 static void mips_cpc_register_types(void)
188 {
189 type_register_static(&mips_cpc_info);
190 }
191
192 type_init(mips_cpc_register_types)
193