1 /*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * License Terms: GNU General Public License v2
6 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
7 *
8 * PRCMU f/w APIs
9 */
10 #ifndef __MFD_DB8500_PRCMU_H
11 #define __MFD_DB8500_PRCMU_H
12
13 #include <linux/interrupt.h>
14
15 /* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
16
17 /**
18 * enum state - ON/OFF state definition
19 * @OFF: State is ON
20 * @ON: State is OFF
21 *
22 */
23 enum state {
24 OFF = 0x0,
25 ON = 0x1,
26 };
27
28 /**
29 * enum ret_state - general purpose On/Off/Retention states
30 *
31 */
32 enum ret_state {
33 OFFST = 0,
34 ONST = 1,
35 RETST = 2
36 };
37
38 /**
39 * enum clk_arm - ARM Cortex A9 clock schemes
40 * @A9_OFF:
41 * @A9_BOOT:
42 * @A9_OPPT1:
43 * @A9_OPPT2:
44 * @A9_EXTCLK:
45 */
46 enum clk_arm {
47 A9_OFF,
48 A9_BOOT,
49 A9_OPPT1,
50 A9_OPPT2,
51 A9_EXTCLK
52 };
53
54 /**
55 * enum clk_gen - GEN#0/GEN#1 clock schemes
56 * @GEN_OFF:
57 * @GEN_BOOT:
58 * @GEN_OPPT1:
59 */
60 enum clk_gen {
61 GEN_OFF,
62 GEN_BOOT,
63 GEN_OPPT1,
64 };
65
66 /* some information between arm and xp70 */
67
68 /**
69 * enum romcode_write - Romcode message written by A9 AND read by XP70
70 * @RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70
71 * @RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the
72 * romcode. The xp70 will go into self-reset
73 */
74 enum romcode_write {
75 RDY_2_DS = 0x09,
76 RDY_2_XP70_RST = 0x10
77 };
78
79 /**
80 * enum romcode_read - Romcode message written by XP70 and read by A9
81 * @INIT: Init value when romcode field is not used
82 * @FS_2_DS: Value set when power state is going from ApExecute to
83 * ApDeepSleep
84 * @END_DS: Value set when ApDeepSleep power state is reached coming from
85 * ApExecute state
86 * @DS_TO_FS: Value set when power state is going from ApDeepSleep to
87 * ApExecute
88 * @END_FS: Value set when ApExecute power state is reached coming from
89 * ApDeepSleep state
90 * @SWR: Value set when power state is going to ApReset
91 * @END_SWR: Value set when the xp70 finished executing ApReset actions and
92 * waits for romcode acknowledgment to go to self-reset
93 */
94 enum romcode_read {
95 INIT = 0x00,
96 FS_2_DS = 0x0A,
97 END_DS = 0x0B,
98 DS_TO_FS = 0x0C,
99 END_FS = 0x0D,
100 SWR = 0x0E,
101 END_SWR = 0x0F
102 };
103
104 /**
105 * enum ap_pwrst - current power states defined in PRCMU firmware
106 * @NO_PWRST: Current power state init
107 * @AP_BOOT: Current power state is apBoot
108 * @AP_EXECUTE: Current power state is apExecute
109 * @AP_DEEP_SLEEP: Current power state is apDeepSleep
110 * @AP_SLEEP: Current power state is apSleep
111 * @AP_IDLE: Current power state is apIdle
112 * @AP_RESET: Current power state is apReset
113 */
114 enum ap_pwrst {
115 NO_PWRST = 0x00,
116 AP_BOOT = 0x01,
117 AP_EXECUTE = 0x02,
118 AP_DEEP_SLEEP = 0x03,
119 AP_SLEEP = 0x04,
120 AP_IDLE = 0x05,
121 AP_RESET = 0x06
122 };
123
124 /**
125 * enum ap_pwrst_trans - Transition states defined in PRCMU firmware
126 * @NO_TRANSITION: No power state transition
127 * @APEXECUTE_TO_APSLEEP: Power state transition from ApExecute to ApSleep
128 * @APIDLE_TO_APSLEEP: Power state transition from ApIdle to ApSleep
129 * @APBOOT_TO_APEXECUTE: Power state transition from ApBoot to ApExecute
130 * @APEXECUTE_TO_APDEEPSLEEP: Power state transition from ApExecute to
131 * ApDeepSleep
132 * @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle
133 */
134 enum ap_pwrst_trans {
135 PRCMU_AP_NO_CHANGE = 0x00,
136 APEXECUTE_TO_APSLEEP = 0x01,
137 APIDLE_TO_APSLEEP = 0x02, /* To be removed */
138 PRCMU_AP_SLEEP = 0x01,
139 APBOOT_TO_APEXECUTE = 0x03,
140 APEXECUTE_TO_APDEEPSLEEP = 0x04, /* To be removed */
141 PRCMU_AP_DEEP_SLEEP = 0x04,
142 APEXECUTE_TO_APIDLE = 0x05, /* To be removed */
143 PRCMU_AP_IDLE = 0x05,
144 PRCMU_AP_DEEP_IDLE = 0x07,
145 };
146
147 /**
148 * enum hw_acc_state - State definition for hardware accelerator
149 * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
150 * @HW_OFF: The hardware accelerator must be switched off
151 * @HW_OFF_RAMRET: The hardware accelerator must be switched off with its
152 * internal RAM in retention
153 * @HW_ON: The hwa hardware accelerator hwa must be switched on
154 *
155 * NOTE! Deprecated, to be removed when all users switched over to use the
156 * regulator API.
157 */
158 enum hw_acc_state {
159 HW_NO_CHANGE = 0x00,
160 HW_OFF = 0x01,
161 HW_OFF_RAMRET = 0x02,
162 HW_ON = 0x04
163 };
164
165 /**
166 * enum mbox_2_arm_stat - Status messages definition for mbox_arm
167 * @BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been
168 * completed
169 * @DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been
170 * completed
171 * @SLEEPOK: The apExecute to apSleep state transition has been completed
172 * @IDLEOK: The apExecute to apIdle state transition has been completed
173 * @SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed
174 * @SOFTRESETGO : The A9 watchdog/SoftReset state is on going
175 * @BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going
176 * @EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on
177 * going
178 * @DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on
179 * going
180 * @DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has
181 * been completed
182 * @EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going
183 * @SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going
184 * @SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been
185 * completed
186 * @EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going
187 * @IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going
188 * @IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been
189 * completed
190 * @INIT_STATUS: Status init
191 */
192 enum ap_pwrsttr_status {
193 BOOT_TO_EXECUTEOK = 0xFF,
194 DEEPSLEEPOK = 0xFE,
195 SLEEPOK = 0xFD,
196 IDLEOK = 0xFC,
197 SOFTRESETOK = 0xFB,
198 SOFTRESETGO = 0xFA,
199 BOOT_TO_EXECUTE = 0xF9,
200 EXECUTE_TO_DEEPSLEEP = 0xF8,
201 DEEPSLEEP_TO_EXECUTE = 0xF7,
202 DEEPSLEEP_TO_EXECUTEOK = 0xF6,
203 EXECUTE_TO_SLEEP = 0xF5,
204 SLEEP_TO_EXECUTE = 0xF4,
205 SLEEP_TO_EXECUTEOK = 0xF3,
206 EXECUTE_TO_IDLE = 0xF2,
207 IDLE_TO_EXECUTE = 0xF1,
208 IDLE_TO_EXECUTEOK = 0xF0,
209 RDYTODS_RETURNTOEXE = 0xEF,
210 NORDYTODS_RETURNTOEXE = 0xEE,
211 EXETOSLEEP_RETURNTOEXE = 0xED,
212 EXETOIDLE_RETURNTOEXE = 0xEC,
213 INIT_STATUS = 0xEB,
214
215 /*error messages */
216 INITERROR = 0x00,
217 PLLARMLOCKP_ER = 0x01,
218 PLLDDRLOCKP_ER = 0x02,
219 PLLSOCLOCKP_ER = 0x03,
220 PLLSOCK1LOCKP_ER = 0x04,
221 ARMWFI_ER = 0x05,
222 SYSCLKOK_ER = 0x06,
223 I2C_NACK_DATA_ER = 0x07,
224 BOOT_ER = 0x08,
225 I2C_STATUS_ALWAYS_1 = 0x0A,
226 I2C_NACK_REG_ADDR_ER = 0x0B,
227 I2C_NACK_DATA0123_ER = 0x1B,
228 I2C_NACK_ADDR_ER = 0x1F,
229 CURAPPWRSTISNOT_BOOT = 0x20,
230 CURAPPWRSTISNOT_EXECUTE = 0x21,
231 CURAPPWRSTISNOT_SLEEPMODE = 0x22,
232 CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23,
233 FIFO4500WUISNOT_WUPEVENT = 0x24,
234 PLL32KLOCKP_ER = 0x29,
235 DDRDEEPSLEEPOK_ER = 0x2A,
236 ROMCODEREADY_ER = 0x50,
237 WUPBEFOREDS = 0x51,
238 DDRCONFIG_ER = 0x52,
239 WUPBEFORESLEEP = 0x53,
240 WUPBEFOREIDLE = 0x54
241 }; /* earlier called as mbox_2_arm_stat */
242
243 /**
244 * enum dvfs_stat - DVFS status messages definition
245 * @DVFS_GO: A state transition DVFS is on going
246 * @DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP
247 * @DVFS_ARM50OPPOK: The state transition DVFS has been completed for 50OPP
248 * @DVFS_ARMEXTCLKOK: The state transition DVFS has been completed for EXTCLK
249 * @DVFS_NOCHGTCLKOK: The state transition DVFS has been completed for
250 * NOCHGCLK
251 * @DVFS_INITSTATUS: Value init
252 */
253 enum dvfs_stat {
254 DVFS_GO = 0xFF,
255 DVFS_ARM100OPPOK = 0xFE,
256 DVFS_ARM50OPPOK = 0xFD,
257 DVFS_ARMEXTCLKOK = 0xFC,
258 DVFS_NOCHGTCLKOK = 0xFB,
259 DVFS_INITSTATUS = 0x00
260 };
261
262 /**
263 * enum sva_mmdsp_stat - SVA MMDSP status messages
264 * @SVA_MMDSP_GO: SVAMMDSP interrupt has happened
265 * @SVA_MMDSP_INIT: Status init
266 */
267 enum sva_mmdsp_stat {
268 SVA_MMDSP_GO = 0xFF,
269 SVA_MMDSP_INIT = 0x00
270 };
271
272 /**
273 * enum sia_mmdsp_stat - SIA MMDSP status messages
274 * @SIA_MMDSP_GO: SIAMMDSP interrupt has happened
275 * @SIA_MMDSP_INIT: Status init
276 */
277 enum sia_mmdsp_stat {
278 SIA_MMDSP_GO = 0xFF,
279 SIA_MMDSP_INIT = 0x00
280 };
281
282 /**
283 * enum mbox_to_arm_err - Error messages definition
284 * @INIT_ERR: Init value
285 * @PLLARMLOCKP_ERR: PLLARM has not been correctly locked in given time
286 * @PLLDDRLOCKP_ERR: PLLDDR has not been correctly locked in the given time
287 * @PLLSOC0LOCKP_ERR: PLLSOC0 has not been correctly locked in the given time
288 * @PLLSOC1LOCKP_ERR: PLLSOC1 has not been correctly locked in the given time
289 * @ARMWFI_ERR: The ARM WFI has not been correctly executed in the given time
290 * @SYSCLKOK_ERR: The SYSCLK is not available in the given time
291 * @BOOT_ERR: Romcode has not validated the XP70 self reset in the given time
292 * @ROMCODESAVECONTEXT: The Romcode didn.t correctly save it secure context
293 * @VARMHIGHSPEEDVALTO_ERR: The ARM high speed supply value transfered
294 * through I2C has not been correctly executed in the given time
295 * @VARMHIGHSPEEDACCESS_ERR: The command value of VarmHighSpeedVal transfered
296 * through I2C has not been correctly executed in the given time
297 * @VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through
298 * I2C has not been correctly executed in the given time
299 * @VARMLOWSPEEDACCESS_ERR: The command value of VarmLowSpeedVal transfered
300 * through I2C has not been correctly executed in the given time
301 * @VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through
302 * I2C has not been correctly executed in the given time
303 * @VARMRETENTIONACCESS_ERR: The command value of VarmRetentionVal transfered
304 * through I2C has not been correctly executed in the given time
305 * @VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through
306 * I2C has not been correctly executed in the given time
307 * @VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C
308 * has not been correctly executed in the given time
309 * @VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has
310 * not been correctly executed in the given time
311 * @VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has
312 * not been correctly executed in the given time
313 * @VARMOFFACCESS_ERR: The command value of Varm ON/OFF transfered through
314 * I2C has not been correctly executed in the given time
315 * @VAPEOFFACCESS_ERR: The command value of Vape ON/OFF transfered through
316 * I2C has not been correctly executed in the given time
317 * @VARMRETACCES_ERR: The command value of Varm retention ON/OFF transfered
318 * through I2C has not been correctly executed in the given time
319 * @CURAPPWRSTISNOTBOOT:Generated when Arm want to do power state transition
320 * ApBoot to ApExecute but the power current state is not Apboot
321 * @CURAPPWRSTISNOTEXECUTE: Generated when Arm want to do power state
322 * transition from ApExecute to others power state but the
323 * power current state is not ApExecute
324 * @CURAPPWRSTISNOTSLEEPMODE: Generated when wake up events are transmitted
325 * but the power current state is not ApDeepSleep/ApSleep/ApIdle
326 * @CURAPPWRSTISNOTCORRECTDBG: Generated when wake up events are transmitted
327 * but the power current state is not correct
328 * @ARMREGU1VALTO_ERR:The ArmRegu1 value transferred through I2C has not
329 * been correctly executed in the given time
330 * @ARMREGU2VALTO_ERR: The ArmRegu2 value transferred through I2C has not
331 * been correctly executed in the given time
332 * @VAPEREGUVALTO_ERR: The VApeRegu value transfered through I2C has not
333 * been correctly executed in the given time
334 * @VSMPS3REGUVALTO_ERR: The VSmps3Regu value transfered through I2C has not
335 * been correctly executed in the given time
336 * @VMODREGUVALTO_ERR: The VModemRegu value transfered through I2C has not
337 * been correctly executed in the given time
338 */
339 enum mbox_to_arm_err {
340 INIT_ERR = 0x00,
341 PLLARMLOCKP_ERR = 0x01,
342 PLLDDRLOCKP_ERR = 0x02,
343 PLLSOC0LOCKP_ERR = 0x03,
344 PLLSOC1LOCKP_ERR = 0x04,
345 ARMWFI_ERR = 0x05,
346 SYSCLKOK_ERR = 0x06,
347 BOOT_ERR = 0x07,
348 ROMCODESAVECONTEXT = 0x08,
349 VARMHIGHSPEEDVALTO_ERR = 0x10,
350 VARMHIGHSPEEDACCESS_ERR = 0x11,
351 VARMLOWSPEEDVALTO_ERR = 0x12,
352 VARMLOWSPEEDACCESS_ERR = 0x13,
353 VARMRETENTIONVALTO_ERR = 0x14,
354 VARMRETENTIONACCESS_ERR = 0x15,
355 VAPEHIGHSPEEDVALTO_ERR = 0x16,
356 VSAFEHPVALTO_ERR = 0x17,
357 VMODSEL1VALTO_ERR = 0x18,
358 VMODSEL2VALTO_ERR = 0x19,
359 VARMOFFACCESS_ERR = 0x1A,
360 VAPEOFFACCESS_ERR = 0x1B,
361 VARMRETACCES_ERR = 0x1C,
362 CURAPPWRSTISNOTBOOT = 0x20,
363 CURAPPWRSTISNOTEXECUTE = 0x21,
364 CURAPPWRSTISNOTSLEEPMODE = 0x22,
365 CURAPPWRSTISNOTCORRECTDBG = 0x23,
366 ARMREGU1VALTO_ERR = 0x24,
367 ARMREGU2VALTO_ERR = 0x25,
368 VAPEREGUVALTO_ERR = 0x26,
369 VSMPS3REGUVALTO_ERR = 0x27,
370 VMODREGUVALTO_ERR = 0x28
371 };
372
373 enum hw_acc {
374 SVAMMDSP = 0,
375 SVAPIPE = 1,
376 SIAMMDSP = 2,
377 SIAPIPE = 3,
378 SGA = 4,
379 B2R2MCDE = 5,
380 ESRAM12 = 6,
381 ESRAM34 = 7,
382 };
383
384 enum cs_pwrmgt {
385 PWRDNCS0 = 0,
386 WKUPCS0 = 1,
387 PWRDNCS1 = 2,
388 WKUPCS1 = 3
389 };
390
391 /* Defs related to autonomous power management */
392
393 /**
394 * enum sia_sva_pwr_policy - Power policy
395 * @NO_CHGT: No change
396 * @DSPOFF_HWPOFF:
397 * @DSPOFFRAMRET_HWPOFF:
398 * @DSPCLKOFF_HWPOFF:
399 * @DSPCLKOFF_HWPCLKOFF:
400 *
401 */
402 enum sia_sva_pwr_policy {
403 NO_CHGT = 0x0,
404 DSPOFF_HWPOFF = 0x1,
405 DSPOFFRAMRET_HWPOFF = 0x2,
406 DSPCLKOFF_HWPOFF = 0x3,
407 DSPCLKOFF_HWPCLKOFF = 0x4,
408 };
409
410 /**
411 * enum auto_enable - Auto Power enable
412 * @AUTO_OFF:
413 * @AUTO_ON:
414 *
415 */
416 enum auto_enable {
417 AUTO_OFF = 0x0,
418 AUTO_ON = 0x1,
419 };
420
421 /* End of file previously known as prcmu-fw-defs_v1.h */
422
423 /**
424 * enum hw_acc_dev - enum for hw accelerators
425 * @HW_ACC_SVAMMDSP: for SVAMMDSP
426 * @HW_ACC_SVAPIPE: for SVAPIPE
427 * @HW_ACC_SIAMMDSP: for SIAMMDSP
428 * @HW_ACC_SIAPIPE: for SIAPIPE
429 * @HW_ACC_SGA: for SGA
430 * @HW_ACC_B2R2: for B2R2
431 * @HW_ACC_MCDE: for MCDE
432 * @HW_ACC_ESRAM1: for ESRAM1
433 * @HW_ACC_ESRAM2: for ESRAM2
434 * @HW_ACC_ESRAM3: for ESRAM3
435 * @HW_ACC_ESRAM4: for ESRAM4
436 * @NUM_HW_ACC: number of hardware accelerators
437 *
438 * Different hw accelerators which can be turned ON/
439 * OFF or put into retention (MMDSPs and ESRAMs).
440 * Used with EPOD API.
441 *
442 * NOTE! Deprecated, to be removed when all users switched over to use the
443 * regulator API.
444 */
445 enum hw_acc_dev {
446 HW_ACC_SVAMMDSP,
447 HW_ACC_SVAPIPE,
448 HW_ACC_SIAMMDSP,
449 HW_ACC_SIAPIPE,
450 HW_ACC_SGA,
451 HW_ACC_B2R2,
452 HW_ACC_MCDE,
453 HW_ACC_ESRAM1,
454 HW_ACC_ESRAM2,
455 HW_ACC_ESRAM3,
456 HW_ACC_ESRAM4,
457 NUM_HW_ACC
458 };
459
460 /*
461 * Definitions for autonomous power management configuration.
462 */
463
464 #define PRCMU_AUTO_PM_OFF 0
465 #define PRCMU_AUTO_PM_ON 1
466
467 #define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0)
468 #define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1)
469
470 enum prcmu_auto_pm_policy {
471 PRCMU_AUTO_PM_POLICY_NO_CHANGE,
472 PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF,
473 PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF,
474 PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF,
475 PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF,
476 };
477
478 /**
479 * struct prcmu_auto_pm_config - Autonomous power management configuration.
480 * @sia_auto_pm_enable: SIA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
481 * @sia_power_on: SIA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
482 * @sia_policy: SIA power policy. (enum prcmu_auto_pm_policy)
483 * @sva_auto_pm_enable: SVA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
484 * @sva_power_on: SVA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
485 * @sva_policy: SVA power policy. (enum prcmu_auto_pm_policy)
486 */
487 struct prcmu_auto_pm_config {
488 u8 sia_auto_pm_enable;
489 u8 sia_power_on;
490 u8 sia_policy;
491 u8 sva_auto_pm_enable;
492 u8 sva_power_on;
493 u8 sva_policy;
494 };
495
496 #ifdef CONFIG_MFD_DB8500_PRCMU
497
498 void db8500_prcmu_early_init(void);
499 int prcmu_set_rc_a2p(enum romcode_write);
500 enum romcode_read prcmu_get_rc_p2a(void);
501 enum ap_pwrst prcmu_get_xp70_current_state(void);
502 bool prcmu_has_arm_maxopp(void);
503 bool prcmu_is_u8400(void);
504 int prcmu_set_ape_opp(u8 opp);
505 int prcmu_get_ape_opp(void);
506 int prcmu_request_ape_opp_100_voltage(bool enable);
507 int prcmu_release_usb_wakeup_state(void);
508 int prcmu_set_ddr_opp(u8 opp);
509 int prcmu_get_ddr_opp(void);
510 /* NOTE! Use regulator framework instead */
511 int prcmu_set_hwacc(u16 hw_acc_dev, u8 state);
512 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
513 struct prcmu_auto_pm_config *idle);
514 bool prcmu_is_auto_pm_enabled(void);
515
516 int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
517 int prcmu_set_clock_divider(u8 clock, u8 divider);
518 int prcmu_config_hotdog(u8 threshold);
519 int prcmu_config_hotmon(u8 low, u8 high);
520 int prcmu_start_temp_sense(u16 cycles32k);
521 int prcmu_stop_temp_sense(void);
522 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
523 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
524
525 void prcmu_ac_wake_req(void);
526 void prcmu_ac_sleep_req(void);
527 void prcmu_modem_reset(void);
528 void prcmu_enable_spi2(void);
529 void prcmu_disable_spi2(void);
530
531 int prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
532 int prcmu_enable_a9wdog(u8 id);
533 int prcmu_disable_a9wdog(u8 id);
534 int prcmu_kick_a9wdog(u8 id);
535 int prcmu_load_a9wdog(u8 id, u32 val);
536
537 void db8500_prcmu_system_reset(u16 reset_code);
538 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
539 void db8500_prcmu_enable_wakeups(u32 wakeups);
540 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
541 int db8500_prcmu_request_clock(u8 clock, bool enable);
542 int db8500_prcmu_set_display_clocks(void);
543 int db8500_prcmu_disable_dsipll(void);
544 int db8500_prcmu_enable_dsipll(void);
545 void db8500_prcmu_config_abb_event_readout(u32 abb_events);
546 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf);
547 int db8500_prcmu_config_esram0_deep_sleep(u8 state);
548 u16 db8500_prcmu_get_reset_code(void);
549 bool db8500_prcmu_is_ac_wake_requested(void);
550 int db8500_prcmu_set_arm_opp(u8 opp);
551 int db8500_prcmu_get_arm_opp(void);
552
553 #else /* !CONFIG_MFD_DB8500_PRCMU */
554
db8500_prcmu_early_init(void)555 static inline void db8500_prcmu_early_init(void) {}
556
prcmu_set_rc_a2p(enum romcode_write code)557 static inline int prcmu_set_rc_a2p(enum romcode_write code)
558 {
559 return 0;
560 }
561
prcmu_get_rc_p2a(void)562 static inline enum romcode_read prcmu_get_rc_p2a(void)
563 {
564 return INIT;
565 }
566
prcmu_get_xp70_current_state(void)567 static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
568 {
569 return AP_EXECUTE;
570 }
571
prcmu_has_arm_maxopp(void)572 static inline bool prcmu_has_arm_maxopp(void)
573 {
574 return false;
575 }
576
prcmu_is_u8400(void)577 static inline bool prcmu_is_u8400(void)
578 {
579 return false;
580 }
581
prcmu_set_ape_opp(u8 opp)582 static inline int prcmu_set_ape_opp(u8 opp)
583 {
584 return 0;
585 }
586
prcmu_get_ape_opp(void)587 static inline int prcmu_get_ape_opp(void)
588 {
589 return APE_100_OPP;
590 }
591
prcmu_request_ape_opp_100_voltage(bool enable)592 static inline int prcmu_request_ape_opp_100_voltage(bool enable)
593 {
594 return 0;
595 }
596
prcmu_release_usb_wakeup_state(void)597 static inline int prcmu_release_usb_wakeup_state(void)
598 {
599 return 0;
600 }
601
prcmu_set_ddr_opp(u8 opp)602 static inline int prcmu_set_ddr_opp(u8 opp)
603 {
604 return 0;
605 }
606
prcmu_get_ddr_opp(void)607 static inline int prcmu_get_ddr_opp(void)
608 {
609 return DDR_100_OPP;
610 }
611
prcmu_set_hwacc(u16 hw_acc_dev,u8 state)612 static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state)
613 {
614 return 0;
615 }
616
prcmu_configure_auto_pm(struct prcmu_auto_pm_config * sleep,struct prcmu_auto_pm_config * idle)617 static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
618 struct prcmu_auto_pm_config *idle)
619 {
620 }
621
prcmu_is_auto_pm_enabled(void)622 static inline bool prcmu_is_auto_pm_enabled(void)
623 {
624 return false;
625 }
626
prcmu_config_clkout(u8 clkout,u8 source,u8 div)627 static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
628 {
629 return 0;
630 }
631
prcmu_set_clock_divider(u8 clock,u8 divider)632 static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
633 {
634 return 0;
635 }
636
prcmu_config_hotdog(u8 threshold)637 static inline int prcmu_config_hotdog(u8 threshold)
638 {
639 return 0;
640 }
641
prcmu_config_hotmon(u8 low,u8 high)642 static inline int prcmu_config_hotmon(u8 low, u8 high)
643 {
644 return 0;
645 }
646
prcmu_start_temp_sense(u16 cycles32k)647 static inline int prcmu_start_temp_sense(u16 cycles32k)
648 {
649 return 0;
650 }
651
prcmu_stop_temp_sense(void)652 static inline int prcmu_stop_temp_sense(void)
653 {
654 return 0;
655 }
656
prcmu_abb_read(u8 slave,u8 reg,u8 * value,u8 size)657 static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
658 {
659 return -ENOSYS;
660 }
661
prcmu_abb_write(u8 slave,u8 reg,u8 * value,u8 size)662 static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
663 {
664 return -ENOSYS;
665 }
666
prcmu_ac_wake_req(void)667 static inline void prcmu_ac_wake_req(void) {}
668
prcmu_ac_sleep_req(void)669 static inline void prcmu_ac_sleep_req(void) {}
670
prcmu_modem_reset(void)671 static inline void prcmu_modem_reset(void) {}
672
prcmu_enable_spi2(void)673 static inline int prcmu_enable_spi2(void)
674 {
675 return 0;
676 }
677
prcmu_disable_spi2(void)678 static inline int prcmu_disable_spi2(void)
679 {
680 return 0;
681 }
682
db8500_prcmu_system_reset(u16 reset_code)683 static inline void db8500_prcmu_system_reset(u16 reset_code) {}
684
db8500_prcmu_set_power_state(u8 state,bool keep_ulp_clk,bool keep_ap_pll)685 static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
686 bool keep_ap_pll)
687 {
688 return 0;
689 }
690
db8500_prcmu_enable_wakeups(u32 wakeups)691 static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
692
db8500_prcmu_set_epod(u16 epod_id,u8 epod_state)693 static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
694 {
695 return 0;
696 }
697
db8500_prcmu_request_clock(u8 clock,bool enable)698 static inline int db8500_prcmu_request_clock(u8 clock, bool enable)
699 {
700 return 0;
701 }
702
db8500_prcmu_set_display_clocks(void)703 static inline int db8500_prcmu_set_display_clocks(void)
704 {
705 return 0;
706 }
707
db8500_prcmu_disable_dsipll(void)708 static inline int db8500_prcmu_disable_dsipll(void)
709 {
710 return 0;
711 }
712
db8500_prcmu_enable_dsipll(void)713 static inline int db8500_prcmu_enable_dsipll(void)
714 {
715 return 0;
716 }
717
db8500_prcmu_config_esram0_deep_sleep(u8 state)718 static inline int db8500_prcmu_config_esram0_deep_sleep(u8 state)
719 {
720 return 0;
721 }
722
db8500_prcmu_config_abb_event_readout(u32 abb_events)723 static inline void db8500_prcmu_config_abb_event_readout(u32 abb_events) {}
724
db8500_prcmu_get_abb_event_buffer(void __iomem ** buf)725 static inline void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
726
db8500_prcmu_get_reset_code(void)727 static inline u16 db8500_prcmu_get_reset_code(void)
728 {
729 return 0;
730 }
731
prcmu_config_a9wdog(u8 num,bool sleep_auto_off)732 static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
733 {
734 return 0;
735 }
736
prcmu_enable_a9wdog(u8 id)737 static inline int prcmu_enable_a9wdog(u8 id)
738 {
739 return 0;
740 }
741
prcmu_disable_a9wdog(u8 id)742 static inline int prcmu_disable_a9wdog(u8 id)
743 {
744 return 0;
745 }
746
prcmu_kick_a9wdog(u8 id)747 static inline int prcmu_kick_a9wdog(u8 id)
748 {
749 return 0;
750 }
751
prcmu_load_a9wdog(u8 id,u32 val)752 static inline int prcmu_load_a9wdog(u8 id, u32 val)
753 {
754 return 0;
755 }
756
db8500_prcmu_is_ac_wake_requested(void)757 static inline bool db8500_prcmu_is_ac_wake_requested(void)
758 {
759 return 0;
760 }
761
db8500_prcmu_set_arm_opp(u8 opp)762 static inline int db8500_prcmu_set_arm_opp(u8 opp)
763 {
764 return 0;
765 }
766
db8500_prcmu_get_arm_opp(void)767 static inline int db8500_prcmu_get_arm_opp(void)
768 {
769 return 0;
770 }
771
772 #endif /* !CONFIG_MFD_DB8500_PRCMU */
773
774 #endif /* __MFD_DB8500_PRCMU_H */
775