1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2019 HiSilicon Limited. */
3 #ifndef HISI_ACC_QM_H
4 #define HISI_ACC_QM_H
5
6 #include <linux/bitfield.h>
7 #include <linux/debugfs.h>
8 #include <linux/iopoll.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11
12 #define QM_QNUM_V1 4096
13 #define QM_QNUM_V2 1024
14 #define QM_MAX_VFS_NUM_V2 63
15
16 /* qm user domain */
17 #define QM_ARUSER_M_CFG_1 0x100088
18 #define AXUSER_SNOOP_ENABLE BIT(30)
19 #define AXUSER_CMD_TYPE GENMASK(14, 12)
20 #define AXUSER_CMD_SMMU_NORMAL 1
21 #define AXUSER_NS BIT(6)
22 #define AXUSER_NO BIT(5)
23 #define AXUSER_FP BIT(4)
24 #define AXUSER_SSV BIT(0)
25 #define AXUSER_BASE (AXUSER_SNOOP_ENABLE | \
26 FIELD_PREP(AXUSER_CMD_TYPE, \
27 AXUSER_CMD_SMMU_NORMAL) | \
28 AXUSER_NS | AXUSER_NO | AXUSER_FP)
29 #define QM_ARUSER_M_CFG_ENABLE 0x100090
30 #define ARUSER_M_CFG_ENABLE 0xfffffffe
31 #define QM_AWUSER_M_CFG_1 0x100098
32 #define QM_AWUSER_M_CFG_ENABLE 0x1000a0
33 #define AWUSER_M_CFG_ENABLE 0xfffffffe
34 #define QM_WUSER_M_CFG_ENABLE 0x1000a8
35 #define WUSER_M_CFG_ENABLE 0xffffffff
36
37 /* mailbox */
38 #define QM_MB_CMD_SQC 0x0
39 #define QM_MB_CMD_CQC 0x1
40 #define QM_MB_CMD_EQC 0x2
41 #define QM_MB_CMD_AEQC 0x3
42 #define QM_MB_CMD_SQC_BT 0x4
43 #define QM_MB_CMD_CQC_BT 0x5
44 #define QM_MB_CMD_SQC_VFT_V2 0x6
45 #define QM_MB_CMD_STOP_QP 0x8
46 #define QM_MB_CMD_FLUSH_QM 0x9
47 #define QM_MB_CMD_SRC 0xc
48 #define QM_MB_CMD_DST 0xd
49
50 #define QM_MB_CMD_SEND_BASE 0x300
51 #define QM_MB_EVENT_SHIFT 8
52 #define QM_MB_BUSY_SHIFT 13
53 #define QM_MB_OP_SHIFT 14
54 #define QM_MB_CMD_DATA_ADDR_L 0x304
55 #define QM_MB_CMD_DATA_ADDR_H 0x308
56 #define QM_MB_MAX_WAIT_CNT 6000
57
58 /* doorbell */
59 #define QM_DOORBELL_CMD_SQ 0
60 #define QM_DOORBELL_CMD_CQ 1
61 #define QM_DOORBELL_CMD_EQ 2
62 #define QM_DOORBELL_CMD_AEQ 3
63
64 #define QM_DOORBELL_SQ_CQ_BASE_V2 0x1000
65 #define QM_DOORBELL_EQ_AEQ_BASE_V2 0x2000
66 #define QM_QP_MAX_NUM_SHIFT 11
67 #define QM_DB_CMD_SHIFT_V2 12
68 #define QM_DB_RAND_SHIFT_V2 16
69 #define QM_DB_INDEX_SHIFT_V2 32
70 #define QM_DB_PRIORITY_SHIFT_V2 48
71 #define QM_VF_STATE 0x60
72
73 /* qm cache */
74 #define QM_CACHE_CTL 0x100050
75 #define SQC_CACHE_ENABLE BIT(0)
76 #define CQC_CACHE_ENABLE BIT(1)
77 #define SQC_CACHE_WB_ENABLE BIT(4)
78 #define SQC_CACHE_WB_THRD GENMASK(10, 5)
79 #define CQC_CACHE_WB_ENABLE BIT(11)
80 #define CQC_CACHE_WB_THRD GENMASK(17, 12)
81 #define QM_AXI_M_CFG 0x1000ac
82 #define AXI_M_CFG 0xffff
83 #define QM_AXI_M_CFG_ENABLE 0x1000b0
84 #define AM_CFG_SINGLE_PORT_MAX_TRANS 0x300014
85 #define AXI_M_CFG_ENABLE 0xffffffff
86 #define QM_PEH_AXUSER_CFG 0x1000cc
87 #define QM_PEH_AXUSER_CFG_ENABLE 0x1000d0
88 #define PEH_AXUSER_CFG 0x401001
89 #define PEH_AXUSER_CFG_ENABLE 0xffffffff
90
91 #define QM_MIN_QNUM 2
92 #define HISI_ACC_SGL_SGE_NR_MAX 255
93 #define QM_SHAPER_CFG 0x100164
94 #define QM_SHAPER_ENABLE BIT(30)
95 #define QM_SHAPER_TYPE1_OFFSET 10
96
97 /* page number for queue file region */
98 #define QM_DOORBELL_PAGE_NR 1
99
100 #define QM_DEV_ALG_MAX_LEN 256
101
102 /* uacce mode of the driver */
103 #define UACCE_MODE_NOUACCE 0 /* don't use uacce */
104 #define UACCE_MODE_SVA 1 /* use uacce sva mode */
105 #define UACCE_MODE_DESC "0(default) means only register to crypto, 1 means both register to crypto and uacce"
106
107 #define QM_ECC_MBIT BIT(2)
108
109 enum qm_stop_reason {
110 QM_NORMAL,
111 QM_SOFT_RESET,
112 QM_DOWN,
113 };
114
115 enum qm_state {
116 QM_WORK = 0,
117 QM_STOP,
118 };
119
120 enum qp_state {
121 QP_START = 1,
122 QP_STOP,
123 };
124
125 enum qm_hw_ver {
126 QM_HW_V1 = 0x20,
127 QM_HW_V2 = 0x21,
128 QM_HW_V3 = 0x30,
129 QM_HW_V4 = 0x50,
130 QM_HW_V5 = 0x51,
131 };
132
133 enum qm_fun_type {
134 QM_HW_PF,
135 QM_HW_VF,
136 };
137
138 enum qm_debug_file {
139 CURRENT_QM,
140 CURRENT_Q,
141 CLEAR_ENABLE,
142 DEBUG_FILE_NUM,
143 };
144
145 enum qm_vf_state {
146 QM_READY = 0,
147 QM_NOT_READY,
148 };
149
150 enum qm_misc_ctl_bits {
151 QM_DRIVER_REMOVING = 0x0,
152 QM_RST_SCHED,
153 QM_RESETTING,
154 QM_MODULE_PARAM,
155 };
156
157 enum qm_cap_bits {
158 QM_SUPPORT_DB_ISOLATION = 0x0,
159 QM_SUPPORT_FUNC_QOS,
160 QM_SUPPORT_STOP_QP,
161 QM_SUPPORT_STOP_FUNC,
162 QM_SUPPORT_MB_COMMAND,
163 QM_SUPPORT_SVA_PREFETCH,
164 QM_SUPPORT_RPM,
165 QM_SUPPORT_DAE,
166 };
167
168 struct qm_dev_alg {
169 u64 alg_msk;
170 const char *alg;
171 };
172
173 struct qm_dev_dfx {
174 u32 dev_state;
175 u32 dev_timeout;
176 };
177
178 struct dfx_diff_registers {
179 u32 *regs;
180 u32 reg_offset;
181 u32 reg_len;
182 };
183
184 struct qm_dfx {
185 atomic64_t err_irq_cnt;
186 atomic64_t aeq_irq_cnt;
187 atomic64_t abnormal_irq_cnt;
188 atomic64_t create_qp_err_cnt;
189 atomic64_t mb_err_cnt;
190 };
191
192 struct debugfs_file {
193 enum qm_debug_file index;
194 struct mutex lock;
195 struct qm_debug *debug;
196 };
197
198 struct qm_debug {
199 u32 curr_qm_qp_num;
200 u32 sqe_mask_offset;
201 u32 sqe_mask_len;
202 struct qm_dfx dfx;
203 struct dentry *debug_root;
204 struct dentry *qm_d;
205 struct debugfs_file files[DEBUG_FILE_NUM];
206 struct qm_dev_dfx dev_dfx;
207 unsigned int *qm_last_words;
208 /* ACC engines recoreding last regs */
209 unsigned int *last_words;
210 struct dfx_diff_registers *qm_diff_regs;
211 struct dfx_diff_registers *acc_diff_regs;
212 };
213
214 struct qm_shaper_factor {
215 u32 func_qos;
216 u64 cir_b;
217 u64 cir_u;
218 u64 cir_s;
219 u64 cbs_s;
220 };
221
222 struct qm_dma {
223 void *va;
224 dma_addr_t dma;
225 size_t size;
226 };
227
228 struct hisi_qm_status {
229 u32 eq_head;
230 bool eqc_phase;
231 u32 aeq_head;
232 bool aeqc_phase;
233 atomic_t flags;
234 int stop_reason;
235 };
236
237 struct hisi_qm;
238
239 enum acc_err_result {
240 ACC_ERR_NONE,
241 ACC_ERR_NEED_RESET,
242 ACC_ERR_RECOVERED,
243 };
244
245 struct hisi_qm_err_mask {
246 u32 ecc_2bits_mask;
247 u32 shutdown_mask;
248 u32 reset_mask;
249 u32 ce;
250 u32 nfe;
251 u32 fe;
252 };
253
254 struct hisi_qm_err_info {
255 char *acpi_rst;
256 u32 msi_wr_port;
257 struct hisi_qm_err_mask qm_err;
258 struct hisi_qm_err_mask dev_err;
259 };
260
261 struct hisi_qm_err_status {
262 u32 is_qm_ecc_mbit;
263 u32 is_dev_ecc_mbit;
264 };
265
266 struct hisi_qm_err_ini {
267 int (*hw_init)(struct hisi_qm *qm);
268 void (*hw_err_enable)(struct hisi_qm *qm);
269 void (*hw_err_disable)(struct hisi_qm *qm);
270 u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
271 void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts);
272 void (*open_axi_master_ooo)(struct hisi_qm *qm);
273 void (*close_axi_master_ooo)(struct hisi_qm *qm);
274 void (*open_sva_prefetch)(struct hisi_qm *qm);
275 void (*close_sva_prefetch)(struct hisi_qm *qm);
276 void (*show_last_dfx_regs)(struct hisi_qm *qm);
277 void (*err_info_init)(struct hisi_qm *qm);
278 enum acc_err_result (*get_err_result)(struct hisi_qm *qm);
279 bool (*dev_is_abnormal)(struct hisi_qm *qm);
280 int (*set_priv_status)(struct hisi_qm *qm);
281 void (*disable_axi_error)(struct hisi_qm *qm);
282 void (*enable_axi_error)(struct hisi_qm *qm);
283 };
284
285 struct hisi_qm_cap_info {
286 u32 type;
287 /* Register offset */
288 u32 offset;
289 /* Bit offset in register */
290 u32 shift;
291 u32 mask;
292 u32 v1_val;
293 u32 v2_val;
294 u32 v3_val;
295 };
296
297 struct hisi_qm_cap_query_info {
298 u32 type;
299 const char *name;
300 u32 offset;
301 u32 v1_val;
302 u32 v2_val;
303 u32 v3_val;
304 };
305
306 struct hisi_qm_cap_record {
307 u32 type;
308 const char *name;
309 u32 cap_val;
310 };
311
312 struct hisi_qm_cap_tables {
313 u32 qm_cap_size;
314 struct hisi_qm_cap_record *qm_cap_table;
315 u32 dev_cap_size;
316 struct hisi_qm_cap_record *dev_cap_table;
317 };
318
319 struct hisi_qm_list {
320 struct mutex lock;
321 struct list_head list;
322 int (*register_to_crypto)(struct hisi_qm *qm);
323 void (*unregister_from_crypto)(struct hisi_qm *qm);
324 };
325
326 struct hisi_qm_poll_data {
327 struct hisi_qm *qm;
328 struct work_struct work;
329 u16 *qp_finish_id;
330 u16 eqe_num;
331 };
332
333 /**
334 * struct qm_err_isolate
335 * @isolate_lock: protects device error log
336 * @err_threshold: user config error threshold which triggers isolation
337 * @is_isolate: device isolation state
338 * @uacce_hw_errs: index into qm device error list
339 */
340 struct qm_err_isolate {
341 struct mutex isolate_lock;
342 u32 err_threshold;
343 bool is_isolate;
344 struct list_head qm_hw_errs;
345 };
346
347 struct qm_rsv_buf {
348 struct qm_sqc *sqc;
349 struct qm_cqc *cqc;
350 struct qm_eqc *eqc;
351 struct qm_aeqc *aeqc;
352 dma_addr_t sqc_dma;
353 dma_addr_t cqc_dma;
354 dma_addr_t eqc_dma;
355 dma_addr_t aeqc_dma;
356 struct qm_dma qcdma;
357 };
358
359 struct hisi_qm {
360 enum qm_hw_ver ver;
361 enum qm_fun_type fun_type;
362 const char *dev_name;
363 struct pci_dev *pdev;
364 void __iomem *io_base;
365 void __iomem *db_io_base;
366
367 /* Capbility version, 0: not supports */
368 u32 cap_ver;
369 u32 sqe_size;
370 u32 qp_base;
371 u32 qp_num;
372 u32 qp_in_used;
373 u32 ctrl_qp_num;
374 u32 max_qp_num;
375 u32 vfs_num;
376 u32 db_interval;
377 u16 eq_depth;
378 u16 aeq_depth;
379 struct list_head list;
380 struct hisi_qm_list *qm_list;
381
382 struct qm_dma qdma;
383 struct qm_sqc *sqc;
384 struct qm_cqc *cqc;
385 struct qm_eqe *eqe;
386 struct qm_aeqe *aeqe;
387 dma_addr_t sqc_dma;
388 dma_addr_t cqc_dma;
389 dma_addr_t eqe_dma;
390 dma_addr_t aeqe_dma;
391 struct qm_rsv_buf xqc_buf;
392
393 struct hisi_qm_status status;
394 const struct hisi_qm_err_ini *err_ini;
395 struct hisi_qm_err_info err_info;
396 struct hisi_qm_err_status err_status;
397 /* driver removing and reset sched */
398 unsigned long misc_ctl;
399 /* Device capability bit */
400 unsigned long caps;
401
402 struct rw_semaphore qps_lock;
403 struct idr qp_idr;
404 struct hisi_qp *qp_array;
405 struct hisi_qm_poll_data *poll_data;
406
407 struct mutex mailbox_lock;
408
409 struct mutex ifc_lock;
410
411 const struct hisi_qm_hw_ops *ops;
412
413 struct qm_debug debug;
414
415 u32 error_mask;
416
417 struct workqueue_struct *wq;
418 struct work_struct rst_work;
419 struct work_struct cmd_process;
420
421 bool use_sva;
422
423 resource_size_t phys_base;
424 resource_size_t db_phys_base;
425 struct uacce_device *uacce;
426 int mode;
427 struct qm_shaper_factor *factor;
428 u32 mb_qos;
429 u32 type_rate;
430 struct qm_err_isolate isolate_data;
431
432 struct hisi_qm_cap_tables cap_tables;
433 };
434
435 struct hisi_qp_status {
436 atomic_t used;
437 u16 sq_tail;
438 u16 cq_head;
439 bool cqc_phase;
440 atomic_t flags;
441 };
442
443 struct hisi_qp_ops {
444 int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm);
445 };
446
447 struct hisi_qp {
448 u32 qp_id;
449 u16 sq_depth;
450 u16 cq_depth;
451 u8 alg_type;
452 u8 req_type;
453
454 struct qm_dma qdma;
455 void *sqe;
456 struct qm_cqe *cqe;
457 dma_addr_t sqe_dma;
458 dma_addr_t cqe_dma;
459
460 struct hisi_qp_status qp_status;
461 struct hisi_qp_ops *hw_ops;
462 void *qp_ctx;
463 void (*req_cb)(struct hisi_qp *qp, void *data);
464 void (*event_cb)(struct hisi_qp *qp);
465
466 struct hisi_qm *qm;
467 bool is_resetting;
468 bool is_in_kernel;
469 u16 pasid;
470 struct uacce_queue *uacce_q;
471 };
472
vfs_num_set(const char * val,const struct kernel_param * kp)473 static inline int vfs_num_set(const char *val, const struct kernel_param *kp)
474 {
475 u32 n;
476 int ret;
477
478 if (!val)
479 return -EINVAL;
480
481 ret = kstrtou32(val, 10, &n);
482 if (ret < 0)
483 return ret;
484
485 if (n > QM_MAX_VFS_NUM_V2)
486 return -EINVAL;
487
488 return param_set_int(val, kp);
489 }
490
mode_set(const char * val,const struct kernel_param * kp)491 static inline int mode_set(const char *val, const struct kernel_param *kp)
492 {
493 u32 n;
494 int ret;
495
496 if (!val)
497 return -EINVAL;
498
499 ret = kstrtou32(val, 10, &n);
500 if (ret != 0 || (n != UACCE_MODE_SVA &&
501 n != UACCE_MODE_NOUACCE))
502 return -EINVAL;
503
504 return param_set_int(val, kp);
505 }
506
uacce_mode_set(const char * val,const struct kernel_param * kp)507 static inline int uacce_mode_set(const char *val, const struct kernel_param *kp)
508 {
509 return mode_set(val, kp);
510 }
511
hisi_qm_init_list(struct hisi_qm_list * qm_list)512 static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
513 {
514 INIT_LIST_HEAD(&qm_list->list);
515 mutex_init(&qm_list->lock);
516 }
517
hisi_qm_add_list(struct hisi_qm * qm,struct hisi_qm_list * qm_list)518 static inline void hisi_qm_add_list(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
519 {
520 mutex_lock(&qm_list->lock);
521 list_add_tail(&qm->list, &qm_list->list);
522 mutex_unlock(&qm_list->lock);
523 }
524
hisi_qm_del_list(struct hisi_qm * qm,struct hisi_qm_list * qm_list)525 static inline void hisi_qm_del_list(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
526 {
527 mutex_lock(&qm_list->lock);
528 list_del(&qm->list);
529 mutex_unlock(&qm_list->lock);
530 }
531
532 int hisi_qm_q_num_set(const char *val, const struct kernel_param *kp,
533 unsigned int device);
534 int hisi_qm_init(struct hisi_qm *qm);
535 void hisi_qm_uninit(struct hisi_qm *qm);
536 int hisi_qm_start(struct hisi_qm *qm);
537 int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);
538 int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
539 void hisi_qm_stop_qp(struct hisi_qp *qp);
540 int hisi_qp_send(struct hisi_qp *qp, const void *msg);
541 void hisi_qm_debug_init(struct hisi_qm *qm);
542 void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
543 int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs);
544 int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen);
545 int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs);
546 void hisi_qm_dev_err_init(struct hisi_qm *qm);
547 void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
548 int hisi_qm_regs_debugfs_init(struct hisi_qm *qm,
549 struct dfx_diff_registers *dregs, u32 reg_len);
550 void hisi_qm_regs_debugfs_uninit(struct hisi_qm *qm, u32 reg_len);
551 void hisi_qm_acc_diff_regs_dump(struct hisi_qm *qm, struct seq_file *s,
552 struct dfx_diff_registers *dregs, u32 regs_len);
553
554 pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
555 pci_channel_state_t state);
556 pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
557 void hisi_qm_reset_prepare(struct pci_dev *pdev);
558 void hisi_qm_reset_done(struct pci_dev *pdev);
559
560 int hisi_qm_wait_mb_ready(struct hisi_qm *qm);
561 int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
562 bool op);
563
564 struct hisi_acc_sgl_pool;
565 struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
566 struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,
567 u32 index, dma_addr_t *hw_sgl_dma, enum dma_data_direction dir);
568 void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
569 struct hisi_acc_hw_sgl *hw_sgl, enum dma_data_direction dir);
570 struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
571 u32 count, u32 sge_nr);
572 void hisi_acc_free_sgl_pool(struct device *dev,
573 struct hisi_acc_sgl_pool *pool);
574 int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
575 u8 alg_type, int node, struct hisi_qp **qps);
576 void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
577 void hisi_qm_dev_shutdown(struct pci_dev *pdev);
578 void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
579 int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard);
580 void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard);
581 int hisi_qm_resume(struct device *dev);
582 int hisi_qm_suspend(struct device *dev);
583 void hisi_qm_pm_uninit(struct hisi_qm *qm);
584 void hisi_qm_pm_init(struct hisi_qm *qm);
585 int hisi_qm_get_dfx_access(struct hisi_qm *qm);
586 void hisi_qm_put_dfx_access(struct hisi_qm *qm);
587 void hisi_qm_regs_dump(struct seq_file *s, struct debugfs_regset32 *regset);
588 u32 hisi_qm_get_hw_info(struct hisi_qm *qm,
589 const struct hisi_qm_cap_info *info_table,
590 u32 index, bool is_read);
591 u32 hisi_qm_get_cap_value(struct hisi_qm *qm,
592 const struct hisi_qm_cap_query_info *info_table,
593 u32 index, bool is_read);
594 int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs,
595 u32 dev_algs_size);
596
597 /* Used by VFIO ACC live migration driver */
598 struct pci_driver *hisi_sec_get_pf_driver(void);
599 struct pci_driver *hisi_hpre_get_pf_driver(void);
600 struct pci_driver *hisi_zip_get_pf_driver(void);
601 #endif
602