1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2024 NXP 4 */ 5 6 #ifndef _SCMI_IMX_H 7 #define _SCMI_IMX_H 8 9 #include <linux/bitfield.h> 10 #include <linux/errno.h> 11 #include <linux/scmi_imx_protocol.h> 12 #include <linux/types.h> 13 14 #define SCMI_IMX95_CTRL_PDM_CLK_SEL 0 /* AON PDM clock sel */ 15 #define SCMI_IMX95_CTRL_MQS1_SETTINGS 1 /* AON MQS settings */ 16 #define SCMI_IMX95_CTRL_SAI1_MCLK 2 /* AON SAI1 MCLK */ 17 #define SCMI_IMX95_CTRL_SAI3_MCLK 3 /* WAKE SAI3 MCLK */ 18 #define SCMI_IMX95_CTRL_SAI4_MCLK 4 /* WAKE SAI4 MCLK */ 19 #define SCMI_IMX95_CTRL_SAI5_MCLK 5 /* WAKE SAI5 MCLK */ 20 21 #define SCMI_IMX94_CTRL_PDM_CLK_SEL 0U /*!< AON PDM clock sel */ 22 #define SCMI_IMX94_CTRL_MQS1_SETTINGS 1U /*!< AON MQS settings */ 23 #define SCMI_IMX94_CTRL_MQS2_SETTINGS 2U /*!< WAKE MQS settings */ 24 #define SCMI_IMX94_CTRL_SAI1_MCLK 3U /*!< AON SAI1 MCLK */ 25 #define SCMI_IMX94_CTRL_SAI2_MCLK 4U /*!< WAKE SAI2 MCLK */ 26 #define SCMI_IMX94_CTRL_SAI3_MCLK 5U /*!< WAKE SAI3 MCLK */ 27 #define SCMI_IMX94_CTRL_SAI4_MCLK 6U /*!< WAKE SAI4 MCLK */ 28 29 int scmi_imx_misc_ctrl_get(u32 id, u32 *num, u32 *val); 30 int scmi_imx_misc_ctrl_set(u32 id, u32 val); 31 32 int scmi_imx_cpu_start(u32 cpuid, bool start); 33 int scmi_imx_cpu_started(u32 cpuid, bool *started); 34 int scmi_imx_cpu_reset_vector_set(u32 cpuid, u64 vector, bool start, bool boot, 35 bool resume); 36 37 enum scmi_imx_lmm_op { 38 SCMI_IMX_LMM_BOOT, 39 SCMI_IMX_LMM_POWER_ON, 40 SCMI_IMX_LMM_SHUTDOWN, 41 }; 42 43 /* For shutdown pperation */ 44 #define SCMI_IMX_LMM_OP_FORCEFUL 0 45 #define SCMI_IMX_LMM_OP_GRACEFUL BIT(0) 46 47 int scmi_imx_lmm_operation(u32 lmid, enum scmi_imx_lmm_op op, u32 flags); 48 int scmi_imx_lmm_info(u32 lmid, struct scmi_imx_lmm_info *info); 49 int scmi_imx_lmm_reset_vector_set(u32 lmid, u32 cpuid, u32 flags, u64 vector); 50 #endif 51