1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. 4 * Synopsys DesignWare eDMA core driver 5 * 6 * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com> 7 */ 8 9 #ifndef _DW_EDMA_H 10 #define _DW_EDMA_H 11 12 #include <linux/device.h> 13 #include <linux/dmaengine.h> 14 15 #define EDMA_MAX_WR_CH 8 16 #define EDMA_MAX_RD_CH 8 17 18 struct dw_edma; 19 20 struct dw_edma_region { 21 u64 paddr; 22 union { 23 void *mem; 24 void __iomem *io; 25 } vaddr; 26 size_t sz; 27 }; 28 29 /** 30 * struct dw_edma_plat_ops - platform-specific eDMA methods 31 * @irq_vector: Get IRQ number of the passed eDMA channel. Note the 32 * method accepts the channel id in the end-to-end 33 * numbering with the eDMA write channels being placed 34 * first in the row. 35 * @pci_address: Get PCIe bus address corresponding to the passed CPU 36 * address. Note there is no need in specifying this 37 * function if the address translation is performed by 38 * the DW PCIe RP/EP controller with the DW eDMA device in 39 * subject and DMA_BYPASS isn't set for all the outbound 40 * iATU windows. That will be done by the controller 41 * automatically. 42 */ 43 struct dw_edma_plat_ops { 44 int (*irq_vector)(struct device *dev, unsigned int nr); 45 u64 (*pci_address)(struct device *dev, phys_addr_t cpu_addr); 46 }; 47 48 enum dw_edma_map_format { 49 EDMA_MF_EDMA_LEGACY = 0x0, 50 EDMA_MF_EDMA_UNROLL = 0x1, 51 EDMA_MF_HDMA_COMPAT = 0x5, 52 EDMA_MF_HDMA_NATIVE = 0x7, 53 }; 54 55 /** 56 * enum dw_edma_chip_flags - Flags specific to an eDMA chip 57 * @DW_EDMA_CHIP_LOCAL: eDMA is used locally by an endpoint 58 */ 59 enum dw_edma_chip_flags { 60 DW_EDMA_CHIP_LOCAL = BIT(0), 61 }; 62 63 /** 64 * struct dw_edma_chip - representation of DesignWare eDMA controller hardware 65 * @dev: struct device of the eDMA controller 66 * @nr_irqs: total number of DMA IRQs 67 * @ops: DMA channel to IRQ number mapping 68 * @flags: dw_edma_chip_flags 69 * @reg_base: DMA register base address 70 * @ll_wr_cnt: DMA write link list count 71 * @ll_rd_cnt: DMA read link list count 72 * @ll_region_wr: DMA descriptor link list memory for write channel 73 * @ll_region_rd: DMA descriptor link list memory for read channel 74 * @dt_region_wr: DMA data memory for write channel 75 * @dt_region_rd: DMA data memory for read channel 76 * @mf: DMA register map format 77 * @dw: struct dw_edma that is filled by dw_edma_probe() 78 */ 79 struct dw_edma_chip { 80 struct device *dev; 81 int nr_irqs; 82 const struct dw_edma_plat_ops *ops; 83 u32 flags; 84 85 void __iomem *reg_base; 86 87 u16 ll_wr_cnt; 88 u16 ll_rd_cnt; 89 /* link list address */ 90 struct dw_edma_region ll_region_wr[EDMA_MAX_WR_CH]; 91 struct dw_edma_region ll_region_rd[EDMA_MAX_RD_CH]; 92 93 /* data region */ 94 struct dw_edma_region dt_region_wr[EDMA_MAX_WR_CH]; 95 struct dw_edma_region dt_region_rd[EDMA_MAX_RD_CH]; 96 97 enum dw_edma_map_format mf; 98 99 struct dw_edma *dw; 100 }; 101 102 /* Export to the platform drivers */ 103 #if IS_REACHABLE(CONFIG_DW_EDMA) 104 int dw_edma_probe(struct dw_edma_chip *chip); 105 int dw_edma_remove(struct dw_edma_chip *chip); 106 #else dw_edma_probe(struct dw_edma_chip * chip)107static inline int dw_edma_probe(struct dw_edma_chip *chip) 108 { 109 return -ENODEV; 110 } 111 dw_edma_remove(struct dw_edma_chip * chip)112static inline int dw_edma_remove(struct dw_edma_chip *chip) 113 { 114 return 0; 115 } 116 #endif /* CONFIG_DW_EDMA */ 117 118 #endif /* _DW_EDMA_H */ 119