1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree file for the J722S MAIN domain peripherals 4 * 5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/phy/phy-cadence.h> 9#include <dt-bindings/phy/phy-ti.h> 10 11/ { 12 serdes_refclk: clk-0 { 13 compatible = "fixed-clock"; 14 #clock-cells = <0>; 15 clock-frequency = <0>; 16 }; 17}; 18 19&cbass_main { 20 serdes_wiz0: phy@f000000 { 21 compatible = "ti,am64-wiz-10g"; 22 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 26 clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>; 27 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 28 num-lanes = <1>; 29 #reset-cells = <1>; 30 #clock-cells = <1>; 31 32 assigned-clocks = <&k3_clks 279 1>; 33 assigned-clock-parents = <&k3_clks 279 5>; 34 35 status = "disabled"; 36 37 serdes0: serdes@f000000 { 38 compatible = "ti,j721e-serdes-10g"; 39 reg = <0x0f000000 0x00010000>; 40 reg-names = "torrent_phy"; 41 resets = <&serdes_wiz0 0>; 42 reset-names = "torrent_reset"; 43 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 44 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 45 clock-names = "refclk", "phy_en_refclk"; 46 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 47 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 48 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 49 assigned-clock-parents = <&k3_clks 279 1>, 50 <&k3_clks 279 1>, 51 <&k3_clks 279 1>; 52 #address-cells = <1>; 53 #size-cells = <0>; 54 #clock-cells = <1>; 55 }; 56 }; 57 58 serdes_wiz1: phy@f010000 { 59 compatible = "ti,am64-wiz-10g"; 60 ranges = <0x0f010000 0x0 0x0f010000 0x00010000>; 61 #address-cells = <1>; 62 #size-cells = <1>; 63 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 64 clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>; 65 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 66 num-lanes = <1>; 67 #reset-cells = <1>; 68 #clock-cells = <1>; 69 70 assigned-clocks = <&k3_clks 280 1>; 71 assigned-clock-parents = <&k3_clks 280 5>; 72 73 status = "disabled"; 74 75 serdes1: serdes@f010000 { 76 compatible = "ti,j721e-serdes-10g"; 77 reg = <0x0f010000 0x00010000>; 78 reg-names = "torrent_phy"; 79 resets = <&serdes_wiz1 0>; 80 reset-names = "torrent_reset"; 81 clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 82 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; 83 clock-names = "refclk", "phy_en_refclk"; 84 assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 85 <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, 86 <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; 87 assigned-clock-parents = <&k3_clks 280 1>, 88 <&k3_clks 280 1>, 89 <&k3_clks 280 1>; 90 #address-cells = <1>; 91 #size-cells = <0>; 92 #clock-cells = <1>; 93 }; 94 }; 95 96 pcie0_rc: pcie@f102000 { 97 compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host"; 98 reg = <0x00 0x0f102000 0x00 0x1000>, 99 <0x00 0x0f100000 0x00 0x400>, 100 <0x00 0x0d000000 0x00 0x00800000>, 101 <0x06 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ 102 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 103 ranges = <0x01000000 0x00 0x00001000 0x06 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ 104 <0x02000000 0x00 0x00101000 0x06 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ 105 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 106 interrupt-names = "link_state"; 107 interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>; 108 device_type = "pci"; 109 max-link-speed = <3>; 110 num-lanes = <1>; 111 power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>; 112 clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; 113 clock-names = "fck", "pcie_refclk"; 114 #address-cells = <3>; 115 #size-cells = <2>; 116 bus-range = <0x0 0xff>; 117 vendor-id = <0x104c>; 118 device-id = <0xb010>; 119 cdns,no-bar-match-nbits = <64>; 120 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; 121 msi-map = <0x0 &gic_its 0x0 0x10000>; 122 status = "disabled"; 123 }; 124 125 usbss1: usb@f920000 { 126 compatible = "ti,j721e-usb"; 127 reg = <0x00 0x0f920000 0x00 0x100>; 128 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 129 clocks = <&k3_clks 278 3>, <&k3_clks 278 1>; 130 clock-names = "ref", "lpm"; 131 assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */ 132 assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */ 133 #address-cells = <2>; 134 #size-cells = <2>; 135 ranges; 136 status = "disabled"; 137 138 usb1: usb@31200000 { 139 compatible = "cdns,usb3"; 140 reg = <0x00 0x31200000 0x00 0x10000>, 141 <0x00 0x31210000 0x00 0x10000>, 142 <0x00 0x31220000 0x00 0x10000>; 143 reg-names = "otg", 144 "xhci", 145 "dev"; 146 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 147 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 148 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */ 149 interrupt-names = "host", 150 "peripheral", 151 "otg"; 152 maximum-speed = "super-speed"; 153 dr_mode = "otg"; 154 }; 155 }; 156 157 ti_csi2rx1: ticsi2rx@30122000 { 158 compatible = "ti,j721e-csi2rx-shim"; 159 reg = <0x00 0x30122000 0x00 0x1000>; 160 ranges; 161 #address-cells = <2>; 162 #size-cells = <2>; 163 dmas = <&main_bcdma_csi 0 0x5100 0>; 164 dma-names = "rx0"; 165 power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; 166 status = "disabled"; 167 168 cdns_csi2rx1: csi-bridge@30121000 { 169 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 170 reg = <0x00 0x30121000 0x00 0x1000>; 171 clocks = <&k3_clks 247 0>, <&k3_clks 247 3>, <&k3_clks 247 0>, 172 <&k3_clks 247 0>, <&k3_clks 247 4>, <&k3_clks 247 4>; 173 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 174 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 175 phys = <&dphy1>; 176 phy-names = "dphy"; 177 178 ports { 179 #address-cells = <1>; 180 #size-cells = <0>; 181 182 csi1_port0: port@0 { 183 reg = <0>; 184 status = "disabled"; 185 }; 186 187 csi1_port1: port@1 { 188 reg = <1>; 189 status = "disabled"; 190 }; 191 192 csi1_port2: port@2 { 193 reg = <2>; 194 status = "disabled"; 195 }; 196 197 csi1_port3: port@3 { 198 reg = <3>; 199 status = "disabled"; 200 }; 201 202 csi1_port4: port@4 { 203 reg = <4>; 204 status = "disabled"; 205 }; 206 }; 207 }; 208 }; 209 210 ti_csi2rx2: ticsi2rx@30142000 { 211 compatible = "ti,j721e-csi2rx-shim"; 212 reg = <0x00 0x30142000 0x00 0x1000>; 213 ranges; 214 #address-cells = <2>; 215 #size-cells = <2>; 216 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 217 dmas = <&main_bcdma_csi 0 0x5200 0>; 218 dma-names = "rx0"; 219 status = "disabled"; 220 221 cdns_csi2rx2: csi-bridge@30141000 { 222 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 223 reg = <0x00 0x30141000 0x00 0x1000>; 224 clocks = <&k3_clks 248 0>, <&k3_clks 248 3>, <&k3_clks 248 0>, 225 <&k3_clks 248 0>, <&k3_clks 248 4>, <&k3_clks 248 4>; 226 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 227 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 228 phys = <&dphy2>; 229 phy-names = "dphy"; 230 231 ports { 232 #address-cells = <1>; 233 #size-cells = <0>; 234 235 csi2_port0: port@0 { 236 reg = <0>; 237 status = "disabled"; 238 }; 239 240 csi2_port1: port@1 { 241 reg = <1>; 242 status = "disabled"; 243 }; 244 245 csi2_port2: port@2 { 246 reg = <2>; 247 status = "disabled"; 248 }; 249 250 csi2_port3: port@3 { 251 reg = <3>; 252 status = "disabled"; 253 }; 254 255 csi2_port4: port@4 { 256 reg = <4>; 257 status = "disabled"; 258 }; 259 }; 260 }; 261 }; 262 263 ti_csi2rx3: ticsi2rx@30162000 { 264 compatible = "ti,j721e-csi2rx-shim"; 265 reg = <0x00 0x30162000 0x00 0x1000>; 266 ranges; 267 #address-cells = <2>; 268 #size-cells = <2>; 269 dmas = <&main_bcdma_csi 0 0x5300 0>; 270 dma-names = "rx0"; 271 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 272 status = "disabled"; 273 274 cdns_csi2rx3: csi-bridge@30161000 { 275 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 276 reg = <0x00 0x30161000 0x00 0x1000>; 277 clocks = <&k3_clks 249 0>, <&k3_clks 249 3>, <&k3_clks 249 0>, 278 <&k3_clks 249 0>, <&k3_clks 249 4>, <&k3_clks 249 4>; 279 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 280 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 281 phys = <&dphy3>; 282 phy-names = "dphy"; 283 284 ports { 285 #address-cells = <1>; 286 #size-cells = <0>; 287 288 csi3_port0: port@0 { 289 reg = <0>; 290 status = "disabled"; 291 }; 292 293 csi3_port1: port@1 { 294 reg = <1>; 295 status = "disabled"; 296 }; 297 298 csi3_port2: port@2 { 299 reg = <2>; 300 status = "disabled"; 301 }; 302 303 csi3_port3: port@3 { 304 reg = <3>; 305 status = "disabled"; 306 }; 307 308 csi3_port4: port@4 { 309 reg = <4>; 310 status = "disabled"; 311 }; 312 }; 313 }; 314 }; 315 316 dphy1: phy@30130000 { 317 compatible = "cdns,dphy-rx"; 318 reg = <0x00 0x30130000 0x00 0x1100>; 319 #phy-cells = <0>; 320 power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; 321 status = "disabled"; 322 }; 323 324 dphy2: phy@30150000 { 325 compatible = "cdns,dphy-rx"; 326 reg = <0x00 0x30150000 0x00 0x1100>; 327 #phy-cells = <0>; 328 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 329 status = "disabled"; 330 }; 331 332 dphy3: phy@30170000 { 333 compatible = "cdns,dphy-rx"; 334 reg = <0x00 0x30170000 0x00 0x1100>; 335 #phy-cells = <0>; 336 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 337 status = "disabled"; 338 }; 339 340 main_r5fss0: r5fss@78400000 { 341 compatible = "ti,am62-r5fss"; 342 #address-cells = <1>; 343 #size-cells = <1>; 344 ranges = <0x78400000 0x00 0x78400000 0x8000>, 345 <0x78500000 0x00 0x78500000 0x8000>; 346 power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>; 347 status = "disabled"; 348 349 main_r5fss0_core0: r5f@78400000 { 350 compatible = "ti,am62-r5f"; 351 reg = <0x78400000 0x00008000>, 352 <0x78500000 0x00008000>; 353 reg-names = "atcm", "btcm"; 354 resets = <&k3_reset 262 1>; 355 firmware-name = "j722s-main-r5f0_0-fw"; 356 ti,sci = <&dmsc>; 357 ti,sci-dev-id = <262>; 358 ti,sci-proc-ids = <0x04 0xff>; 359 ti,atcm-enable = <1>; 360 ti,btcm-enable = <1>; 361 ti,loczrama = <1>; 362 }; 363 }; 364 365 c7x_0: dsp@7e000000 { 366 compatible = "ti,am62a-c7xv-dsp"; 367 reg = <0x00 0x7e000000 0x00 0x00200000>; 368 reg-names = "l2sram"; 369 resets = <&k3_reset 208 1>; 370 firmware-name = "j722s-c71_0-fw"; 371 ti,sci = <&dmsc>; 372 ti,sci-dev-id = <208>; 373 ti,sci-proc-ids = <0x30 0xff>; 374 status = "disabled"; 375 }; 376 377 c7x_1: dsp@7e200000 { 378 compatible = "ti,am62a-c7xv-dsp"; 379 reg = <0x00 0x7e200000 0x00 0x00200000>; 380 reg-names = "l2sram"; 381 resets = <&k3_reset 268 1>; 382 firmware-name = "j722s-c71_1-fw"; 383 ti,sci = <&dmsc>; 384 ti,sci-dev-id = <268>; 385 ti,sci-proc-ids = <0x31 0xff>; 386 status = "disabled"; 387 }; 388}; 389 390&main_bcdma_csi { 391 compatible = "ti,j722s-dmss-bcdma-csi"; 392 reg = <0x00 0x4e230000 0x00 0x100>, 393 <0x00 0x4e180000 0x00 0x20000>, 394 <0x00 0x4e300000 0x00 0x10000>, 395 <0x00 0x4e100000 0x00 0x80000>; 396 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 397 ti,sci-rm-range-tchan = <0x22>; 398}; 399 400/* MCU domain overrides */ 401 402&mcu_r5fss0_core0 { 403 firmware-name = "j722s-mcu-r5f0_0-fw"; 404}; 405 406/* Wakeup domain overrides */ 407 408&wkup_r5fss0_core0 { 409 firmware-name = "j722s-wkup-r5f0_0-fw"; 410}; 411 412&main_conf { 413 serdes_ln_ctrl: mux-controller@4080 { 414 compatible = "reg-mux"; 415 reg = <0x4080 0x14>; 416 #mux-control-cells = <1>; 417 mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */ 418 <0x10 0x3>; /* SERDES1 lane0 select */ 419 }; 420 421 audio_refclk0: clock@82e0 { 422 compatible = "ti,am62-audio-refclk"; 423 reg = <0x82e0 0x4>; 424 clocks = <&k3_clks 157 0>; 425 assigned-clocks = <&k3_clks 157 0>; 426 assigned-clock-parents = <&k3_clks 157 15>; 427 #clock-cells = <0>; 428 }; 429 430 audio_refclk1: clock@82e4 { 431 compatible = "ti,am62-audio-refclk"; 432 reg = <0x82e4 0x4>; 433 clocks = <&k3_clks 157 18>; 434 assigned-clocks = <&k3_clks 157 18>; 435 assigned-clock-parents = <&k3_clks 157 33>; 436 #clock-cells = <0>; 437 }; 438}; 439 440&wkup_conf { 441 pcie0_ctrl: pcie0-ctrl@4070 { 442 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 443 reg = <0x4070 0x4>; 444 }; 445}; 446 447&oc_sram { 448 reg = <0x00 0x70000000 0x00 0x40000>; 449 ranges = <0x00 0x00 0x70000000 0x40000>; 450}; 451 452&inta_main_dmss { 453 ti,interrupt-ranges = <7 71 21>; 454}; 455 456&main_gpio0 { 457 gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>, 458 <&main_pmx0 70 72 17>; 459 ti,ngpio = <87>; 460}; 461 462&main_gpio1 { 463 gpio-ranges = <&main_pmx0 7 101 25>, <&main_pmx0 42 137 5>, 464 <&main_pmx0 47 143 3>, <&main_pmx0 50 149 2>; 465 gpio-reserved-ranges = <0 7>, <32 10>; 466 ti,ngpio = <73>; 467}; 468