1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree file for the MAIN domain peripherals shared by AM62P and J722S 4 * 5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 #address-cells = <1>; 12 #size-cells = <1>; 13 }; 14 15 gic500: interrupt-controller@1800000 { 16 compatible = "arm,gic-v3"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 ranges; 20 #interrupt-cells = <3>; 21 interrupt-controller; 22 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 23 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 24 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 25 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 26 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 27 /* 28 * vcpumntirq: 29 * virtual CPU interface maintenance interrupt 30 */ 31 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 32 33 gic_its: msi-controller@1820000 { 34 compatible = "arm,gic-v3-its"; 35 reg = <0x00 0x01820000 0x00 0x10000>; 36 socionext,synquacer-pre-its = <0x1000000 0x400000>; 37 msi-controller; 38 #msi-cells = <1>; 39 }; 40 }; 41 42 main_conf: bus@100000 { 43 compatible = "simple-bus"; 44 reg = <0x00 0x00100000 0x00 0x20000>; 45 #address-cells = <1>; 46 #size-cells = <1>; 47 ranges = <0x00 0x00 0x00100000 0x20000>; 48 49 phy_gmii_sel: phy@4044 { 50 compatible = "ti,am654-phy-gmii-sel"; 51 reg = <0x4044 0x8>; 52 #phy-cells = <1>; 53 }; 54 55 epwm_tbclk: clock-controller@4130 { 56 compatible = "ti,am62-epwm-tbclk"; 57 reg = <0x4130 0x4>; 58 #clock-cells = <1>; 59 }; 60 }; 61 62 dmss: bus@48000000 { 63 compatible = "simple-bus"; 64 #address-cells = <2>; 65 #size-cells = <2>; 66 dma-ranges; 67 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 68 bootph-all; 69 70 ti,sci-dev-id = <25>; 71 72 secure_proxy_main: mailbox@4d000000 { 73 compatible = "ti,am654-secure-proxy"; 74 #mbox-cells = <1>; 75 reg-names = "target_data", "rt", "scfg"; 76 reg = <0x00 0x4d000000 0x00 0x80000>, 77 <0x00 0x4a600000 0x00 0x80000>, 78 <0x00 0x4a400000 0x00 0x80000>; 79 interrupt-names = "rx_012"; 80 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 81 bootph-all; 82 }; 83 84 inta_main_dmss: interrupt-controller@48000000 { 85 compatible = "ti,sci-inta"; 86 reg = <0x00 0x48000000 0x00 0x100000>; 87 #interrupt-cells = <0>; 88 interrupt-controller; 89 interrupt-parent = <&gic500>; 90 msi-controller; 91 ti,sci = <&dmsc>; 92 ti,sci-dev-id = <28>; 93 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 94 }; 95 96 main_bcdma: dma-controller@485c0100 { 97 compatible = "ti,am64-dmss-bcdma"; 98 reg = <0x00 0x485c0100 0x00 0x100>, 99 <0x00 0x4c000000 0x00 0x20000>, 100 <0x00 0x4a820000 0x00 0x20000>, 101 <0x00 0x4aa40000 0x00 0x20000>, 102 <0x00 0x4bc00000 0x00 0x100000>, 103 <0x00 0x48600000 0x00 0x8000>, 104 <0x00 0x484a4000 0x00 0x2000>, 105 <0x00 0x484c2000 0x00 0x2000>, 106 <0x00 0x48420000 0x00 0x2000>; 107 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", 108 "ring", "tchan", "rchan", "bchan"; 109 msi-parent = <&inta_main_dmss>; 110 #dma-cells = <3>; 111 112 ti,sci = <&dmsc>; 113 ti,sci-dev-id = <26>; 114 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 115 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 116 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 117 bootph-all; 118 }; 119 120 main_pktdma: dma-controller@485c0000 { 121 compatible = "ti,am64-dmss-pktdma"; 122 reg = <0x00 0x485c0000 0x00 0x100>, 123 <0x00 0x4a800000 0x00 0x20000>, 124 <0x00 0x4aa00000 0x00 0x20000>, 125 <0x00 0x4b800000 0x00 0x200000>, 126 <0x00 0x485e0000 0x00 0x10000>, 127 <0x00 0x484a0000 0x00 0x2000>, 128 <0x00 0x484c0000 0x00 0x2000>, 129 <0x00 0x48430000 0x00 0x1000>; 130 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", 131 "ring", "tchan", "rchan", "rflow"; 132 msi-parent = <&inta_main_dmss>; 133 #dma-cells = <2>; 134 bootph-all; 135 136 ti,sci = <&dmsc>; 137 ti,sci-dev-id = <30>; 138 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 139 <0x24>, /* CPSW_TX_CHAN */ 140 <0x25>, /* SAUL_TX_0_CHAN */ 141 <0x26>; /* SAUL_TX_1_CHAN */ 142 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 143 <0x11>, /* RING_CPSW_TX_CHAN */ 144 <0x12>, /* RING_SAUL_TX_0_CHAN */ 145 <0x13>; /* RING_SAUL_TX_1_CHAN */ 146 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 147 <0x2b>, /* CPSW_RX_CHAN */ 148 <0x2d>, /* SAUL_RX_0_CHAN */ 149 <0x2f>, /* SAUL_RX_1_CHAN */ 150 <0x31>, /* SAUL_RX_2_CHAN */ 151 <0x33>; /* SAUL_RX_3_CHAN */ 152 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 153 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 154 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 155 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 156 }; 157 }; 158 159 dmss_csi: bus@4e000000 { 160 compatible = "simple-bus"; 161 ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x408000>; 162 #address-cells = <2>; 163 #size-cells = <2>; 164 dma-ranges; 165 ti,sci-dev-id = <198>; 166 167 inta_main_dmss_csi: interrupt-controller@4e400000 { 168 compatible = "ti,sci-inta"; 169 reg = <0x00 0x4e400000 0x00 0x8000>; 170 #interrupt-cells = <0>; 171 interrupt-controller; 172 interrupt-parent = <&gic500>; 173 msi-controller; 174 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 175 ti,sci = <&dmsc>; 176 ti,sci-dev-id = <200>; 177 ti,interrupt-ranges = <0 237 8>; 178 ti,unmapped-event-sources = <&main_bcdma_csi>; 179 }; 180 181 main_bcdma_csi: dma-controller@4e230000 { 182 compatible = "ti,am62a-dmss-bcdma-csirx"; 183 reg = <0x00 0x4e230000 0x00 0x100>, 184 <0x00 0x4e180000 0x00 0x8000>, 185 <0x00 0x4e100000 0x00 0x10000>; 186 reg-names = "gcfg", "rchanrt", "ringrt"; 187 #dma-cells = <3>; 188 msi-parent = <&inta_main_dmss_csi>; 189 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 190 ti,sci = <&dmsc>; 191 ti,sci-dev-id = <199>; 192 ti,sci-rm-range-rchan = <0x21>; 193 }; 194 }; 195 196 dmsc: system-controller@44043000 { 197 compatible = "ti,k2g-sci"; 198 ti,host-id = <12>; 199 mbox-names = "rx", "tx"; 200 mboxes = <&secure_proxy_main 12>, 201 <&secure_proxy_main 13>; 202 reg-names = "debug_messages"; 203 reg = <0x00 0x44043000 0x00 0xfe0>; 204 bootph-all; 205 206 k3_pds: power-controller { 207 compatible = "ti,sci-pm-domain"; 208 #power-domain-cells = <2>; 209 bootph-all; 210 }; 211 212 k3_clks: clock-controller { 213 compatible = "ti,k2g-sci-clk"; 214 #clock-cells = <2>; 215 bootph-all; 216 }; 217 218 k3_reset: reset-controller { 219 compatible = "ti,sci-reset"; 220 #reset-cells = <2>; 221 bootph-all; 222 }; 223 }; 224 225 crypto: crypto@40900000 { 226 compatible = "ti,am62-sa3ul"; 227 reg = <0x00 0x40900000 0x00 0x1200>; 228 #address-cells = <2>; 229 #size-cells = <2>; 230 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 231 232 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, 233 <&main_pktdma 0x7507 0>; 234 dma-names = "tx", "rx1", "rx2"; 235 236 rng: rng@40910000 { 237 compatible = "inside-secure,safexcel-eip76"; 238 reg = <0x00 0x40910000 0x0 0x7d>; 239 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 240 status = "reserved"; 241 }; 242 }; 243 244 secure_proxy_sa3: mailbox@43600000 { 245 compatible = "ti,am654-secure-proxy"; 246 #mbox-cells = <1>; 247 reg-names = "target_data", "rt", "scfg"; 248 reg = <0x00 0x43600000 0x00 0x10000>, 249 <0x00 0x44880000 0x00 0x20000>, 250 <0x00 0x44860000 0x00 0x20000>; 251 /* 252 * Marked Disabled: 253 * Node is incomplete as it is meant for bootloaders and 254 * firmware on non-MPU processors 255 */ 256 status = "disabled"; 257 bootph-all; 258 }; 259 260 main_pmx0: pinctrl@f4000 { 261 compatible = "pinctrl-single"; 262 reg = <0x00 0xf4000 0x00 0x2b0>; 263 #pinctrl-cells = <1>; 264 pinctrl-single,register-width = <32>; 265 pinctrl-single,function-mask = <0xffffffff>; 266 bootph-all; 267 }; 268 269 main_esm: esm@420000 { 270 compatible = "ti,j721e-esm"; 271 reg = <0x00 0x420000 0x00 0x1000>; 272 bootph-pre-ram; 273 /* Interrupt sources: rti0, rti1, wrti0 rti2, rti3, rti15 */ 274 ti,esm-pins = <224>, <225>, <227>, <241>, <242>, <248>; 275 }; 276 277 main_timer0: timer@2400000 { 278 compatible = "ti,am654-timer"; 279 reg = <0x00 0x2400000 0x00 0x400>; 280 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&k3_clks 36 2>; 282 clock-names = "fck"; 283 assigned-clocks = <&k3_clks 36 2>; 284 assigned-clock-parents = <&k3_clks 36 3>; 285 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 286 ti,timer-pwm; 287 bootph-all; 288 }; 289 290 main_timer1: timer@2410000 { 291 compatible = "ti,am654-timer"; 292 reg = <0x00 0x2410000 0x00 0x400>; 293 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&k3_clks 37 2>; 295 clock-names = "fck"; 296 assigned-clocks = <&k3_clks 37 2>; 297 assigned-clock-parents = <&k3_clks 37 3>; 298 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 299 ti,timer-pwm; 300 }; 301 302 main_timer2: timer@2420000 { 303 compatible = "ti,am654-timer"; 304 reg = <0x00 0x2420000 0x00 0x400>; 305 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&k3_clks 38 2>; 307 clock-names = "fck"; 308 assigned-clocks = <&k3_clks 38 2>; 309 assigned-clock-parents = <&k3_clks 38 3>; 310 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 311 ti,timer-pwm; 312 }; 313 314 main_timer3: timer@2430000 { 315 compatible = "ti,am654-timer"; 316 reg = <0x00 0x2430000 0x00 0x400>; 317 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&k3_clks 39 2>; 319 clock-names = "fck"; 320 assigned-clocks = <&k3_clks 39 2>; 321 assigned-clock-parents = <&k3_clks 39 3>; 322 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 323 ti,timer-pwm; 324 }; 325 326 main_timer4: timer@2440000 { 327 compatible = "ti,am654-timer"; 328 reg = <0x00 0x2440000 0x00 0x400>; 329 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&k3_clks 40 2>; 331 clock-names = "fck"; 332 assigned-clocks = <&k3_clks 40 2>; 333 assigned-clock-parents = <&k3_clks 40 3>; 334 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 335 ti,timer-pwm; 336 }; 337 338 main_timer5: timer@2450000 { 339 compatible = "ti,am654-timer"; 340 reg = <0x00 0x2450000 0x00 0x400>; 341 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&k3_clks 41 2>; 343 clock-names = "fck"; 344 assigned-clocks = <&k3_clks 41 2>; 345 assigned-clock-parents = <&k3_clks 41 3>; 346 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 347 ti,timer-pwm; 348 }; 349 350 main_timer6: timer@2460000 { 351 compatible = "ti,am654-timer"; 352 reg = <0x00 0x2460000 0x00 0x400>; 353 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&k3_clks 42 2>; 355 clock-names = "fck"; 356 assigned-clocks = <&k3_clks 42 2>; 357 assigned-clock-parents = <&k3_clks 42 3>; 358 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 359 ti,timer-pwm; 360 }; 361 362 main_timer7: timer@2470000 { 363 compatible = "ti,am654-timer"; 364 reg = <0x00 0x2470000 0x00 0x400>; 365 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&k3_clks 43 2>; 367 clock-names = "fck"; 368 assigned-clocks = <&k3_clks 43 2>; 369 assigned-clock-parents = <&k3_clks 43 3>; 370 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 371 ti,timer-pwm; 372 }; 373 374 main_uart0: serial@2800000 { 375 compatible = "ti,am64-uart", "ti,am654-uart"; 376 reg = <0x00 0x02800000 0x00 0x100>; 377 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 378 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 379 clocks = <&k3_clks 146 0>; 380 clock-names = "fclk"; 381 status = "disabled"; 382 }; 383 384 main_uart1: serial@2810000 { 385 compatible = "ti,am64-uart", "ti,am654-uart"; 386 reg = <0x00 0x02810000 0x00 0x100>; 387 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 388 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 389 clocks = <&k3_clks 152 0>; 390 clock-names = "fclk"; 391 status = "disabled"; 392 }; 393 394 main_uart2: serial@2820000 { 395 compatible = "ti,am64-uart", "ti,am654-uart"; 396 reg = <0x00 0x02820000 0x00 0x100>; 397 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 398 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 399 clocks = <&k3_clks 153 0>; 400 clock-names = "fclk"; 401 status = "disabled"; 402 }; 403 404 main_uart3: serial@2830000 { 405 compatible = "ti,am64-uart", "ti,am654-uart"; 406 reg = <0x00 0x02830000 0x00 0x100>; 407 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 408 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 409 clocks = <&k3_clks 154 0>; 410 clock-names = "fclk"; 411 status = "disabled"; 412 }; 413 414 main_uart4: serial@2840000 { 415 compatible = "ti,am64-uart", "ti,am654-uart"; 416 reg = <0x00 0x02840000 0x00 0x100>; 417 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 418 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 419 clocks = <&k3_clks 155 0>; 420 clock-names = "fclk"; 421 status = "disabled"; 422 }; 423 424 main_uart5: serial@2850000 { 425 compatible = "ti,am64-uart", "ti,am654-uart"; 426 reg = <0x00 0x02850000 0x00 0x100>; 427 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 428 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 429 clocks = <&k3_clks 156 0>; 430 clock-names = "fclk"; 431 status = "disabled"; 432 }; 433 434 main_uart6: serial@2860000 { 435 compatible = "ti,am64-uart", "ti,am654-uart"; 436 reg = <0x00 0x02860000 0x00 0x100>; 437 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 438 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 439 clocks = <&k3_clks 158 0>; 440 clock-names = "fclk"; 441 status = "disabled"; 442 }; 443 444 main_i2c0: i2c@20000000 { 445 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 446 reg = <0x00 0x20000000 0x00 0x100>; 447 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 451 clocks = <&k3_clks 102 2>; 452 clock-names = "fck"; 453 status = "disabled"; 454 }; 455 456 main_i2c1: i2c@20010000 { 457 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 458 reg = <0x00 0x20010000 0x00 0x100>; 459 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 463 clocks = <&k3_clks 103 2>; 464 clock-names = "fck"; 465 status = "disabled"; 466 }; 467 468 main_i2c2: i2c@20020000 { 469 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 470 reg = <0x00 0x20020000 0x00 0x100>; 471 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 475 clocks = <&k3_clks 104 2>; 476 clock-names = "fck"; 477 status = "disabled"; 478 }; 479 480 main_i2c3: i2c@20030000 { 481 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 482 reg = <0x00 0x20030000 0x00 0x100>; 483 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 487 clocks = <&k3_clks 105 2>; 488 clock-names = "fck"; 489 status = "disabled"; 490 }; 491 492 main_spi0: spi@20100000 { 493 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 494 reg = <0x00 0x20100000 0x00 0x400>; 495 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 499 clocks = <&k3_clks 141 0>; 500 status = "disabled"; 501 }; 502 503 main_spi1: spi@20110000 { 504 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 505 reg = <0x00 0x20110000 0x00 0x400>; 506 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 510 clocks = <&k3_clks 142 0>; 511 status = "disabled"; 512 }; 513 514 main_spi2: spi@20120000 { 515 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 516 reg = <0x00 0x20120000 0x00 0x400>; 517 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 521 clocks = <&k3_clks 143 0>; 522 status = "disabled"; 523 }; 524 525 main_gpio_intr: interrupt-controller@a00000 { 526 compatible = "ti,sci-intr"; 527 reg = <0x00 0x00a00000 0x00 0x800>; 528 ti,intr-trigger-type = <1>; 529 interrupt-controller; 530 interrupt-parent = <&gic500>; 531 #interrupt-cells = <1>; 532 ti,sci = <&dmsc>; 533 ti,sci-dev-id = <3>; 534 ti,interrupt-ranges = <0 32 16>; 535 }; 536 537 main_gpio0: gpio@600000 { 538 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 539 reg = <0x00 0x00600000 0x00 0x100>; 540 gpio-controller; 541 #gpio-cells = <2>; 542 interrupt-parent = <&main_gpio_intr>; 543 interrupts = <190>, <191>, <192>, 544 <193>, <194>, <195>; 545 interrupt-controller; 546 #interrupt-cells = <2>; 547 ti,davinci-gpio-unbanked = <0>; 548 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 549 clocks = <&k3_clks 77 0>; 550 clock-names = "gpio"; 551 }; 552 553 main_gpio1: gpio@601000 { 554 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 555 reg = <0x00 0x00601000 0x00 0x100>; 556 gpio-controller; 557 #gpio-cells = <2>; 558 interrupt-parent = <&main_gpio_intr>; 559 interrupts = <180>, <181>, <182>, 560 <183>, <184>, <185>; 561 interrupt-controller; 562 #interrupt-cells = <2>; 563 ti,davinci-gpio-unbanked = <0>; 564 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 565 clocks = <&k3_clks 78 0>; 566 clock-names = "gpio"; 567 }; 568 569 sdhci0: mmc@fa10000 { 570 compatible = "ti,am64-sdhci-8bit"; 571 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; 572 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 573 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 574 clocks = <&k3_clks 57 1>, <&k3_clks 57 2>; 575 clock-names = "clk_ahb", "clk_xin"; 576 bus-width = <8>; 577 mmc-ddr-1_8v; 578 mmc-hs200-1_8v; 579 mmc-hs400-1_8v; 580 ti,clkbuf-sel = <0x7>; 581 ti,strobe-sel = <0x77>; 582 ti,trm-icp = <0x8>; 583 ti,otap-del-sel-legacy = <0x1>; 584 ti,otap-del-sel-mmc-hs = <0x1>; 585 ti,otap-del-sel-ddr52 = <0x6>; 586 ti,otap-del-sel-hs200 = <0x8>; 587 ti,otap-del-sel-hs400 = <0x5>; 588 ti,itap-del-sel-legacy = <0x10>; 589 ti,itap-del-sel-mmc-hs = <0xa>; 590 ti,itap-del-sel-ddr52 = <0x3>; 591 status = "disabled"; 592 }; 593 594 sdhci1: mmc@fa00000 { 595 compatible = "ti,am62-sdhci"; 596 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; 597 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 598 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 599 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 600 clock-names = "clk_ahb", "clk_xin"; 601 bus-width = <4>; 602 ti,clkbuf-sel = <0x7>; 603 ti,otap-del-sel-legacy = <0x0>; 604 ti,otap-del-sel-sd-hs = <0x0>; 605 ti,otap-del-sel-sdr12 = <0xf>; 606 ti,otap-del-sel-sdr25 = <0xf>; 607 ti,otap-del-sel-sdr50 = <0xc>; 608 ti,otap-del-sel-ddr50 = <0x9>; 609 ti,otap-del-sel-sdr104 = <0x6>; 610 ti,itap-del-sel-legacy = <0x0>; 611 ti,itap-del-sel-sd-hs = <0x0>; 612 ti,itap-del-sel-sdr12 = <0x0>; 613 ti,itap-del-sel-sdr25 = <0x0>; 614 status = "disabled"; 615 }; 616 617 sdhci2: mmc@fa20000 { 618 compatible = "ti,am62-sdhci"; 619 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; 620 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 621 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 622 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; 623 clock-names = "clk_ahb", "clk_xin"; 624 bus-width = <4>; 625 ti,clkbuf-sel = <0x7>; 626 ti,otap-del-sel-legacy = <0x0>; 627 ti,otap-del-sel-sd-hs = <0x0>; 628 ti,otap-del-sel-sdr12 = <0xf>; 629 ti,otap-del-sel-sdr25 = <0xf>; 630 ti,otap-del-sel-sdr50 = <0xc>; 631 ti,otap-del-sel-ddr50 = <0x9>; 632 ti,otap-del-sel-sdr104 = <0x6>; 633 ti,itap-del-sel-legacy = <0x0>; 634 ti,itap-del-sel-sd-hs = <0x0>; 635 ti,itap-del-sel-sdr12 = <0x0>; 636 ti,itap-del-sel-sdr25 = <0x0>; 637 status = "disabled"; 638 }; 639 640 usbss0: usb@f900000 { 641 compatible = "ti,am62-usb"; 642 reg = <0x00 0x0f900000 0x00 0x800>, 643 <0x00 0x0f908000 0x00 0x400>; 644 clocks = <&k3_clks 161 3>; 645 clock-names = "ref"; 646 ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>; 647 #address-cells = <2>; 648 #size-cells = <2>; 649 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 650 ranges; 651 status = "disabled"; 652 653 usb0: usb@31000000 { 654 compatible = "snps,dwc3"; 655 reg = <0x00 0x31000000 0x00 0x50000>; 656 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 657 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 658 interrupt-names = "host", "peripheral"; 659 maximum-speed = "high-speed"; 660 dr_mode = "otg"; 661 bootph-all; 662 snps,usb2-gadget-lpm-disable; 663 snps,usb2-lpm-disable; 664 }; 665 }; 666 667 fss: bus@fc00000 { 668 compatible = "simple-bus"; 669 reg = <0x00 0x0fc00000 0x00 0x70000>; 670 #address-cells = <2>; 671 #size-cells = <2>; 672 ranges; 673 674 ospi0: spi@fc40000 { 675 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 676 reg = <0x00 0x0fc40000 0x00 0x100>, 677 <0x05 0x00000000 0x01 0x00000000>; 678 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 679 cdns,fifo-depth = <256>; 680 cdns,fifo-width = <4>; 681 cdns,trigger-address = <0x0>; 682 clocks = <&k3_clks 75 7>; 683 assigned-clocks = <&k3_clks 75 7>; 684 assigned-clock-parents = <&k3_clks 75 8>; 685 assigned-clock-rates = <166666666>; 686 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 687 #address-cells = <1>; 688 #size-cells = <0>; 689 status = "disabled"; 690 }; 691 }; 692 693 cpsw3g: ethernet@8000000 { 694 compatible = "ti,am642-cpsw-nuss"; 695 #address-cells = <2>; 696 #size-cells = <2>; 697 reg = <0x00 0x08000000 0x00 0x200000>; 698 reg-names = "cpsw_nuss"; 699 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; 700 clocks = <&k3_clks 13 0>; 701 assigned-clocks = <&k3_clks 13 3>; 702 assigned-clock-parents = <&k3_clks 13 11>; 703 clock-names = "fck"; 704 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 705 status = "disabled"; 706 707 dmas = <&main_pktdma 0xc600 15>, 708 <&main_pktdma 0xc601 15>, 709 <&main_pktdma 0xc602 15>, 710 <&main_pktdma 0xc603 15>, 711 <&main_pktdma 0xc604 15>, 712 <&main_pktdma 0xc605 15>, 713 <&main_pktdma 0xc606 15>, 714 <&main_pktdma 0xc607 15>, 715 <&main_pktdma 0x4600 15>; 716 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 717 "tx7", "rx"; 718 719 ethernet-ports { 720 #address-cells = <1>; 721 #size-cells = <0>; 722 723 cpsw_port1: port@1 { 724 reg = <1>; 725 ti,mac-only; 726 label = "port1"; 727 phys = <&phy_gmii_sel 1>; 728 mac-address = [00 00 00 00 00 00]; 729 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; 730 status = "disabled"; 731 }; 732 733 cpsw_port2: port@2 { 734 reg = <2>; 735 ti,mac-only; 736 label = "port2"; 737 phys = <&phy_gmii_sel 2>; 738 mac-address = [00 00 00 00 00 00]; 739 status = "disabled"; 740 }; 741 }; 742 743 cpsw3g_mdio: mdio@f00 { 744 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 745 reg = <0x00 0xf00 0x00 0x100>; 746 #address-cells = <1>; 747 #size-cells = <0>; 748 clocks = <&k3_clks 13 0>; 749 clock-names = "fck"; 750 bus_freq = <1000000>; 751 status = "disabled"; 752 }; 753 754 cpts@3d000 { 755 compatible = "ti,j721e-cpts"; 756 reg = <0x00 0x3d000 0x00 0x400>; 757 clocks = <&k3_clks 13 3>; 758 clock-names = "cpts"; 759 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 760 interrupt-names = "cpts"; 761 ti,cpts-ext-ts-inputs = <4>; 762 ti,cpts-periodic-outputs = <2>; 763 }; 764 }; 765 766 hwspinlock: spinlock@2a000000 { 767 compatible = "ti,am64-hwspinlock"; 768 reg = <0x00 0x2a000000 0x00 0x1000>; 769 #hwlock-cells = <1>; 770 }; 771 772 mailbox0_cluster0: mailbox@29000000 { 773 compatible = "ti,am64-mailbox"; 774 reg = <0x00 0x29000000 0x00 0x200>; 775 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 776 #mbox-cells = <1>; 777 ti,mbox-num-users = <4>; 778 ti,mbox-num-fifos = <16>; 779 status = "disabled"; 780 }; 781 782 mailbox0_cluster1: mailbox@29010000 { 783 compatible = "ti,am64-mailbox"; 784 reg = <0x00 0x29010000 0x00 0x200>; 785 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 786 #mbox-cells = <1>; 787 ti,mbox-num-users = <4>; 788 ti,mbox-num-fifos = <16>; 789 status = "disabled"; 790 }; 791 792 mailbox0_cluster2: mailbox@29020000 { 793 compatible = "ti,am64-mailbox"; 794 reg = <0x00 0x29020000 0x00 0x200>; 795 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 796 #mbox-cells = <1>; 797 ti,mbox-num-users = <4>; 798 ti,mbox-num-fifos = <16>; 799 status = "disabled"; 800 }; 801 802 mailbox0_cluster3: mailbox@29030000 { 803 compatible = "ti,am64-mailbox"; 804 reg = <0x00 0x29030000 0x00 0x200>; 805 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 806 #mbox-cells = <1>; 807 ti,mbox-num-users = <4>; 808 ti,mbox-num-fifos = <16>; 809 status = "disabled"; 810 }; 811 812 ecap0: pwm@23100000 { 813 compatible = "ti,am3352-ecap"; 814 #pwm-cells = <3>; 815 reg = <0x00 0x23100000 0x00 0x100>; 816 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 817 clocks = <&k3_clks 51 0>; 818 clock-names = "fck"; 819 status = "disabled"; 820 }; 821 822 ecap1: pwm@23110000 { 823 compatible = "ti,am3352-ecap"; 824 #pwm-cells = <3>; 825 reg = <0x00 0x23110000 0x00 0x100>; 826 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 827 clocks = <&k3_clks 52 0>; 828 clock-names = "fck"; 829 status = "disabled"; 830 }; 831 832 ecap2: pwm@23120000 { 833 compatible = "ti,am3352-ecap"; 834 #pwm-cells = <3>; 835 reg = <0x00 0x23120000 0x00 0x100>; 836 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 837 clocks = <&k3_clks 53 0>; 838 clock-names = "fck"; 839 status = "disabled"; 840 }; 841 842 eqep0: counter@23200000 { 843 compatible = "ti,am62-eqep"; 844 reg = <0x00 0x23200000 0x00 0x100>; 845 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; 846 clocks = <&k3_clks 59 0>; 847 interrupts = <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>; 848 status = "disabled"; 849 }; 850 851 eqep1: counter@23210000 { 852 compatible = "ti,am62-eqep"; 853 reg = <0x00 0x23210000 0x00 0x100>; 854 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; 855 clocks = <&k3_clks 60 0>; 856 interrupts = <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>; 857 status = "disabled"; 858 }; 859 860 eqep2: counter@23220000 { 861 compatible = "ti,am62-eqep"; 862 reg = <0x00 0x23220000 0x00 0x100>; 863 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 864 clocks = <&k3_clks 62 0>; 865 interrupts = <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>; 866 status = "disabled"; 867 }; 868 869 main_mcan0: can@20701000 { 870 compatible = "bosch,m_can"; 871 reg = <0x00 0x20701000 0x00 0x200>, 872 <0x00 0x20708000 0x00 0x8000>; 873 reg-names = "m_can", "message_ram"; 874 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 875 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 876 clock-names = "hclk", "cclk"; 877 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 879 interrupt-names = "int0", "int1"; 880 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 881 status = "disabled"; 882 }; 883 884 main_mcan1: can@20711000 { 885 compatible = "bosch,m_can"; 886 reg = <0x00 0x20711000 0x00 0x200>, 887 <0x00 0x20718000 0x00 0x8000>; 888 reg-names = "m_can", "message_ram"; 889 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 890 clocks = <&k3_clks 99 6>, <&k3_clks 99 1>; 891 clock-names = "hclk", "cclk"; 892 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 894 interrupt-names = "int0", "int1"; 895 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 896 status = "disabled"; 897 }; 898 899 main_rti0: watchdog@e000000 { 900 compatible = "ti,j7-rti-wdt"; 901 reg = <0x00 0x0e000000 0x00 0x100>; 902 clocks = <&k3_clks 125 0>; 903 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 904 assigned-clocks = <&k3_clks 125 0>; 905 assigned-clock-parents = <&k3_clks 125 2>; 906 }; 907 908 main_rti1: watchdog@e010000 { 909 compatible = "ti,j7-rti-wdt"; 910 reg = <0x00 0x0e010000 0x00 0x100>; 911 clocks = <&k3_clks 126 0>; 912 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 913 assigned-clocks = <&k3_clks 126 0>; 914 assigned-clock-parents = <&k3_clks 126 2>; 915 }; 916 917 main_rti2: watchdog@e020000 { 918 compatible = "ti,j7-rti-wdt"; 919 reg = <0x00 0x0e020000 0x00 0x100>; 920 clocks = <&k3_clks 127 0>; 921 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; 922 assigned-clocks = <&k3_clks 127 0>; 923 assigned-clock-parents = <&k3_clks 127 2>; 924 }; 925 926 main_rti3: watchdog@e030000 { 927 compatible = "ti,j7-rti-wdt"; 928 reg = <0x00 0x0e030000 0x00 0x100>; 929 clocks = <&k3_clks 128 0>; 930 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; 931 assigned-clocks = <&k3_clks 128 0>; 932 assigned-clock-parents = <&k3_clks 128 2>; 933 }; 934 935 main_rti15: watchdog@e0f0000 { 936 compatible = "ti,j7-rti-wdt"; 937 reg = <0x00 0x0e0f0000 0x00 0x100>; 938 clocks = <&k3_clks 130 0>; 939 power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>; 940 assigned-clocks = <&k3_clks 130 0>; 941 assigned-clock-parents = <&k3_clks 130 2>; 942 }; 943 944 epwm0: pwm@23000000 { 945 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 946 #pwm-cells = <3>; 947 reg = <0x00 0x23000000 0x00 0x100>; 948 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 949 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 950 clock-names = "tbclk", "fck"; 951 status = "disabled"; 952 }; 953 954 epwm1: pwm@23010000 { 955 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 956 #pwm-cells = <3>; 957 reg = <0x00 0x23010000 0x00 0x100>; 958 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 959 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 960 clock-names = "tbclk", "fck"; 961 status = "disabled"; 962 }; 963 964 epwm2: pwm@23020000 { 965 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 966 #pwm-cells = <3>; 967 reg = <0x00 0x23020000 0x00 0x100>; 968 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 969 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 970 clock-names = "tbclk", "fck"; 971 status = "disabled"; 972 }; 973 974 mcasp0: audio-controller@2b00000 { 975 compatible = "ti,am33xx-mcasp-audio"; 976 reg = <0x00 0x02b00000 0x00 0x2000>, 977 <0x00 0x02b08000 0x00 0x400>; 978 reg-names = "mpu", "dat"; 979 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 981 interrupt-names = "tx", "rx"; 982 983 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; 984 dma-names = "tx", "rx"; 985 986 clocks = <&k3_clks 190 0>; 987 clock-names = "fck"; 988 assigned-clocks = <&k3_clks 190 0>; 989 assigned-clock-parents = <&k3_clks 190 2>; 990 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 991 status = "disabled"; 992 }; 993 994 mcasp1: audio-controller@2b10000 { 995 compatible = "ti,am33xx-mcasp-audio"; 996 reg = <0x00 0x02b10000 0x00 0x2000>, 997 <0x00 0x02b18000 0x00 0x400>; 998 reg-names = "mpu", "dat"; 999 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 1001 interrupt-names = "tx", "rx"; 1002 1003 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; 1004 dma-names = "tx", "rx"; 1005 1006 clocks = <&k3_clks 191 0>; 1007 clock-names = "fck"; 1008 assigned-clocks = <&k3_clks 191 0>; 1009 assigned-clock-parents = <&k3_clks 191 2>; 1010 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1011 status = "disabled"; 1012 }; 1013 1014 mcasp2: audio-controller@2b20000 { 1015 compatible = "ti,am33xx-mcasp-audio"; 1016 reg = <0x00 0x02b20000 0x00 0x2000>, 1017 <0x00 0x02b28000 0x00 0x400>; 1018 reg-names = "mpu", "dat"; 1019 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1021 interrupt-names = "tx", "rx"; 1022 1023 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; 1024 dma-names = "tx", "rx"; 1025 1026 clocks = <&k3_clks 192 0>; 1027 clock-names = "fck"; 1028 assigned-clocks = <&k3_clks 192 0>; 1029 assigned-clock-parents = <&k3_clks 192 2>; 1030 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1031 status = "disabled"; 1032 }; 1033 1034 ti_csi2rx0: ticsi2rx@30102000 { 1035 compatible = "ti,j721e-csi2rx-shim"; 1036 reg = <0x00 0x30102000 0x00 0x1000>; 1037 ranges; 1038 #address-cells = <2>; 1039 #size-cells = <2>; 1040 dmas = <&main_bcdma_csi 0 0x5000 0>; 1041 dma-names = "rx0"; 1042 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1043 status = "disabled"; 1044 1045 cdns_csi2rx0: csi-bridge@30101000 { 1046 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 1047 reg = <0x00 0x30101000 0x00 0x1000>; 1048 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, 1049 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; 1050 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 1051 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 1052 phys = <&dphy0>; 1053 phy-names = "dphy"; 1054 1055 ports { 1056 #address-cells = <1>; 1057 #size-cells = <0>; 1058 1059 csi0_port0: port@0 { 1060 reg = <0>; 1061 status = "disabled"; 1062 }; 1063 1064 csi0_port1: port@1 { 1065 reg = <1>; 1066 status = "disabled"; 1067 }; 1068 1069 csi0_port2: port@2 { 1070 reg = <2>; 1071 status = "disabled"; 1072 }; 1073 1074 csi0_port3: port@3 { 1075 reg = <3>; 1076 status = "disabled"; 1077 }; 1078 1079 csi0_port4: port@4 { 1080 reg = <4>; 1081 status = "disabled"; 1082 }; 1083 }; 1084 }; 1085 }; 1086 1087 dphy0: phy@30110000 { 1088 compatible = "cdns,dphy-rx"; 1089 reg = <0x00 0x30110000 0x00 0x1100>; 1090 #phy-cells = <0>; 1091 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1092 status = "disabled"; 1093 }; 1094 1095 vpu: video-codec@30210000 { 1096 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 1097 reg = <0x00 0x30210000 0x00 0x10000>; 1098 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&k3_clks 204 2>; 1100 power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; 1101 }; 1102}; 1103