1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2023 - 2024 PHYTEC America LLC 4 * Author: Garrett Giordano <ggiordano@phytec.com> 5 * 6 * Product homepage: 7 * https://www.phytec.com/product/phycore-am62a 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/leds/common.h> 12#include <dt-bindings/net/ti-dp83867.h> 13 14/ { 15 model = "PHYTEC phyCORE-AM62Ax"; 16 compatible = "phytec,am62a-phycore-som", "ti,am62a7"; 17 18 aliases { 19 ethernet0 = &cpsw_port1; 20 gpio0 = &main_gpio0; 21 gpio1 = &main_gpio1; 22 i2c0 = &main_i2c0; 23 mmc0 = &sdhci0; 24 rtc0 = &i2c_som_rtc; 25 spi0 = &ospi0; 26 }; 27 28 leds { 29 compatible = "gpio-leds"; 30 pinctrl-names = "default"; 31 pinctrl-0 = <&leds_pins_default>; 32 33 led-0 { 34 color = <LED_COLOR_ID_GREEN>; 35 gpios = <&main_gpio0 13 GPIO_ACTIVE_HIGH>; 36 linux,default-trigger = "heartbeat"; 37 function = LED_FUNCTION_HEARTBEAT; 38 }; 39 }; 40 41 memory@80000000 { 42 device_type = "memory"; 43 /* 2G RAM */ 44 reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 45 bootph-all; 46 }; 47 48 reserved-memory { 49 #address-cells = <2>; 50 #size-cells = <2>; 51 ranges; 52 53 /* global cma region */ 54 linux,cma { 55 compatible = "shared-dma-pool"; 56 reusable; 57 size = <0x00 0x24000000>; 58 alloc-ranges = <0x00 0xc0000000 0x00 0x24000000>; 59 linux,cma-default; 60 }; 61 62 c7x_0_dma_memory_region: c7x-dma-memory@99800000 { 63 compatible = "shared-dma-pool"; 64 reg = <0x00 0x99800000 0x00 0x100000>; 65 no-map; 66 }; 67 68 c7x_0_memory_region: c7x-memory@99900000 { 69 compatible = "shared-dma-pool"; 70 reg = <0x00 0x99900000 0x00 0xf00000>; 71 no-map; 72 }; 73 74 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { 75 compatible = "shared-dma-pool"; 76 reg = <0x00 0x9b800000 0x00 0x100000>; 77 no-map; 78 }; 79 80 mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { 81 compatible = "shared-dma-pool"; 82 reg = <0x00 0x9b900000 0x00 0xf00000>; 83 no-map; 84 }; 85 86 wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { 87 compatible = "shared-dma-pool"; 88 reg = <0x00 0x9c800000 0x00 0x100000>; 89 no-map; 90 }; 91 92 wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { 93 compatible = "shared-dma-pool"; 94 reg = <0x00 0x9c900000 0x00 0xf00000>; 95 no-map; 96 }; 97 98 secure_tfa_ddr: tfa@9e780000 { 99 reg = <0x00 0x9e780000 0x00 0x80000>; 100 alignment = <0x1000>; 101 no-map; 102 }; 103 104 secure_ddr: optee@9e800000 { 105 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 106 alignment = <0x1000>; 107 no-map; 108 }; 109 }; 110 111 vcc_5v0_som: regulator-vcc-5v0-som { 112 compatible = "regulator-fixed"; 113 regulator-name = "VCC_5V0_SOM"; 114 regulator-min-microvolt = <5000000>; 115 regulator-max-microvolt = <5000000>; 116 regulator-always-on; 117 regulator-boot-on; 118 }; 119}; 120 121&main_pmx0 { 122 leds_pins_default: leds-default-pins { 123 pinctrl-single,pins = < 124 AM62AX_IOPAD(0x034, PIN_OUTPUT, 7) /* (K20) OSPI0_CSN2.GPIO0_13 */ 125 >; 126 }; 127 128 main_i2c0_pins_default: main-i2c0-default-pins { 129 pinctrl-single,pins = < 130 AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (D17) I2C0_SCL */ 131 AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (E16) I2C0_SDA */ 132 >; 133 bootph-all; 134 }; 135 136 main_mdio1_pins_default: main-mdio1-default-pins { 137 pinctrl-single,pins = < 138 AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */ 139 AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */ 140 >; 141 bootph-all; 142 }; 143 144 main_mmc0_pins_default: main-mmc0-default-pins { 145 pinctrl-single,pins = < 146 AM62AX_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (Y6) MMC0_CMD */ 147 AM62AX_IOPAD(0x218, PIN_INPUT_PULLDOWN, 0) /* (AB7) MMC0_CLK */ 148 AM62AX_IOPAD(0x214, PIN_INPUT_PULLUP, 0) /* (AA6) MMC0_DAT0 */ 149 AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AB6) MMC0_DAT1 */ 150 AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (Y7) MMC0_DAT2 */ 151 AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (AA7) MMC0_DAT3 */ 152 AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (Y8) MMC0_DAT4 */ 153 AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (W7) MMC0_DAT5 */ 154 AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (W9) MMC0_DAT6 */ 155 AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AB8) MMC0_DAT7 */ 156 >; 157 bootph-all; 158 }; 159 160 main_rgmii1_pins_default: main-rgmii1-default-pins { 161 pinctrl-single,pins = < 162 AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */ 163 AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */ 164 AM62AX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */ 165 AM62AX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */ 166 AM62AX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */ 167 AM62AX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */ 168 AM62AX_IOPAD(0x134, PIN_OUTPUT, 0) /* (Y17) RGMII1_TD0 */ 169 AM62AX_IOPAD(0x138, PIN_OUTPUT, 0) /* (V16) RGMII1_TD1 */ 170 AM62AX_IOPAD(0x13c, PIN_OUTPUT, 0) /* (Y16) RGMII1_TD2 */ 171 AM62AX_IOPAD(0x140, PIN_OUTPUT, 0) /* (AA17) RGMII1_TD3 */ 172 AM62AX_IOPAD(0x130, PIN_OUTPUT, 0) /* (AB17) RGMII1_TXC */ 173 AM62AX_IOPAD(0x12c, PIN_OUTPUT, 0) /* (W16) RGMII1_TX_CTL */ 174 >; 175 bootph-all; 176 }; 177 178 ospi0_pins_default: ospi0-default-pins { 179 pinctrl-single,pins = < 180 AM62AX_IOPAD(0x000, PIN_OUTPUT, 0) /* (L22) OSPI0_CLK */ 181 AM62AX_IOPAD(0x02c, PIN_OUTPUT, 0) /* (H21) OSPI0_CSn0 */ 182 AM62AX_IOPAD(0x038, PIN_OUTPUT, 0) /* (G20) OSPI0_CSn3 */ 183 AM62AX_IOPAD(0x00c, PIN_INPUT, 0) /* (J21) OSPI0_D0 */ 184 AM62AX_IOPAD(0x010, PIN_INPUT, 0) /* (J18) OSPI0_D1 */ 185 AM62AX_IOPAD(0x014, PIN_INPUT, 0) /* (J19) OSPI0_D2 */ 186 AM62AX_IOPAD(0x018, PIN_INPUT, 0) /* (H18) OSPI0_D3 */ 187 AM62AX_IOPAD(0x01c, PIN_INPUT, 0) /* (K21) OSPI0_D4 */ 188 AM62AX_IOPAD(0x020, PIN_INPUT, 0) /* (H19) OSPI0_D5 */ 189 AM62AX_IOPAD(0x024, PIN_INPUT, 0) /* (J20) OSPI0_D6 */ 190 AM62AX_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ 191 AM62AX_IOPAD(0x008, PIN_INPUT, 0) /* (L21) OSPI0_DQS */ 192 >; 193 bootph-all; 194 }; 195 196 pmic_irq_pins_default: pmic-irq-default-pins { 197 pinctrl-single,pins = < 198 AM62AX_IOPAD(0x1f4, PIN_INPUT, 0) /* (D16) EXTINTn */ 199 >; 200 }; 201}; 202 203&c7x_0 { 204 mboxes = <&mailbox0_cluster1 &mbox_c7x_0>; 205 memory-region = <&c7x_0_dma_memory_region>, 206 <&c7x_0_memory_region>; 207 status = "okay"; 208}; 209 210&cpsw3g { 211 pinctrl-names = "default"; 212 pinctrl-0 = <&main_rgmii1_pins_default>; 213 status = "okay"; 214}; 215 216&cpsw_port1 { 217 phy-mode = "rgmii-rxid"; 218 phy-handle = <&cpsw3g_phy1>; 219 bootph-all; 220}; 221 222&cpsw3g_mdio { 223 pinctrl-names = "default"; 224 pinctrl-0 = <&main_mdio1_pins_default>; 225 226 cpsw3g_phy1: ethernet-phy@1 { 227 compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; 228 reg = <1>; 229 bootph-all; 230 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 231 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 232 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 233 }; 234}; 235 236&fss { 237 status = "okay"; 238}; 239 240&mailbox0_cluster0 { 241 status = "okay"; 242 243 mbox_r5_0: mbox-r5-0 { 244 ti,mbox-rx = <0 0 0>; 245 ti,mbox-tx = <1 0 0>; 246 }; 247}; 248 249&mailbox0_cluster1 { 250 status = "okay"; 251 252 mbox_c7x_0: mbox-c7x-0 { 253 ti,mbox-rx = <0 0 0>; 254 ti,mbox-tx = <1 0 0>; 255 }; 256}; 257 258&mailbox0_cluster2 { 259 status = "okay"; 260 261 mbox_mcu_r5_0: mbox-mcu-r5-0 { 262 ti,mbox-rx = <0 0 0>; 263 ti,mbox-tx = <1 0 0>; 264 }; 265}; 266 267&main_i2c0 { 268 pinctrl-names = "default"; 269 pinctrl-0 = <&main_i2c0_pins_default>; 270 clock-frequency = <400000>; 271 bootph-all; 272 status = "okay"; 273 274 pmic@30 { 275 compatible = "ti,tps65219"; 276 reg = <0x30>; 277 buck1-supply = <&vcc_5v0_som>; 278 buck2-supply = <&vcc_5v0_som>; 279 buck3-supply = <&vcc_5v0_som>; 280 ldo1-supply = <&vdd_3v3>; 281 ldo2-supply = <&vdd_1v8>; 282 ldo3-supply = <&vcc_5v0_som>; 283 ldo4-supply = <&vcc_5v0_som>; 284 285 pinctrl-names = "default"; 286 pinctrl-0 = <&pmic_irq_pins_default>; 287 interrupt-parent = <&gic500>; 288 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 289 interrupt-controller; 290 #interrupt-cells = <1>; 291 system-power-controller; 292 ti,power-button; 293 294 regulators { 295 vdd_3v3: buck1 { 296 regulator-name = "VDD_3V3"; 297 regulator-min-microvolt = <3300000>; 298 regulator-max-microvolt = <3300000>; 299 regulator-boot-on; 300 regulator-always-on; 301 }; 302 303 vdd_1v8: buck2 { 304 regulator-name = "VDD_1V8"; 305 regulator-min-microvolt = <1800000>; 306 regulator-max-microvolt = <1800000>; 307 regulator-boot-on; 308 regulator-always-on; 309 }; 310 311 vdd_lpddr4: buck3 { 312 regulator-name = "VDD_LPDDR4"; 313 regulator-min-microvolt = <1100000>; 314 regulator-max-microvolt = <1100000>; 315 regulator-boot-on; 316 regulator-always-on; 317 }; 318 319 vddshv5_sdio: ldo1 { 320 regulator-name = "VDDSHV5_SDIO"; 321 regulator-min-microvolt = <3300000>; 322 regulator-max-microvolt = <3300000>; 323 regulator-allow-bypass; 324 regulator-boot-on; 325 regulator-always-on; 326 }; 327 328 vddr_core: ldo2 { 329 regulator-name = "VDDR_CORE"; 330 regulator-min-microvolt = <850000>; 331 regulator-max-microvolt = <850000>; 332 regulator-boot-on; 333 regulator-always-on; 334 }; 335 336 vdda_1v8: ldo3 { 337 regulator-name = "VDDA_1V8"; 338 regulator-min-microvolt = <1800000>; 339 regulator-max-microvolt = <1800000>; 340 regulator-boot-on; 341 regulator-always-on; 342 }; 343 344 vdd_2v5: ldo4 { 345 regulator-name = "VDD_2V5"; 346 regulator-min-microvolt = <2500000>; 347 regulator-max-microvolt = <2500000>; 348 regulator-boot-on; 349 regulator-always-on; 350 }; 351 }; 352 }; 353 354 eeprom@50 { 355 compatible = "atmel,24c32"; 356 pagesize = <32>; 357 reg = <0x50>; 358 }; 359 360 i2c_som_rtc: rtc@52 { 361 compatible = "microcrystal,rv3028"; 362 reg = <0x52>; 363 }; 364}; 365 366&main_gpio0 { 367 status = "okay"; 368}; 369 370&main_gpio1 { 371 status = "okay"; 372}; 373 374&main_gpio_intr { 375 status = "okay"; 376}; 377 378&main_pktdma { 379 bootph-all; 380}; 381 382/* main_rti4 is used by C7x DSP */ 383&main_rti4 { 384 status = "reserved"; 385}; 386 387/* main_timer2 is used by C7x DSP */ 388&main_timer2 { 389 status = "reserved"; 390}; 391 392&mcu_r5fss0 { 393 status = "okay"; 394}; 395 396&mcu_r5fss0_core0 { 397 mboxes = <&mailbox0_cluster2 &mbox_mcu_r5_0>; 398 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 399 <&mcu_r5fss0_core0_memory_region>; 400}; 401 402&ospi0 { 403 pinctrl-names = "default"; 404 pinctrl-0 = <&ospi0_pins_default>; 405 status = "okay"; 406 407 serial_flash: flash@0 { 408 compatible = "jedec,spi-nor"; 409 reg = <0x0>; 410 spi-tx-bus-width = <8>; 411 spi-rx-bus-width = <8>; 412 spi-max-frequency = <25000000>; 413 cdns,tshsl-ns = <60>; 414 cdns,tsd2d-ns = <60>; 415 cdns,tchsh-ns = <60>; 416 cdns,tslch-ns = <60>; 417 cdns,read-delay = <0>; 418 bootph-all; 419 }; 420}; 421 422&sdhci0 { 423 pinctrl-names = "default"; 424 pinctrl-0 = <&main_mmc0_pins_default>; 425 non-removable; 426 bootph-all; 427 status = "okay"; 428}; 429 430&wkup_r5fss0 { 431 status = "okay"; 432}; 433 434&wkup_r5fss0_core0 { 435 mboxes = <&mailbox0_cluster0 &mbox_r5_0>; 436 memory-region = <&wkup_r5fss0_core0_dma_memory_region>, 437 <&wkup_r5fss0_core0_memory_region>; 438}; 439