1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2020-2023 Intel Corporation
4 */
5
6 #ifndef __IVPU_HW_REG_IO_H__
7 #define __IVPU_HW_REG_IO_H__
8
9 #include <linux/bitfield.h>
10 #include <linux/fault-inject.h>
11 #include <linux/io.h>
12 #include <linux/iopoll.h>
13
14 #include "ivpu_drv.h"
15
16 #define REG_POLL_SLEEP_US 50
17 #define REG_IO_ERROR 0xffffffff
18
19 #define REGB_RD32(reg) ivpu_hw_reg_rd32(vdev, vdev->regb, (reg), #reg, __func__)
20 #define REGB_RD64(reg) ivpu_hw_reg_rd64(vdev, vdev->regb, (reg), #reg, __func__)
21 #define REGB_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regb, (reg), (val), #reg, __func__)
22 #define REGB_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regb, (reg), (val), #reg, __func__)
23
24 #define REGV_RD32(reg) ivpu_hw_reg_rd32(vdev, vdev->regv, (reg), #reg, __func__)
25 #define REGV_RD64(reg) ivpu_hw_reg_rd64(vdev, vdev->regv, (reg), #reg, __func__)
26 #define REGV_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regv, (reg), (val), #reg, __func__)
27 #define REGV_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regv, (reg), (val), #reg, __func__)
28
29 #define REGV_WR32I(reg, stride, index, val) \
30 ivpu_hw_reg_wr32_index(vdev, vdev->regv, (reg), (stride), (index), (val), #reg, __func__)
31
32 #define REG_FLD(REG, FLD) \
33 (REG##_##FLD##_MASK)
34 #define REG_FLD_NUM(REG, FLD, num) \
35 FIELD_PREP(REG##_##FLD##_MASK, num)
36 #define REG_GET_FLD(REG, FLD, val) \
37 FIELD_GET(REG##_##FLD##_MASK, val)
38 #define REG_CLR_FLD(REG, FLD, val) \
39 ((val) & ~(REG##_##FLD##_MASK))
40 #define REG_SET_FLD(REG, FLD, val) \
41 ((val) | (REG##_##FLD##_MASK))
42 #define REG_SET_FLD_NUM(REG, FLD, num, val) \
43 (((val) & ~(REG##_##FLD##_MASK)) | FIELD_PREP(REG##_##FLD##_MASK, num))
44 #define REG_TEST_FLD(REG, FLD, val) \
45 ((REG##_##FLD##_MASK) == ((val) & (REG##_##FLD##_MASK)))
46 #define REG_TEST_FLD_NUM(REG, FLD, num, val) \
47 ((num) == FIELD_GET(REG##_##FLD##_MASK, val))
48
49 #define REGB_POLL_FLD(reg, fld, exp_fld_val, timeout_us) \
50 ivpu_hw_reg_poll_fld(vdev, vdev->regb, reg, reg##_##fld##_MASK, \
51 FIELD_PREP(reg##_##fld##_MASK, exp_fld_val), timeout_us, \
52 __func__, #reg, #fld)
53
54 #define REGV_POLL_FLD(reg, fld, exp_fld_val, timeout_us) \
55 ivpu_hw_reg_poll_fld(vdev, vdev->regv, reg, reg##_##fld##_MASK, \
56 FIELD_PREP(reg##_##fld##_MASK, exp_fld_val), timeout_us, \
57 __func__, #reg, #fld)
58
59 extern struct fault_attr ivpu_hw_failure;
60
61 static inline int __must_check
ivpu_hw_reg_poll_fld(struct ivpu_device * vdev,void __iomem * base,u32 reg_offset,u32 reg_mask,u32 exp_masked_val,u32 timeout_us,const char * func_name,const char * reg_name,const char * fld_name)62 ivpu_hw_reg_poll_fld(struct ivpu_device *vdev, void __iomem *base,
63 u32 reg_offset, u32 reg_mask, u32 exp_masked_val, u32 timeout_us,
64 const char *func_name, const char *reg_name, const char *fld_name)
65 {
66 u32 reg_val;
67 int ret;
68
69 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) POLL %s started (exp_val 0x%x)\n",
70 func_name, reg_name, reg_offset, fld_name, exp_masked_val);
71
72 ret = read_poll_timeout(readl, reg_val, (reg_val & reg_mask) == exp_masked_val,
73 REG_POLL_SLEEP_US, timeout_us, false, base + reg_offset);
74
75 #ifdef CONFIG_FAULT_INJECTION
76 if (should_fail(&ivpu_hw_failure, 1))
77 ret = -ETIMEDOUT;
78 #endif
79
80 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) POLL %s %s (reg_val 0x%08x)\n",
81 func_name, reg_name, reg_offset, fld_name, ret ? "ETIMEDOUT" : "OK", reg_val);
82
83 return ret;
84 }
85
86 static inline u32
ivpu_hw_reg_rd32(struct ivpu_device * vdev,void __iomem * base,u32 reg,const char * name,const char * func)87 ivpu_hw_reg_rd32(struct ivpu_device *vdev, void __iomem *base, u32 reg,
88 const char *name, const char *func)
89 {
90 u32 val = readl(base + reg);
91
92 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) RD: 0x%08x\n", func, name, reg, val);
93 return val;
94 }
95
96 static inline u64
ivpu_hw_reg_rd64(struct ivpu_device * vdev,void __iomem * base,u32 reg,const char * name,const char * func)97 ivpu_hw_reg_rd64(struct ivpu_device *vdev, void __iomem *base, u32 reg,
98 const char *name, const char *func)
99 {
100 u64 val = readq(base + reg);
101
102 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) RD: 0x%016llx\n", func, name, reg, val);
103 return val;
104 }
105
106 static inline void
ivpu_hw_reg_wr32(struct ivpu_device * vdev,void __iomem * base,u32 reg,u32 val,const char * name,const char * func)107 ivpu_hw_reg_wr32(struct ivpu_device *vdev, void __iomem *base, u32 reg, u32 val,
108 const char *name, const char *func)
109 {
110 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) WR: 0x%08x\n", func, name, reg, val);
111 writel(val, base + reg);
112 }
113
114 static inline void
ivpu_hw_reg_wr64(struct ivpu_device * vdev,void __iomem * base,u32 reg,u64 val,const char * name,const char * func)115 ivpu_hw_reg_wr64(struct ivpu_device *vdev, void __iomem *base, u32 reg, u64 val,
116 const char *name, const char *func)
117 {
118 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) WR: 0x%016llx\n", func, name, reg, val);
119 writeq(val, base + reg);
120 }
121
122 static inline void
ivpu_hw_reg_wr32_index(struct ivpu_device * vdev,void __iomem * base,u32 reg,u32 stride,u32 index,u32 val,const char * name,const char * func)123 ivpu_hw_reg_wr32_index(struct ivpu_device *vdev, void __iomem *base, u32 reg,
124 u32 stride, u32 index, u32 val, const char *name,
125 const char *func)
126 {
127 reg += index * stride;
128
129 ivpu_dbg(vdev, REG, "%s WR: %s_%d (0x%08x) <= 0x%08x\n", func, name, index, reg, val);
130 writel(val, base + reg);
131 }
132
133 #endif /* __IVPU_HW_REG_IO_H__ */
134