1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
4  */
5 
6 #ifndef __IRIS_VPU_BUFFER_H__
7 #define __IRIS_VPU_BUFFER_H__
8 
9 struct iris_inst;
10 
11 #define MIN_BUFFERS			4
12 
13 #define DMA_ALIGNMENT			256
14 
15 #define NUM_HW_PIC_BUF			32
16 #define SIZE_HW_PIC(size_per_buf)	(NUM_HW_PIC_BUF * (size_per_buf))
17 
18 #define MAX_TILE_COLUMNS		32
19 #define BIN_BUFFER_THRESHOLD		(1280 * 736)
20 #define VPP_CMD_MAX_SIZE		(BIT(20))
21 #define H264D_MAX_SLICE			1800
22 
23 #define SIZE_H264D_BUFTAB_T		256
24 #define SIZE_H264D_BSE_CMD_PER_BUF	(32 * 4)
25 #define SIZE_H264D_VPP_CMD_PER_BUF	512
26 
27 #define NUM_SLIST_BUF_H264		(256 + 32)
28 #define SIZE_SLIST_BUF_H264		512
29 #define H264_DISPLAY_BUF_SIZE		3328
30 #define H264_NUM_FRM_INFO		66
31 
32 #define SIZE_SEI_USERDATA		4096
33 
34 #define H264_CABAC_HDR_RATIO_HD_TOT	1
35 #define H264_CABAC_RES_RATIO_HD_TOT	3
36 #define SIZE_H264D_HW_PIC_T		(BIT(11))
37 
38 #define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE	64
39 #define MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE	16
40 #define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE	384
41 #define MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE	640
42 
size_h264d_lb_fe_top_data(u32 frame_width)43 static inline u32 size_h264d_lb_fe_top_data(u32 frame_width)
44 {
45 	return MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE * ALIGN(frame_width, 16) * 3;
46 }
47 
size_h264d_lb_fe_top_ctrl(u32 frame_width)48 static inline u32 size_h264d_lb_fe_top_ctrl(u32 frame_width)
49 {
50 	return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16);
51 }
52 
size_h264d_lb_fe_left_ctrl(u32 frame_height)53 static inline u32 size_h264d_lb_fe_left_ctrl(u32 frame_height)
54 {
55 	return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_height, 16);
56 }
57 
size_h264d_lb_se_top_ctrl(u32 frame_width)58 static inline u32 size_h264d_lb_se_top_ctrl(u32 frame_width)
59 {
60 	return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16);
61 }
62 
size_h264d_lb_se_left_ctrl(u32 frame_height)63 static inline u32 size_h264d_lb_se_left_ctrl(u32 frame_height)
64 {
65 	return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_height, 16);
66 }
67 
size_h264d_lb_pe_top_data(u32 frame_width)68 static inline u32 size_h264d_lb_pe_top_data(u32 frame_width)
69 {
70 	return MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16);
71 }
72 
size_h264d_lb_vsp_top(u32 frame_width)73 static inline u32 size_h264d_lb_vsp_top(u32 frame_width)
74 {
75 	return (DIV_ROUND_UP(frame_width, 16) << 7);
76 }
77 
size_h264d_lb_recon_dma_metadata_wr(u32 frame_height)78 static inline u32 size_h264d_lb_recon_dma_metadata_wr(u32 frame_height)
79 {
80 	return ALIGN(frame_height, 16) * 32;
81 }
82 
size_h264d_qp(u32 frame_width,u32 frame_height)83 static inline u32 size_h264d_qp(u32 frame_width, u32 frame_height)
84 {
85 	return DIV_ROUND_UP(frame_width, 64) * DIV_ROUND_UP(frame_height, 64) * 128;
86 }
87 
88 int iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
89 int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffer_type);
90 
91 #endif
92