1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
4  */
5 
6 #ifndef __IRIS_CORE_H__
7 #define __IRIS_CORE_H__
8 
9 #include <linux/types.h>
10 #include <linux/pm_domain.h>
11 #include <media/v4l2-device.h>
12 
13 #include "iris_hfi_common.h"
14 #include "iris_hfi_queue.h"
15 #include "iris_platform_common.h"
16 #include "iris_resources.h"
17 #include "iris_state.h"
18 
19 struct icc_info {
20 	const char		*name;
21 	u32			bw_min_kbps;
22 	u32			bw_max_kbps;
23 };
24 
25 #define IRIS_FW_VERSION_LENGTH		128
26 #define IFACEQ_CORE_PKT_SIZE		(1024 * 4)
27 
28 /**
29  * struct iris_core - holds core parameters valid for all instances
30  *
31  * @dev: reference to device structure
32  * @reg_base: IO memory base address
33  * @irq: iris irq
34  * @v4l2_dev: a holder for v4l2 device structure
35  * @vdev_dec: iris video device structure for decoder
36  * @iris_v4l2_file_ops: iris v4l2 file ops
37  * @iris_v4l2_ioctl_ops: iris v4l2 ioctl ops
38  * @iris_vb2_ops: iris vb2 ops
39  * @icc_tbl: table of iris interconnects
40  * @icc_count: count of iris interconnects
41  * @pmdomain_tbl: table of iris power domains
42  * @opp_pmdomain_tbl: table of opp power domains
43  * @clock_tbl: table of iris clocks
44  * @clk_count: count of iris clocks
45  * @resets: table of iris reset clocks
46  * @iris_platform_data: a structure for platform data
47  * @state: current state of core
48  * @iface_q_table_daddr: device address for interface queue table memory
49  * @sfr_daddr: device address for SFR (Sub System Failure Reason) register memory
50  * @iface_q_table_vaddr: virtual address for interface queue table memory
51  * @sfr_vaddr: virtual address for SFR (Sub System Failure Reason) register memory
52  * @command_queue: shared interface queue to send commands to firmware
53  * @message_queue: shared interface queue to receive responses from firmware
54  * @debug_queue: shared interface queue to receive debug info from firmware
55  * @lock: a lock for this strucure
56  * @response_packet: a pointer to response packet from fw to driver
57  * @header_id: id of packet header
58  * @packet_id: id of packet
59  * @power: a structure for clock and bw information
60  * @hfi_ops: iris hfi command ops
61  * @hfi_response_ops: iris hfi response ops
62  * @core_init_done: structure of signal completion for system response
63  * @intr_status: interrupt status
64  * @sys_error_handler: a delayed work for handling system fatal error
65  * @instances: a list_head of all instances
66  * @inst_fw_caps: an array of supported instance capabilities
67  */
68 
69 struct iris_core {
70 	struct device				*dev;
71 	void __iomem				*reg_base;
72 	int					irq;
73 	struct v4l2_device			v4l2_dev;
74 	struct video_device			*vdev_dec;
75 	const struct v4l2_file_operations	*iris_v4l2_file_ops;
76 	const struct v4l2_ioctl_ops		*iris_v4l2_ioctl_ops;
77 	const struct vb2_ops			*iris_vb2_ops;
78 	struct icc_bulk_data			*icc_tbl;
79 	u32					icc_count;
80 	struct dev_pm_domain_list		*pmdomain_tbl;
81 	struct dev_pm_domain_list		*opp_pmdomain_tbl;
82 	struct clk_bulk_data			*clock_tbl;
83 	u32					clk_count;
84 	struct reset_control_bulk_data		*resets;
85 	const struct iris_platform_data		*iris_platform_data;
86 	enum iris_core_state			state;
87 	dma_addr_t				iface_q_table_daddr;
88 	dma_addr_t				sfr_daddr;
89 	void					*iface_q_table_vaddr;
90 	void					*sfr_vaddr;
91 	struct iris_iface_q_info		command_queue;
92 	struct iris_iface_q_info		message_queue;
93 	struct iris_iface_q_info		debug_queue;
94 	struct mutex				lock; /* lock for core related operations */
95 	u8					*response_packet;
96 	u32					header_id;
97 	u32					packet_id;
98 	struct iris_core_power			power;
99 	const struct iris_hfi_command_ops	*hfi_ops;
100 	const struct iris_hfi_response_ops	*hfi_response_ops;
101 	struct completion			core_init_done;
102 	u32					intr_status;
103 	struct delayed_work			sys_error_handler;
104 	struct list_head			instances;
105 	struct platform_inst_fw_cap		inst_fw_caps[INST_FW_CAP_MAX];
106 };
107 
108 int iris_core_init(struct iris_core *core);
109 void iris_core_deinit(struct iris_core *core);
110 
111 #endif
112