1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright © 2019 Intel Corporation
4 */
5
6 #ifndef __INTEL_DP_H__
7 #define __INTEL_DP_H__
8
9 #include <linux/types.h>
10
11 enum intel_output_format;
12 enum pipe;
13 enum port;
14 struct drm_connector_state;
15 struct drm_dp_vsc_sdp;
16 struct drm_encoder;
17 struct drm_modeset_acquire_ctx;
18 struct intel_atomic_state;
19 struct intel_connector;
20 struct intel_crtc_state;
21 struct intel_digital_port;
22 struct intel_display;
23 struct intel_dp;
24 struct intel_encoder;
25
26 struct link_config_limits {
27 int min_rate, max_rate;
28 int min_lane_count, max_lane_count;
29 struct {
30 /* Uncompressed DSC input or link output bpp in 1 bpp units */
31 int min_bpp, max_bpp;
32 } pipe;
33 struct {
34 /* Compressed or uncompressed link output bpp in 1/16 bpp units */
35 int min_bpp_x16, max_bpp_x16;
36 } link;
37 };
38
39 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
40 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
41 const struct drm_connector_state *conn_state);
42 int intel_dp_min_bpp(enum intel_output_format output_format);
43 void intel_dp_init_modeset_retry_work(struct intel_connector *connector);
44 void
45 intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,
46 struct intel_encoder *encoder,
47 const struct intel_crtc_state *crtc_state);
48 bool intel_dp_init_connector(struct intel_digital_port *dig_port,
49 struct intel_connector *intel_connector);
50 void intel_dp_connector_sync_state(struct intel_connector *connector,
51 const struct intel_crtc_state *crtc_state);
52 void intel_dp_set_link_params(struct intel_dp *intel_dp,
53 int link_rate, int lane_count);
54 int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
55 struct drm_modeset_acquire_ctx *ctx,
56 u8 *pipe_mask);
57 void intel_dp_flush_connector_commits(struct intel_connector *connector);
58 void intel_dp_link_check(struct intel_encoder *encoder);
59 void intel_dp_check_link_state(struct intel_dp *intel_dp);
60 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode);
61 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
62 const struct intel_crtc_state *crtc_state);
63 void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
64 struct intel_connector *connector,
65 const struct intel_crtc_state *new_crtc_state);
66 void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
67 struct intel_connector *connector,
68 const struct intel_crtc_state *old_crtc_state);
69 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
70 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder);
71 void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
72 int intel_dp_compute_config(struct intel_encoder *encoder,
73 struct intel_crtc_state *pipe_config,
74 struct drm_connector_state *conn_state);
75 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
76 struct intel_crtc_state *pipe_config,
77 struct drm_connector_state *conn_state,
78 const struct link_config_limits *limits,
79 int timeslots);
80 void intel_dp_audio_compute_config(struct intel_encoder *encoder,
81 struct intel_crtc_state *pipe_config,
82 struct drm_connector_state *conn_state);
83 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);
84 bool intel_dp_is_edp(struct intel_dp *intel_dp);
85 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
86 bool intel_dp_has_dsc(const struct intel_connector *connector);
87 int intel_dp_link_symbol_size(int rate);
88 int intel_dp_link_symbol_clock(int rate);
89 bool intel_dp_is_port_edp(struct intel_display *display, enum port port);
90 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
91 bool long_hpd);
92 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
93 const struct drm_connector_state *conn_state);
94 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
95 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
96 void intel_dp_mst_suspend(struct intel_display *display);
97 void intel_dp_mst_resume(struct intel_display *display);
98 int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port);
99 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
100 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
101 int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state);
102 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
103 int intel_dp_max_common_rate(struct intel_dp *intel_dp);
104 int intel_dp_max_common_lane_count(struct intel_dp *intel_dp);
105 int intel_dp_common_rate(struct intel_dp *intel_dp, int index);
106 int intel_dp_rate_index(const int *rates, int len, int rate);
107 int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count);
108 void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count);
109 void intel_dp_update_sink_caps(struct intel_dp *intel_dp);
110 void intel_dp_reset_link_params(struct intel_dp *intel_dp);
111
112 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
113 u8 *link_bw, u8 *rate_select);
114 bool intel_dp_source_supports_tps3(struct intel_display *display);
115 bool intel_dp_source_supports_tps4(struct intel_display *display);
116
117 int intel_dp_link_required(int pixel_clock, int bpp);
118 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
119 int bw_overhead);
120 int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,
121 int max_dprx_rate, int max_dprx_lanes);
122 bool intel_dp_joiner_needs_dsc(struct intel_display *display,
123 int num_joined_pipes);
124 bool intel_dp_has_joiner(struct intel_dp *intel_dp);
125 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
126 const struct drm_connector_state *conn_state);
127 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
128 const struct intel_crtc_state *crtc_state,
129 const struct drm_connector_state *conn_state);
130 void intel_read_dp_sdp(struct intel_encoder *encoder,
131 struct intel_crtc_state *crtc_state,
132 unsigned int type);
133 void intel_digital_port_lock(struct intel_encoder *encoder);
134 void intel_digital_port_unlock(struct intel_encoder *encoder);
135 bool intel_digital_port_connected(struct intel_encoder *encoder);
136 bool intel_digital_port_connected_locked(struct intel_encoder *encoder);
137 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
138 u8 dsc_max_bpc);
139 u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display,
140 u32 link_clock, u32 lane_count,
141 u32 mode_clock, u32 mode_hdisplay,
142 int num_joined_pipes,
143 enum intel_output_format output_format,
144 u32 pipe_bpp,
145 u32 timeslots);
146 int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_config);
147 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
148 const struct intel_crtc_state *pipe_config,
149 int bpc);
150 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
151 int mode_clock, int mode_hdisplay,
152 int num_joined_pipes);
153 int intel_dp_num_joined_pipes(struct intel_dp *intel_dp,
154 struct intel_connector *connector,
155 int hdisplay, int clock);
156
intel_dp_unused_lane_mask(int lane_count)157 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
158 {
159 return ~((1 << lane_count) - 1) & 0xf;
160 }
161
162 bool intel_dp_supports_fec(struct intel_dp *intel_dp,
163 const struct intel_connector *connector,
164 const struct intel_crtc_state *pipe_config);
165 u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
166 int intel_dp_bw_fec_overhead(bool fec_enabled);
167
168 bool intel_dp_supports_fec(struct intel_dp *intel_dp,
169 const struct intel_connector *connector,
170 const struct intel_crtc_state *pipe_config);
171
172 bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
173 const struct intel_connector *connector,
174 const struct intel_crtc_state *crtc_state);
175
176 u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp);
177
178 void intel_ddi_update_pipe(struct intel_atomic_state *state,
179 struct intel_encoder *encoder,
180 const struct intel_crtc_state *crtc_state,
181 const struct drm_connector_state *conn_state);
182
183 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
184 struct intel_crtc_state *crtc_state);
185 void intel_dp_sync_state(struct intel_encoder *encoder,
186 const struct intel_crtc_state *crtc_state);
187
188 void intel_dp_check_frl_training(struct intel_dp *intel_dp);
189 void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
190 const struct intel_crtc_state *crtc_state);
191
192 void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp);
193 void intel_dp_wait_source_oui(struct intel_dp *intel_dp);
194 int intel_dp_output_bpp(enum intel_output_format output_format, int bpp);
195
196 bool intel_dp_compute_config_limits(struct intel_dp *intel_dp,
197 struct intel_crtc_state *crtc_state,
198 bool respect_downstream_limits,
199 bool dsc,
200 struct link_config_limits *limits);
201
202 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector);
203 bool intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder);
204
205 bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
206 u8 lane_count);
207 bool intel_dp_has_connector(struct intel_dp *intel_dp,
208 const struct drm_connector_state *conn_state);
209 int intel_dp_dsc_max_src_input_bpc(struct intel_display *display);
210 int intel_dp_dsc_min_src_input_bpc(void);
211
212 #endif /* __INTEL_DP_H__ */
213