1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25
26 #ifndef __INTEL_DISPLAY_TYPES_H__
27 #define __INTEL_DISPLAY_TYPES_H__
28
29 #include <linux/i2c.h>
30 #include <linux/pm_qos.h>
31 #include <linux/pwm.h>
32 #include <linux/sched/clock.h>
33
34 #include <drm/display/drm_dp_dual_mode_helper.h>
35 #include <drm/display/drm_dp_mst_helper.h>
36 #include <drm/display/drm_dsc.h>
37 #include <drm/drm_atomic.h>
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_encoder.h>
40 #include <drm/drm_fourcc.h>
41 #include <drm/drm_framebuffer.h>
42 #include <drm/drm_probe_helper.h>
43 #include <drm/drm_rect.h>
44 #include <drm/drm_vblank.h>
45 #include <drm/drm_vblank_work.h>
46 #include <drm/i915_hdcp_interface.h>
47 #include <media/cec-notifier.h>
48
49 #include "i915_vma.h"
50 #include "i915_vma_types.h"
51 #include "intel_bios.h"
52 #include "intel_display.h"
53 #include "intel_display_limits.h"
54 #include "intel_display_power.h"
55 #include "intel_dpll_mgr.h"
56 #include "intel_wm_types.h"
57
58 struct drm_printer;
59 struct __intel_global_objs_state;
60 struct intel_ddi_buf_trans;
61 struct intel_fbc;
62 struct intel_connector;
63 struct intel_tc_port;
64
65 /*
66 * Display related stuff
67 */
68
69 /* these are outputs from the chip - integrated only
70 external chips are via DVO or SDVO output */
71 enum intel_output_type {
72 INTEL_OUTPUT_UNUSED = 0,
73 INTEL_OUTPUT_ANALOG = 1,
74 INTEL_OUTPUT_DVO = 2,
75 INTEL_OUTPUT_SDVO = 3,
76 INTEL_OUTPUT_LVDS = 4,
77 INTEL_OUTPUT_TVOUT = 5,
78 INTEL_OUTPUT_HDMI = 6,
79 INTEL_OUTPUT_DP = 7,
80 INTEL_OUTPUT_EDP = 8,
81 INTEL_OUTPUT_DSI = 9,
82 INTEL_OUTPUT_DDI = 10,
83 INTEL_OUTPUT_DP_MST = 11,
84 };
85
86 enum hdmi_force_audio {
87 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
88 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
89 HDMI_AUDIO_AUTO, /* trust EDID */
90 HDMI_AUDIO_ON, /* force turn on HDMI audio */
91 };
92
93 /* "Broadcast RGB" property */
94 enum intel_broadcast_rgb {
95 INTEL_BROADCAST_RGB_AUTO,
96 INTEL_BROADCAST_RGB_FULL,
97 INTEL_BROADCAST_RGB_LIMITED,
98 };
99
100 struct intel_fb_view {
101 /*
102 * The remap information used in the remapped and rotated views to
103 * create the DMA scatter-gather list for each FB color plane. This sg
104 * list is created along with the view type (gtt.type) specific
105 * i915_vma object and contains the list of FB object pages (reordered
106 * in the rotated view) that are visible in the view.
107 * In the normal view the FB object's backing store sg list is used
108 * directly and hence the remap information here is not used.
109 */
110 struct i915_gtt_view gtt;
111
112 /*
113 * The GTT view (gtt.type) specific information for each FB color
114 * plane. In the normal GTT view all formats (up to 4 color planes),
115 * in the rotated and remapped GTT view all no-CCS formats (up to 2
116 * color planes) are supported.
117 *
118 * The view information shared by all FB color planes in the FB,
119 * like dst x/y and src/dst width, is stored separately in
120 * intel_plane_state.
121 */
122 struct i915_color_plane_view {
123 u32 offset;
124 unsigned int x, y;
125 /*
126 * Plane stride in:
127 * bytes for 0/180 degree rotation
128 * pixels for 90/270 degree rotation
129 */
130 unsigned int mapping_stride;
131 unsigned int scanout_stride;
132 } color_plane[4];
133 };
134
135 struct intel_framebuffer {
136 struct drm_framebuffer base;
137 struct intel_frontbuffer *frontbuffer;
138
139 /* Params to remap the FB pages and program the plane registers in each view. */
140 struct intel_fb_view normal_view;
141 union {
142 struct intel_fb_view rotated_view;
143 struct intel_fb_view remapped_view;
144 };
145
146 struct i915_address_space *dpt_vm;
147 };
148
149 enum intel_hotplug_state {
150 INTEL_HOTPLUG_UNCHANGED,
151 INTEL_HOTPLUG_CHANGED,
152 INTEL_HOTPLUG_RETRY,
153 };
154
155 struct intel_encoder {
156 struct drm_encoder base;
157
158 enum intel_output_type type;
159 enum port port;
160 u16 cloneable;
161 u8 pipe_mask;
162 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
163 struct intel_connector *connector);
164 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
165 struct intel_crtc_state *,
166 struct drm_connector_state *);
167 int (*compute_config)(struct intel_encoder *,
168 struct intel_crtc_state *,
169 struct drm_connector_state *);
170 int (*compute_config_late)(struct intel_encoder *,
171 struct intel_crtc_state *,
172 struct drm_connector_state *);
173 void (*pre_pll_enable)(struct intel_atomic_state *,
174 struct intel_encoder *,
175 const struct intel_crtc_state *,
176 const struct drm_connector_state *);
177 void (*pre_enable)(struct intel_atomic_state *,
178 struct intel_encoder *,
179 const struct intel_crtc_state *,
180 const struct drm_connector_state *);
181 void (*enable)(struct intel_atomic_state *,
182 struct intel_encoder *,
183 const struct intel_crtc_state *,
184 const struct drm_connector_state *);
185 void (*disable)(struct intel_atomic_state *,
186 struct intel_encoder *,
187 const struct intel_crtc_state *,
188 const struct drm_connector_state *);
189 void (*post_disable)(struct intel_atomic_state *,
190 struct intel_encoder *,
191 const struct intel_crtc_state *,
192 const struct drm_connector_state *);
193 void (*post_pll_disable)(struct intel_atomic_state *,
194 struct intel_encoder *,
195 const struct intel_crtc_state *,
196 const struct drm_connector_state *);
197 void (*update_pipe)(struct intel_atomic_state *,
198 struct intel_encoder *,
199 const struct intel_crtc_state *,
200 const struct drm_connector_state *);
201 void (*audio_enable)(struct intel_encoder *encoder,
202 const struct intel_crtc_state *crtc_state,
203 const struct drm_connector_state *conn_state);
204 void (*audio_disable)(struct intel_encoder *encoder,
205 const struct intel_crtc_state *old_crtc_state,
206 const struct drm_connector_state *old_conn_state);
207 /* Read out the current hw state of this connector, returning true if
208 * the encoder is active. If the encoder is enabled it also set the pipe
209 * it is connected to in the pipe parameter. */
210 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
211 /* Reconstructs the equivalent mode flags for the current hardware
212 * state. This must be called _after_ display->get_pipe_config has
213 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
214 * be set correctly before calling this function. */
215 void (*get_config)(struct intel_encoder *,
216 struct intel_crtc_state *pipe_config);
217
218 /*
219 * Optional hook called during init/resume to sync any state
220 * stored in the encoder (eg. DP link parameters) wrt. the HW state.
221 */
222 void (*sync_state)(struct intel_encoder *encoder,
223 const struct intel_crtc_state *crtc_state);
224
225 /*
226 * Optional hook, returning true if this encoder allows a fastset
227 * during the initial commit, false otherwise.
228 */
229 bool (*initial_fastset_check)(struct intel_encoder *encoder,
230 struct intel_crtc_state *crtc_state);
231
232 /*
233 * Acquires the power domains needed for an active encoder during
234 * hardware state readout.
235 */
236 void (*get_power_domains)(struct intel_encoder *encoder,
237 struct intel_crtc_state *crtc_state);
238 /*
239 * Called during system suspend after all pending requests for the
240 * encoder are flushed (for example for DP AUX transactions) and
241 * device interrupts are disabled.
242 * All modeset locks are held while the hook is called.
243 */
244 void (*suspend)(struct intel_encoder *);
245 /*
246 * Called without the modeset locks held after the suspend() hook for
247 * all encoders have been called.
248 */
249 void (*suspend_complete)(struct intel_encoder *encoder);
250 /*
251 * Called during system reboot/shutdown after all the
252 * encoders have been disabled and suspended.
253 * All modeset locks are held while the hook is called.
254 */
255 void (*shutdown)(struct intel_encoder *encoder);
256 /*
257 * Called without the modeset locks held after the shutdown() hook for
258 * all encoders have been called.
259 */
260 void (*shutdown_complete)(struct intel_encoder *encoder);
261 /*
262 * Enable/disable the clock to the port.
263 */
264 void (*enable_clock)(struct intel_encoder *encoder,
265 const struct intel_crtc_state *crtc_state);
266 void (*disable_clock)(struct intel_encoder *encoder);
267 /*
268 * Returns whether the port clock is enabled or not.
269 */
270 bool (*is_clock_enabled)(struct intel_encoder *encoder);
271 /*
272 * Returns the PLL type the port uses.
273 */
274 enum icl_port_dpll_id (*port_pll_type)(struct intel_encoder *encoder,
275 const struct intel_crtc_state *crtc_state);
276 const struct intel_ddi_buf_trans *(*get_buf_trans)(struct intel_encoder *encoder,
277 const struct intel_crtc_state *crtc_state,
278 int *n_entries);
279 void (*set_signal_levels)(struct intel_encoder *encoder,
280 const struct intel_crtc_state *crtc_state);
281
282 enum hpd_pin hpd_pin;
283 enum intel_display_power_domain power_domain;
284
285 /* VBT information for this encoder (may be NULL for older platforms) */
286 const struct intel_bios_encoder_data *devdata;
287 };
288
289 struct intel_panel_bl_funcs {
290 /* Connector and platform specific backlight functions */
291 int (*setup)(struct intel_connector *connector, enum pipe pipe);
292 u32 (*get)(struct intel_connector *connector, enum pipe pipe);
293 void (*set)(const struct drm_connector_state *conn_state, u32 level);
294 void (*disable)(const struct drm_connector_state *conn_state, u32 level);
295 void (*enable)(const struct intel_crtc_state *crtc_state,
296 const struct drm_connector_state *conn_state, u32 level);
297 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
298 };
299
300 enum drrs_type {
301 DRRS_TYPE_NONE,
302 DRRS_TYPE_STATIC,
303 DRRS_TYPE_SEAMLESS,
304 };
305
306 struct intel_vbt_panel_data {
307 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
308 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
309
310 /* Feature bits */
311 int panel_type;
312 unsigned int lvds_dither:1;
313 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
314
315 bool vrr;
316
317 u8 seamless_drrs_min_refresh_rate;
318 enum drrs_type drrs_type;
319
320 struct {
321 int max_link_rate;
322 int rate;
323 int lanes;
324 int preemphasis;
325 int vswing;
326 int bpp;
327 struct edp_power_seq pps;
328 u8 drrs_msa_timing_delay;
329 bool low_vswing;
330 bool initialized;
331 bool hobl;
332 } edp;
333
334 struct {
335 bool enable;
336 bool full_link;
337 bool require_aux_wakeup;
338 int idle_frames;
339 int tp1_wakeup_time_us;
340 int tp2_tp3_wakeup_time_us;
341 int psr2_tp2_tp3_wakeup_time_us;
342 } psr;
343
344 struct {
345 u16 pwm_freq_hz;
346 u16 brightness_precision_bits;
347 u16 hdr_dpcd_refresh_timeout;
348 bool present;
349 bool active_low_pwm;
350 u8 min_brightness; /* min_brightness/255 of max */
351 s8 controller; /* brightness controller number */
352 enum intel_backlight_type type;
353 } backlight;
354
355 /* MIPI DSI */
356 struct {
357 u16 panel_id;
358 struct mipi_config *config;
359 struct mipi_pps_data *pps;
360 u16 bl_ports;
361 u16 cabc_ports;
362 u8 seq_version;
363 u32 size;
364 u8 *data;
365 const u8 *sequence[MIPI_SEQ_MAX];
366 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
367 enum drm_panel_orientation orientation;
368 } dsi;
369 };
370
371 struct intel_panel {
372 /* Fixed EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
373 const struct drm_edid *fixed_edid;
374
375 struct list_head fixed_modes;
376
377 /* backlight */
378 struct {
379 bool present;
380 u32 level;
381 u32 min;
382 u32 max;
383 bool enabled;
384 bool combination_mode; /* gen 2/4 only */
385 bool active_low_pwm;
386 bool alternate_pwm_increment; /* lpt+ */
387
388 /* PWM chip */
389 u32 pwm_level_min;
390 u32 pwm_level_max;
391 bool pwm_enabled;
392 bool util_pin_active_low; /* bxt+ */
393 u8 controller; /* bxt+ only */
394 struct pwm_device *pwm;
395 struct pwm_state pwm_state;
396
397 /* DPCD backlight */
398 union {
399 struct {
400 struct drm_edp_backlight_info info;
401 } vesa;
402 struct {
403 bool sdr_uses_aux;
404 } intel;
405 } edp;
406
407 struct backlight_device *device;
408
409 const struct intel_panel_bl_funcs *funcs;
410 const struct intel_panel_bl_funcs *pwm_funcs;
411 void (*power)(struct intel_connector *, bool enable);
412 } backlight;
413
414 struct intel_vbt_panel_data vbt;
415 };
416
417 struct intel_digital_port;
418
419 enum check_link_response {
420 HDCP_LINK_PROTECTED = 0,
421 HDCP_TOPOLOGY_CHANGE,
422 HDCP_LINK_INTEGRITY_FAILURE,
423 HDCP_REAUTH_REQUEST
424 };
425
426 /*
427 * This structure serves as a translation layer between the generic HDCP code
428 * and the bus-specific code. What that means is that HDCP over HDMI differs
429 * from HDCP over DP, so to account for these differences, we need to
430 * communicate with the receiver through this shim.
431 *
432 * For completeness, the 2 buses differ in the following ways:
433 * - DP AUX vs. DDC
434 * HDCP registers on the receiver are set via DP AUX for DP, and
435 * they are set via DDC for HDMI.
436 * - Receiver register offsets
437 * The offsets of the registers are different for DP vs. HDMI
438 * - Receiver register masks/offsets
439 * For instance, the ready bit for the KSV fifo is in a different
440 * place on DP vs HDMI
441 * - Receiver register names
442 * Seriously. In the DP spec, the 16-bit register containing
443 * downstream information is called BINFO, on HDMI it's called
444 * BSTATUS. To confuse matters further, DP has a BSTATUS register
445 * with a completely different definition.
446 * - KSV FIFO
447 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
448 * be read 3 keys at a time
449 * - Aksv output
450 * Since Aksv is hidden in hardware, there's different procedures
451 * to send it over DP AUX vs DDC
452 */
453 struct intel_hdcp_shim {
454 /* Outputs the transmitter's An and Aksv values to the receiver. */
455 int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an);
456
457 /* Reads the receiver's key selection vector */
458 int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv);
459
460 /*
461 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
462 * definitions are the same in the respective specs, but the names are
463 * different. Call it BSTATUS since that's the name the HDMI spec
464 * uses and it was there first.
465 */
466 int (*read_bstatus)(struct intel_digital_port *dig_port,
467 u8 *bstatus);
468
469 /* Determines whether a repeater is present downstream */
470 int (*repeater_present)(struct intel_digital_port *dig_port,
471 bool *repeater_present);
472
473 /* Reads the receiver's Ri' value */
474 int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri);
475
476 /* Determines if the receiver's KSV FIFO is ready for consumption */
477 int (*read_ksv_ready)(struct intel_digital_port *dig_port,
478 bool *ksv_ready);
479
480 /* Reads the ksv fifo for num_downstream devices */
481 int (*read_ksv_fifo)(struct intel_digital_port *dig_port,
482 int num_downstream, u8 *ksv_fifo);
483
484 /* Reads a 32-bit part of V' from the receiver */
485 int (*read_v_prime_part)(struct intel_digital_port *dig_port,
486 int i, u32 *part);
487
488 /* Enables HDCP signalling on the port */
489 int (*toggle_signalling)(struct intel_digital_port *dig_port,
490 enum transcoder cpu_transcoder,
491 bool enable);
492
493 /* Enable/Disable stream encryption on DP MST Transport Link */
494 int (*stream_encryption)(struct intel_connector *connector,
495 bool enable);
496
497 /* Ensures the link is still protected */
498 bool (*check_link)(struct intel_digital_port *dig_port,
499 struct intel_connector *connector);
500
501 /* Detects panel's hdcp capability. This is optional for HDMI. */
502 int (*hdcp_capable)(struct intel_digital_port *dig_port,
503 bool *hdcp_capable);
504
505 /* HDCP adaptation(DP/HDMI) required on the port */
506 enum hdcp_wired_protocol protocol;
507
508 /* Detects whether sink is HDCP2.2 capable */
509 int (*hdcp_2_2_capable)(struct intel_connector *connector,
510 bool *capable);
511
512 /* Write HDCP2.2 messages */
513 int (*write_2_2_msg)(struct intel_connector *connector,
514 void *buf, size_t size);
515
516 /* Read HDCP2.2 messages */
517 int (*read_2_2_msg)(struct intel_connector *connector,
518 u8 msg_id, void *buf, size_t size);
519
520 /*
521 * Implementation of DP HDCP2.2 Errata for the communication of stream
522 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
523 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
524 */
525 int (*config_stream_type)(struct intel_connector *connector,
526 bool is_repeater, u8 type);
527
528 /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
529 int (*stream_2_2_encryption)(struct intel_connector *connector,
530 bool enable);
531
532 /* HDCP2.2 Link Integrity Check */
533 int (*check_2_2_link)(struct intel_digital_port *dig_port,
534 struct intel_connector *connector);
535 };
536
537 struct intel_hdcp {
538 const struct intel_hdcp_shim *shim;
539 /* Mutex for hdcp state of the connector */
540 struct mutex mutex;
541 u64 value;
542 struct delayed_work check_work;
543 struct work_struct prop_work;
544
545 /* HDCP1.4 Encryption status */
546 bool hdcp_encrypted;
547
548 /* HDCP2.2 related definitions */
549 /* Flag indicates whether this connector supports HDCP2.2 or not. */
550 bool hdcp2_supported;
551
552 /* HDCP2.2 Encryption status */
553 bool hdcp2_encrypted;
554
555 /*
556 * Content Stream Type defined by content owner. TYPE0(0x0) content can
557 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
558 * content can flow only through a link protected by HDCP2.2.
559 */
560 u8 content_type;
561
562 bool is_paired;
563 bool is_repeater;
564
565 /*
566 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
567 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
568 * When it rolls over re-auth has to be triggered.
569 */
570 u32 seq_num_v;
571
572 /*
573 * Count of RepeaterAuth_Stream_Manage msg propagated.
574 * Initialized to 0 on AKE_INIT. Incremented after every successful
575 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
576 * over re-Auth has to be triggered.
577 */
578 u32 seq_num_m;
579
580 /*
581 * Work queue to signal the CP_IRQ. Used for the waiters to read the
582 * available information from HDCP DP sink.
583 */
584 wait_queue_head_t cp_irq_queue;
585 atomic_t cp_irq_count;
586 int cp_irq_count_cached;
587
588 /*
589 * HDCP register access for gen12+ need the transcoder associated.
590 * Transcoder attached to the connector could be changed at modeset.
591 * Hence caching the transcoder here.
592 */
593 enum transcoder cpu_transcoder;
594 /* Only used for DP MST stream encryption */
595 enum transcoder stream_transcoder;
596 };
597
598 struct intel_connector {
599 struct drm_connector base;
600 /*
601 * The fixed encoder this connector is connected to.
602 */
603 struct intel_encoder *encoder;
604
605 /* ACPI device id for ACPI and driver cooperation */
606 u32 acpi_device_id;
607
608 /* Reads out the current hw, returning true if the connector is enabled
609 * and active (i.e. dpms ON state). */
610 bool (*get_hw_state)(struct intel_connector *);
611
612 /*
613 * Optional hook called during init/resume to sync any state
614 * stored in the connector (eg. DSC state) wrt. the HW state.
615 */
616 void (*sync_state)(struct intel_connector *connector,
617 const struct intel_crtc_state *crtc_state);
618
619 /* Panel info for eDP and LVDS */
620 struct intel_panel panel;
621
622 /* Cached EDID for detect. */
623 const struct drm_edid *detect_edid;
624
625 /* Number of times hotplug detection was tried after an HPD interrupt */
626 int hotplug_retries;
627
628 /* since POLL and HPD connectors may use the same HPD line keep the native
629 state of connector->polled in case hotplug storm detection changes it */
630 u8 polled;
631
632 struct drm_dp_mst_port *port;
633
634 struct intel_dp *mst_port;
635
636 struct {
637 struct drm_dp_aux *dsc_decompression_aux;
638 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
639 u8 fec_capability;
640
641 u8 dsc_hblank_expansion_quirk:1;
642 u8 dsc_decompression_enabled:1;
643 } dp;
644
645 /* Work struct to schedule a uevent on link train failure */
646 struct work_struct modeset_retry_work;
647
648 struct intel_hdcp hdcp;
649 };
650
651 struct intel_digital_connector_state {
652 struct drm_connector_state base;
653
654 enum hdmi_force_audio force_audio;
655 int broadcast_rgb;
656 };
657
658 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
659
660 struct dpll {
661 /* given values */
662 int n;
663 int m1, m2;
664 int p1, p2;
665 /* derived values */
666 int dot;
667 int vco;
668 int m;
669 int p;
670 };
671
672 struct intel_atomic_state {
673 struct drm_atomic_state base;
674
675 intel_wakeref_t wakeref;
676
677 struct __intel_global_objs_state *global_objs;
678 int num_global_objs;
679
680 /* Internal commit, as opposed to userspace/client initiated one */
681 bool internal;
682
683 bool dpll_set, modeset;
684
685 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
686
687 /*
688 * Current watermarks can't be trusted during hardware readout, so
689 * don't bother calculating intermediate watermarks.
690 */
691 bool skip_intermediate_wm;
692
693 bool rps_interactive;
694 };
695
696 struct intel_plane_state {
697 struct drm_plane_state uapi;
698
699 /*
700 * actual hardware state, the state we program to the hardware.
701 * The following members are used to verify the hardware state:
702 * During initial hw readout, they need to be copied from uapi.
703 */
704 struct {
705 struct drm_crtc *crtc;
706 struct drm_framebuffer *fb;
707
708 u16 alpha;
709 u16 pixel_blend_mode;
710 unsigned int rotation;
711 enum drm_color_encoding color_encoding;
712 enum drm_color_range color_range;
713 enum drm_scaling_filter scaling_filter;
714 } hw;
715
716 struct i915_vma *ggtt_vma;
717 struct i915_vma *dpt_vma;
718 unsigned long flags;
719 #define PLANE_HAS_FENCE BIT(0)
720
721 struct intel_fb_view view;
722
723 /* Plane pxp decryption state */
724 bool decrypt;
725
726 /* Plane state to display black pixels when pxp is borked */
727 bool force_black;
728
729 /* plane control register */
730 u32 ctl;
731
732 /* plane color control register */
733 u32 color_ctl;
734
735 /* chroma upsampler control register */
736 u32 cus_ctl;
737
738 /*
739 * scaler_id
740 * = -1 : not using a scaler
741 * >= 0 : using a scalers
742 *
743 * plane requiring a scaler:
744 * - During check_plane, its bit is set in
745 * crtc_state->scaler_state.scaler_users by calling helper function
746 * update_scaler_plane.
747 * - scaler_id indicates the scaler it got assigned.
748 *
749 * plane doesn't require a scaler:
750 * - this can happen when scaling is no more required or plane simply
751 * got disabled.
752 * - During check_plane, corresponding bit is reset in
753 * crtc_state->scaler_state.scaler_users by calling helper function
754 * update_scaler_plane.
755 */
756 int scaler_id;
757
758 /*
759 * planar_linked_plane:
760 *
761 * ICL planar formats require 2 planes that are updated as pairs.
762 * This member is used to make sure the other plane is also updated
763 * when required, and for update_slave() to find the correct
764 * plane_state to pass as argument.
765 */
766 struct intel_plane *planar_linked_plane;
767
768 /*
769 * planar_slave:
770 * If set don't update use the linked plane's state for updating
771 * this plane during atomic commit with the update_slave() callback.
772 *
773 * It's also used by the watermark code to ignore wm calculations on
774 * this plane. They're calculated by the linked plane's wm code.
775 */
776 u32 planar_slave;
777
778 struct drm_intel_sprite_colorkey ckey;
779
780 struct drm_rect psr2_sel_fetch_area;
781
782 /* Clear Color Value */
783 u64 ccval;
784
785 const char *no_fbc_reason;
786 };
787
788 struct intel_initial_plane_config {
789 struct intel_framebuffer *fb;
790 struct i915_vma *vma;
791 unsigned int tiling;
792 int size;
793 u32 base;
794 u8 rotation;
795 };
796
797 struct intel_scaler {
798 int in_use;
799 u32 mode;
800 };
801
802 struct intel_crtc_scaler_state {
803 #define SKL_NUM_SCALERS 2
804 struct intel_scaler scalers[SKL_NUM_SCALERS];
805
806 /*
807 * scaler_users: keeps track of users requesting scalers on this crtc.
808 *
809 * If a bit is set, a user is using a scaler.
810 * Here user can be a plane or crtc as defined below:
811 * bits 0-30 - plane (bit position is index from drm_plane_index)
812 * bit 31 - crtc
813 *
814 * Instead of creating a new index to cover planes and crtc, using
815 * existing drm_plane_index for planes which is well less than 31
816 * planes and bit 31 for crtc. This should be fine to cover all
817 * our platforms.
818 *
819 * intel_atomic_setup_scalers will setup available scalers to users
820 * requesting scalers. It will gracefully fail if request exceeds
821 * avilability.
822 */
823 #define SKL_CRTC_INDEX 31
824 unsigned scaler_users;
825
826 /* scaler used by crtc for panel fitting purpose */
827 int scaler_id;
828 };
829
830 /* {crtc,crtc_state}->mode_flags */
831 /* Flag to get scanline using frame time stamps */
832 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
833 /* Flag to use the scanline counter instead of the pixel counter */
834 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
835 /*
836 * TE0 or TE1 flag is set if the crtc has a DSI encoder which
837 * is operating in command mode.
838 * Flag to use TE from DSI0 instead of VBI in command mode
839 */
840 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
841 /* Flag to use TE from DSI1 instead of VBI in command mode */
842 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
843 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */
844 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
845 /* Do tricks to make vblank timestamps sane with VRR? */
846 #define I915_MODE_FLAG_VRR (1<<6)
847
848 struct intel_wm_level {
849 bool enable;
850 u32 pri_val;
851 u32 spr_val;
852 u32 cur_val;
853 u32 fbc_val;
854 };
855
856 struct intel_pipe_wm {
857 struct intel_wm_level wm[5];
858 bool fbc_wm_enabled;
859 bool pipe_enabled;
860 bool sprites_enabled;
861 bool sprites_scaled;
862 };
863
864 struct skl_wm_level {
865 u16 min_ddb_alloc;
866 u16 blocks;
867 u8 lines;
868 bool enable;
869 bool ignore_lines;
870 bool can_sagv;
871 };
872
873 struct skl_plane_wm {
874 struct skl_wm_level wm[8];
875 struct skl_wm_level uv_wm[8];
876 struct skl_wm_level trans_wm;
877 struct {
878 struct skl_wm_level wm0;
879 struct skl_wm_level trans_wm;
880 } sagv;
881 bool is_planar;
882 };
883
884 struct skl_pipe_wm {
885 struct skl_plane_wm planes[I915_MAX_PLANES];
886 bool use_sagv_wm;
887 };
888
889 enum vlv_wm_level {
890 VLV_WM_LEVEL_PM2,
891 VLV_WM_LEVEL_PM5,
892 VLV_WM_LEVEL_DDR_DVFS,
893 NUM_VLV_WM_LEVELS,
894 };
895
896 struct vlv_wm_state {
897 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
898 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
899 u8 num_levels;
900 bool cxsr;
901 };
902
903 struct vlv_fifo_state {
904 u16 plane[I915_MAX_PLANES];
905 };
906
907 enum g4x_wm_level {
908 G4X_WM_LEVEL_NORMAL,
909 G4X_WM_LEVEL_SR,
910 G4X_WM_LEVEL_HPLL,
911 NUM_G4X_WM_LEVELS,
912 };
913
914 struct g4x_wm_state {
915 struct g4x_pipe_wm wm;
916 struct g4x_sr_wm sr;
917 struct g4x_sr_wm hpll;
918 bool cxsr;
919 bool hpll_en;
920 bool fbc_en;
921 };
922
923 struct intel_crtc_wm_state {
924 union {
925 /*
926 * raw:
927 * The "raw" watermark values produced by the formula
928 * given the plane's current state. They do not consider
929 * how much FIFO is actually allocated for each plane.
930 *
931 * optimal:
932 * The "optimal" watermark values given the current
933 * state of the planes and the amount of FIFO
934 * allocated to each, ignoring any previous state
935 * of the planes.
936 *
937 * intermediate:
938 * The "intermediate" watermark values when transitioning
939 * between the old and new "optimal" values. Used when
940 * the watermark registers are single buffered and hence
941 * their state changes asynchronously with regards to the
942 * actual plane registers. These are essentially the
943 * worst case combination of the old and new "optimal"
944 * watermarks, which are therefore safe to use when the
945 * plane is in either its old or new state.
946 */
947 struct {
948 struct intel_pipe_wm intermediate;
949 struct intel_pipe_wm optimal;
950 } ilk;
951
952 struct {
953 struct skl_pipe_wm raw;
954 /* gen9+ only needs 1-step wm programming */
955 struct skl_pipe_wm optimal;
956 struct skl_ddb_entry ddb;
957 /*
958 * pre-icl: for packed/planar CbCr
959 * icl+: for everything
960 */
961 struct skl_ddb_entry plane_ddb[I915_MAX_PLANES];
962 /* pre-icl: for planar Y */
963 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
964 } skl;
965
966 struct {
967 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */
968 struct vlv_wm_state intermediate; /* inverted */
969 struct vlv_wm_state optimal; /* inverted */
970 struct vlv_fifo_state fifo_state;
971 } vlv;
972
973 struct {
974 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
975 struct g4x_wm_state intermediate;
976 struct g4x_wm_state optimal;
977 } g4x;
978 };
979
980 /*
981 * Platforms with two-step watermark programming will need to
982 * update watermark programming post-vblank to switch from the
983 * safe intermediate watermarks to the optimal final
984 * watermarks.
985 */
986 bool need_postvbl_update;
987 };
988
989 enum intel_output_format {
990 INTEL_OUTPUT_FORMAT_RGB,
991 INTEL_OUTPUT_FORMAT_YCBCR420,
992 INTEL_OUTPUT_FORMAT_YCBCR444,
993 };
994
995 struct intel_mpllb_state {
996 u32 clock; /* in KHz */
997 u32 ref_control;
998 u32 mpllb_cp;
999 u32 mpllb_div;
1000 u32 mpllb_div2;
1001 u32 mpllb_fracn1;
1002 u32 mpllb_fracn2;
1003 u32 mpllb_sscen;
1004 u32 mpllb_sscstep;
1005 };
1006
1007 /* Used by dp and fdi links */
1008 struct intel_link_m_n {
1009 u32 tu;
1010 u32 data_m;
1011 u32 data_n;
1012 u32 link_m;
1013 u32 link_n;
1014 };
1015
1016 struct intel_csc_matrix {
1017 u16 coeff[9];
1018 u16 preoff[3];
1019 u16 postoff[3];
1020 };
1021
1022 struct intel_c10pll_state {
1023 u32 clock; /* in KHz */
1024 u8 tx;
1025 u8 cmn;
1026 u8 pll[20];
1027 };
1028
1029 struct intel_c20pll_state {
1030 u32 clock; /* in kHz */
1031 u16 tx[3];
1032 u16 cmn[4];
1033 union {
1034 u16 mplla[10];
1035 u16 mpllb[11];
1036 };
1037 };
1038
1039 struct intel_cx0pll_state {
1040 union {
1041 struct intel_c10pll_state c10;
1042 struct intel_c20pll_state c20;
1043 };
1044 bool ssc_enabled;
1045 };
1046
1047 struct intel_crtc_state {
1048 /*
1049 * uapi (drm) state. This is the software state shown to userspace.
1050 * In particular, the following members are used for bookkeeping:
1051 * - crtc
1052 * - state
1053 * - *_changed
1054 * - event
1055 * - commit
1056 * - mode_blob
1057 */
1058 struct drm_crtc_state uapi;
1059
1060 /*
1061 * actual hardware state, the state we program to the hardware.
1062 * The following members are used to verify the hardware state:
1063 * - enable
1064 * - active
1065 * - mode / pipe_mode / adjusted_mode
1066 * - color property blobs.
1067 *
1068 * During initial hw readout, they need to be copied to uapi.
1069 *
1070 * Bigjoiner will allow a transcoder mode that spans 2 pipes;
1071 * Use the pipe_mode for calculations like watermarks, pipe
1072 * scaler, and bandwidth.
1073 *
1074 * Use adjusted_mode for things that need to know the full
1075 * mode on the transcoder, which spans all pipes.
1076 */
1077 struct {
1078 bool active, enable;
1079 /* logical state of LUTs */
1080 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
1081 struct drm_display_mode mode, pipe_mode, adjusted_mode;
1082 enum drm_scaling_filter scaling_filter;
1083 } hw;
1084
1085 /* actual state of LUTs */
1086 struct drm_property_blob *pre_csc_lut, *post_csc_lut;
1087
1088 struct intel_csc_matrix csc, output_csc;
1089
1090 /**
1091 * quirks - bitfield with hw state readout quirks
1092 *
1093 * For various reasons the hw state readout code might not be able to
1094 * completely faithfully read out the current state. These cases are
1095 * tracked with quirk flags so that fastboot and state checker can act
1096 * accordingly.
1097 */
1098 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
1099 unsigned long quirks;
1100
1101 unsigned fb_bits; /* framebuffers to flip */
1102 bool update_pipe; /* can a fast modeset be performed? */
1103 bool update_m_n; /* update M/N seamlessly during fastset? */
1104 bool update_lrr; /* update TRANS_VTOTAL/etc. during fastset? */
1105 bool disable_cxsr;
1106 bool update_wm_pre, update_wm_post; /* watermarks are updated */
1107 bool fifo_changed; /* FIFO split is changed */
1108 bool preload_luts;
1109 bool inherited; /* state inherited from BIOS? */
1110
1111 /* Ask the hardware to actually async flip? */
1112 bool do_async_flip;
1113
1114 /* Pipe source size (ie. panel fitter input size)
1115 * All planes will be positioned inside this space,
1116 * and get clipped at the edges. */
1117 struct drm_rect pipe_src;
1118
1119 /*
1120 * Pipe pixel rate, adjusted for
1121 * panel fitter/pipe scaler downscaling.
1122 */
1123 unsigned int pixel_rate;
1124
1125 /* Whether to set up the PCH/FDI. Note that we never allow sharing
1126 * between pch encoders and cpu encoders. */
1127 bool has_pch_encoder;
1128
1129 /* Are we sending infoframes on the attached port */
1130 bool has_infoframe;
1131
1132 /* CPU Transcoder for the pipe. Currently this can only differ from the
1133 * pipe on Haswell and later (where we have a special eDP transcoder)
1134 * and Broxton (where we have special DSI transcoders). */
1135 enum transcoder cpu_transcoder;
1136
1137 /*
1138 * Use reduced/limited/broadcast rbg range, compressing from the full
1139 * range fed into the crtcs.
1140 */
1141 bool limited_color_range;
1142
1143 /* Bitmask of encoder types (enum intel_output_type)
1144 * driven by the pipe.
1145 */
1146 unsigned int output_types;
1147
1148 /* Whether we should send NULL infoframes. Required for audio. */
1149 bool has_hdmi_sink;
1150
1151 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
1152 * has_dp_encoder is set. */
1153 bool has_audio;
1154
1155 /*
1156 * Enable dithering, used when the selected pipe bpp doesn't match the
1157 * plane bpp.
1158 */
1159 bool dither;
1160
1161 /*
1162 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
1163 * compliance video pattern tests.
1164 * Disable dither only if it is a compliance test request for
1165 * 18bpp.
1166 */
1167 bool dither_force_disable;
1168
1169 /* Controls for the clock computation, to override various stages. */
1170 bool clock_set;
1171
1172 /* SDVO TV has a bunch of special case. To make multifunction encoders
1173 * work correctly, we need to track this at runtime.*/
1174 bool sdvo_tv_clock;
1175
1176 /*
1177 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
1178 * required. This is set in the 2nd loop of calling encoder's
1179 * ->compute_config if the first pick doesn't work out.
1180 */
1181 bool bw_constrained;
1182
1183 /* Settings for the intel dpll used on pretty much everything but
1184 * haswell. */
1185 struct dpll dpll;
1186
1187 /* Selected dpll when shared or NULL. */
1188 struct intel_shared_dpll *shared_dpll;
1189
1190 /* Actual register state of the dpll, for shared dpll cross-checking. */
1191 union {
1192 struct intel_dpll_hw_state dpll_hw_state;
1193 struct intel_mpllb_state mpllb_state;
1194 struct intel_cx0pll_state cx0pll_state;
1195 };
1196
1197 /*
1198 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
1199 * setting shared_dpll and dpll_hw_state to one of these reserved ones.
1200 */
1201 struct icl_port_dpll {
1202 struct intel_shared_dpll *pll;
1203 struct intel_dpll_hw_state hw_state;
1204 } icl_port_dplls[ICL_PORT_DPLL_COUNT];
1205
1206 /* DSI PLL registers */
1207 struct {
1208 u32 ctrl, div;
1209 } dsi_pll;
1210
1211 int max_link_bpp_x16; /* in 1/16 bpp units */
1212 int pipe_bpp; /* in 1 bpp units */
1213 struct intel_link_m_n dp_m_n;
1214
1215 /* m2_n2 for eDP downclock */
1216 struct intel_link_m_n dp_m2_n2;
1217 bool has_drrs;
1218
1219 /* PSR is supported but might not be enabled due the lack of enabled planes */
1220 bool has_psr;
1221 bool has_psr2;
1222 bool enable_psr2_sel_fetch;
1223 bool req_psr2_sdp_prior_scanline;
1224 bool has_panel_replay;
1225 bool wm_level_disabled;
1226 u32 dc3co_exitline;
1227 u16 su_y_granularity;
1228 struct drm_dp_vsc_sdp psr_vsc;
1229
1230 /*
1231 * Frequence the dpll for the port should run at. Differs from the
1232 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
1233 * already multiplied by pixel_multiplier.
1234 */
1235 int port_clock;
1236
1237 /* Used by SDVO (and if we ever fix it, HDMI). */
1238 unsigned pixel_multiplier;
1239
1240 /* I915_MODE_FLAG_* */
1241 u8 mode_flags;
1242
1243 u8 lane_count;
1244
1245 /*
1246 * Used by platforms having DP/HDMI PHY with programmable lane
1247 * latency optimization.
1248 */
1249 u8 lane_lat_optim_mask;
1250
1251 /* minimum acceptable voltage level */
1252 u8 min_voltage_level;
1253
1254 /* Panel fitter controls for gen2-gen4 + VLV */
1255 struct {
1256 u32 control;
1257 u32 pgm_ratios;
1258 u32 lvds_border_bits;
1259 } gmch_pfit;
1260
1261 /* Panel fitter placement and size for Ironlake+ */
1262 struct {
1263 struct drm_rect dst;
1264 bool enabled;
1265 bool force_thru;
1266 } pch_pfit;
1267
1268 /* FDI configuration, only valid if has_pch_encoder is set. */
1269 int fdi_lanes;
1270 struct intel_link_m_n fdi_m_n;
1271
1272 bool ips_enabled;
1273
1274 bool crc_enabled;
1275
1276 bool double_wide;
1277
1278 int pbn;
1279
1280 struct intel_crtc_scaler_state scaler_state;
1281
1282 /* w/a for waiting 2 vblanks during crtc enable */
1283 enum pipe hsw_workaround_pipe;
1284
1285 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
1286 bool disable_lp_wm;
1287
1288 struct intel_crtc_wm_state wm;
1289
1290 int min_cdclk[I915_MAX_PLANES];
1291
1292 /* for packed/planar CbCr */
1293 u32 data_rate[I915_MAX_PLANES];
1294 /* for planar Y */
1295 u32 data_rate_y[I915_MAX_PLANES];
1296
1297 /* FIXME unify with data_rate[]? */
1298 u64 rel_data_rate[I915_MAX_PLANES];
1299 u64 rel_data_rate_y[I915_MAX_PLANES];
1300
1301 /* Gamma mode programmed on the pipe */
1302 u32 gamma_mode;
1303
1304 union {
1305 /* CSC mode programmed on the pipe */
1306 u32 csc_mode;
1307
1308 /* CHV CGM mode */
1309 u32 cgm_mode;
1310 };
1311
1312 /* bitmask of logically enabled planes (enum plane_id) */
1313 u8 enabled_planes;
1314
1315 /* bitmask of actually visible planes (enum plane_id) */
1316 u8 active_planes;
1317 u8 scaled_planes;
1318 u8 nv12_planes;
1319 u8 c8_planes;
1320
1321 /* bitmask of planes that will be updated during the commit */
1322 u8 update_planes;
1323
1324 /* bitmask of planes with async flip active */
1325 u8 async_flip_planes;
1326
1327 u8 framestart_delay; /* 1-4 */
1328 u8 msa_timing_delay; /* 0-3 */
1329
1330 struct {
1331 u32 enable;
1332 u32 gcp;
1333 union hdmi_infoframe avi;
1334 union hdmi_infoframe spd;
1335 union hdmi_infoframe hdmi;
1336 union hdmi_infoframe drm;
1337 struct drm_dp_vsc_sdp vsc;
1338 } infoframes;
1339
1340 u8 eld[MAX_ELD_BYTES];
1341
1342 /* HDMI scrambling status */
1343 bool hdmi_scrambling;
1344
1345 /* HDMI High TMDS char rate ratio */
1346 bool hdmi_high_tmds_clock_ratio;
1347
1348 /*
1349 * Output format RGB/YCBCR etc., that is coming out
1350 * at the end of the pipe.
1351 */
1352 enum intel_output_format output_format;
1353
1354 /*
1355 * Sink output format RGB/YCBCR etc., that is going
1356 * into the sink.
1357 */
1358 enum intel_output_format sink_format;
1359
1360 /* enable pipe gamma? */
1361 bool gamma_enable;
1362
1363 /* enable pipe csc? */
1364 bool csc_enable;
1365
1366 /* enable vlv/chv wgc csc? */
1367 bool wgc_enable;
1368
1369 /* big joiner pipe bitmask */
1370 u8 bigjoiner_pipes;
1371
1372 /* Display Stream compression state */
1373 struct {
1374 bool compression_enable;
1375 bool dsc_split;
1376 /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
1377 u16 compressed_bpp_x16;
1378 u8 slice_count;
1379 struct drm_dsc_config config;
1380 } dsc;
1381
1382 /* HSW+ linetime watermarks */
1383 u16 linetime;
1384 u16 ips_linetime;
1385
1386 bool enhanced_framing;
1387
1388 /*
1389 * Forward Error Correction.
1390 *
1391 * Note: This will be false for 128b/132b, which will always have FEC
1392 * enabled automatically.
1393 */
1394 bool fec_enable;
1395
1396 bool sdp_split_enable;
1397
1398 /* Pointer to master transcoder in case of tiled displays */
1399 enum transcoder master_transcoder;
1400
1401 /* Bitmask to indicate slaves attached */
1402 u8 sync_mode_slaves_mask;
1403
1404 /* Only valid on TGL+ */
1405 enum transcoder mst_master_transcoder;
1406
1407 /* For DSB related info */
1408 struct intel_dsb *dsb;
1409
1410 u32 psr2_man_track_ctl;
1411
1412 /* Variable Refresh Rate state */
1413 struct {
1414 bool enable, in_range;
1415 u8 pipeline_full;
1416 u16 flipline, vmin, vmax, guardband;
1417 } vrr;
1418
1419 /* Stream Splitter for eDP MSO */
1420 struct {
1421 bool enable;
1422 u8 link_count;
1423 u8 pixel_overlap;
1424 } splitter;
1425
1426 /* for loading single buffered registers during vblank */
1427 struct drm_vblank_work vblank_work;
1428 };
1429
1430 enum intel_pipe_crc_source {
1431 INTEL_PIPE_CRC_SOURCE_NONE,
1432 INTEL_PIPE_CRC_SOURCE_PLANE1,
1433 INTEL_PIPE_CRC_SOURCE_PLANE2,
1434 INTEL_PIPE_CRC_SOURCE_PLANE3,
1435 INTEL_PIPE_CRC_SOURCE_PLANE4,
1436 INTEL_PIPE_CRC_SOURCE_PLANE5,
1437 INTEL_PIPE_CRC_SOURCE_PLANE6,
1438 INTEL_PIPE_CRC_SOURCE_PLANE7,
1439 INTEL_PIPE_CRC_SOURCE_PIPE,
1440 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1441 INTEL_PIPE_CRC_SOURCE_TV,
1442 INTEL_PIPE_CRC_SOURCE_DP_B,
1443 INTEL_PIPE_CRC_SOURCE_DP_C,
1444 INTEL_PIPE_CRC_SOURCE_DP_D,
1445 INTEL_PIPE_CRC_SOURCE_AUTO,
1446 INTEL_PIPE_CRC_SOURCE_MAX,
1447 };
1448
1449 enum drrs_refresh_rate {
1450 DRRS_REFRESH_RATE_HIGH,
1451 DRRS_REFRESH_RATE_LOW,
1452 };
1453
1454 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1455 struct intel_pipe_crc {
1456 spinlock_t lock;
1457 int skipped;
1458 enum intel_pipe_crc_source source;
1459 };
1460
1461 struct intel_crtc {
1462 struct drm_crtc base;
1463 enum pipe pipe;
1464 /*
1465 * Whether the crtc and the connected output pipeline is active. Implies
1466 * that crtc->enabled is set, i.e. the current mode configuration has
1467 * some outputs connected to this crtc.
1468 */
1469 bool active;
1470 u8 plane_ids_mask;
1471
1472 /* I915_MODE_FLAG_* */
1473 u8 mode_flags;
1474
1475 u16 vmax_vblank_start;
1476
1477 struct intel_display_power_domain_set enabled_power_domains;
1478 struct intel_display_power_domain_set hw_readout_power_domains;
1479 struct intel_overlay *overlay;
1480
1481 struct intel_crtc_state *config;
1482
1483 /* armed event for async flip */
1484 struct drm_pending_vblank_event *flip_done_event;
1485
1486 /* Access to these should be protected by dev_priv->irq_lock. */
1487 bool cpu_fifo_underrun_disabled;
1488 bool pch_fifo_underrun_disabled;
1489
1490 /* per-pipe watermark state */
1491 struct {
1492 /* watermarks currently being used */
1493 union {
1494 struct intel_pipe_wm ilk;
1495 struct vlv_wm_state vlv;
1496 struct g4x_wm_state g4x;
1497 } active;
1498 } wm;
1499
1500 struct {
1501 struct mutex mutex;
1502 struct delayed_work work;
1503 enum drrs_refresh_rate refresh_rate;
1504 unsigned int frontbuffer_bits;
1505 unsigned int busy_frontbuffer_bits;
1506 enum transcoder cpu_transcoder;
1507 struct intel_link_m_n m_n, m2_n2;
1508 } drrs;
1509
1510 int scanline_offset;
1511
1512 struct {
1513 unsigned start_vbl_count;
1514 ktime_t start_vbl_time;
1515 int min_vbl, max_vbl;
1516 int scanline_start;
1517 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
1518 struct {
1519 u64 min;
1520 u64 max;
1521 u64 sum;
1522 unsigned int over;
1523 unsigned int times[17]; /* [1us, 16ms] */
1524 } vbl;
1525 #endif
1526 } debug;
1527
1528 /* scalers available on this crtc */
1529 int num_scalers;
1530
1531 /* for loading single buffered registers during vblank */
1532 struct pm_qos_request vblank_pm_qos;
1533
1534 #ifdef CONFIG_DEBUG_FS
1535 struct intel_pipe_crc pipe_crc;
1536 #endif
1537 };
1538
1539 struct intel_plane {
1540 struct drm_plane base;
1541 enum i9xx_plane_id i9xx_plane;
1542 enum plane_id id;
1543 enum pipe pipe;
1544 bool need_async_flip_disable_wa;
1545 u32 frontbuffer_bit;
1546
1547 struct {
1548 u32 base, cntl, size;
1549 } cursor;
1550
1551 struct intel_fbc *fbc;
1552
1553 /*
1554 * NOTE: Do not place new plane state fields here (e.g., when adding
1555 * new plane properties). New runtime state should now be placed in
1556 * the intel_plane_state structure and accessed via plane_state.
1557 */
1558
1559 int (*min_width)(const struct drm_framebuffer *fb,
1560 int color_plane,
1561 unsigned int rotation);
1562 int (*max_width)(const struct drm_framebuffer *fb,
1563 int color_plane,
1564 unsigned int rotation);
1565 int (*max_height)(const struct drm_framebuffer *fb,
1566 int color_plane,
1567 unsigned int rotation);
1568 unsigned int (*max_stride)(struct intel_plane *plane,
1569 u32 pixel_format, u64 modifier,
1570 unsigned int rotation);
1571 /* Write all non-self arming plane registers */
1572 void (*update_noarm)(struct intel_plane *plane,
1573 const struct intel_crtc_state *crtc_state,
1574 const struct intel_plane_state *plane_state);
1575 /* Write all self-arming plane registers */
1576 void (*update_arm)(struct intel_plane *plane,
1577 const struct intel_crtc_state *crtc_state,
1578 const struct intel_plane_state *plane_state);
1579 /* Disable the plane, must arm */
1580 void (*disable_arm)(struct intel_plane *plane,
1581 const struct intel_crtc_state *crtc_state);
1582 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1583 int (*check_plane)(struct intel_crtc_state *crtc_state,
1584 struct intel_plane_state *plane_state);
1585 int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1586 const struct intel_plane_state *plane_state);
1587 void (*async_flip)(struct intel_plane *plane,
1588 const struct intel_crtc_state *crtc_state,
1589 const struct intel_plane_state *plane_state,
1590 bool async_flip);
1591 void (*enable_flip_done)(struct intel_plane *plane);
1592 void (*disable_flip_done)(struct intel_plane *plane);
1593 };
1594
1595 struct intel_watermark_params {
1596 u16 fifo_size;
1597 u16 max_wm;
1598 u8 default_wm;
1599 u8 guard_size;
1600 u8 cacheline_size;
1601 };
1602
1603 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1604 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1605 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
1606 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1607 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1608 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1609 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1610 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
1611 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1612
1613 struct intel_hdmi {
1614 i915_reg_t hdmi_reg;
1615 struct {
1616 enum drm_dp_dual_mode_type type;
1617 int max_tmds_clock;
1618 } dp_dual_mode;
1619 struct intel_connector *attached_connector;
1620 struct cec_notifier *cec_notifier;
1621 };
1622
1623 struct intel_dp_mst_encoder;
1624
1625 struct intel_dp_compliance_data {
1626 unsigned long edid;
1627 u8 video_pattern;
1628 u16 hdisplay, vdisplay;
1629 u8 bpc;
1630 struct drm_dp_phy_test_params phytest;
1631 };
1632
1633 struct intel_dp_compliance {
1634 unsigned long test_type;
1635 struct intel_dp_compliance_data test_data;
1636 bool test_active;
1637 int test_link_rate;
1638 u8 test_lane_count;
1639 };
1640
1641 struct intel_dp_pcon_frl {
1642 bool is_trained;
1643 int trained_rate_gbps;
1644 };
1645
1646 struct intel_pps {
1647 int panel_power_up_delay;
1648 int panel_power_down_delay;
1649 int panel_power_cycle_delay;
1650 int backlight_on_delay;
1651 int backlight_off_delay;
1652 struct delayed_work panel_vdd_work;
1653 bool want_panel_vdd;
1654 bool initializing;
1655 unsigned long last_power_on;
1656 unsigned long last_backlight_off;
1657 ktime_t panel_power_off_time;
1658 intel_wakeref_t vdd_wakeref;
1659
1660 union {
1661 /*
1662 * Pipe whose power sequencer is currently locked into
1663 * this port. Only relevant on VLV/CHV.
1664 */
1665 enum pipe pps_pipe;
1666
1667 /*
1668 * Power sequencer index. Only relevant on BXT+.
1669 */
1670 int pps_idx;
1671 };
1672
1673 /*
1674 * Pipe currently driving the port. Used for preventing
1675 * the use of the PPS for any pipe currentrly driving
1676 * external DP as that will mess things up on VLV.
1677 */
1678 enum pipe active_pipe;
1679 /*
1680 * Set if the sequencer may be reset due to a power transition,
1681 * requiring a reinitialization. Only relevant on BXT+.
1682 */
1683 bool pps_reset;
1684 struct edp_power_seq pps_delays;
1685 struct edp_power_seq bios_pps_delays;
1686 };
1687
1688 struct intel_psr {
1689 /* Mutex for PSR state of the transcoder */
1690 struct mutex lock;
1691
1692 #define I915_PSR_DEBUG_MODE_MASK 0x0f
1693 #define I915_PSR_DEBUG_DEFAULT 0x00
1694 #define I915_PSR_DEBUG_DISABLE 0x01
1695 #define I915_PSR_DEBUG_ENABLE 0x02
1696 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
1697 #define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4
1698 #define I915_PSR_DEBUG_IRQ 0x10
1699
1700 u32 debug;
1701 bool sink_support;
1702 bool source_support;
1703 bool enabled;
1704 bool paused;
1705 enum pipe pipe;
1706 enum transcoder transcoder;
1707 bool active;
1708 struct work_struct work;
1709 unsigned int busy_frontbuffer_bits;
1710 bool sink_psr2_support;
1711 bool link_standby;
1712 bool colorimetry_support;
1713 bool psr2_enabled;
1714 bool psr2_sel_fetch_enabled;
1715 bool psr2_sel_fetch_cff_enabled;
1716 bool req_psr2_sdp_prior_scanline;
1717 u8 sink_sync_latency;
1718 u8 io_wake_lines;
1719 u8 fast_wake_lines;
1720 ktime_t last_entry_attempt;
1721 ktime_t last_exit;
1722 bool sink_not_reliable;
1723 bool irq_aux_error;
1724 u16 su_w_granularity;
1725 u16 su_y_granularity;
1726 bool source_panel_replay_support;
1727 bool sink_panel_replay_support;
1728 bool panel_replay_enabled;
1729 u32 dc3co_exitline;
1730 u32 dc3co_exit_delay;
1731 struct delayed_work dc3co_work;
1732 u8 entry_setup_frames;
1733 };
1734
1735 struct intel_dp {
1736 i915_reg_t output_reg;
1737 u32 DP;
1738 int link_rate;
1739 u8 lane_count;
1740 u8 sink_count;
1741 bool link_trained;
1742 bool reset_link_params;
1743 bool use_max_params;
1744 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1745 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1746 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1747 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1748 u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
1749 u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
1750 u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
1751 /* source rates */
1752 int num_source_rates;
1753 const int *source_rates;
1754 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1755 int num_sink_rates;
1756 int sink_rates[DP_MAX_SUPPORTED_RATES];
1757 bool use_rate_select;
1758 /* Max sink lane count as reported by DP_MAX_LANE_COUNT */
1759 int max_sink_lane_count;
1760 /* intersection of source and sink rates */
1761 int num_common_rates;
1762 int common_rates[DP_MAX_SUPPORTED_RATES];
1763 /* Max lane count for the current link */
1764 int max_link_lane_count;
1765 /* Max rate for the current link */
1766 int max_link_rate;
1767 int mso_link_count;
1768 int mso_pixel_overlap;
1769 /* sink or branch descriptor */
1770 struct drm_dp_desc desc;
1771 struct drm_dp_aux aux;
1772 u32 aux_busy_last_status;
1773 u8 train_set[4];
1774
1775 struct intel_pps pps;
1776
1777 bool is_mst;
1778 int active_mst_links;
1779
1780 /* connector directly attached - won't be use for modeset in mst world */
1781 struct intel_connector *attached_connector;
1782
1783 /* mst connector list */
1784 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1785 struct drm_dp_mst_topology_mgr mst_mgr;
1786
1787 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1788 /*
1789 * This function returns the value we have to program the AUX_CTL
1790 * register with to kick off an AUX transaction.
1791 */
1792 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1793 u32 aux_clock_divider);
1794
1795 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1796 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1797
1798 /* This is called before a link training is starterd */
1799 void (*prepare_link_retrain)(struct intel_dp *intel_dp,
1800 const struct intel_crtc_state *crtc_state);
1801 void (*set_link_train)(struct intel_dp *intel_dp,
1802 const struct intel_crtc_state *crtc_state,
1803 u8 dp_train_pat);
1804 void (*set_idle_link_train)(struct intel_dp *intel_dp,
1805 const struct intel_crtc_state *crtc_state);
1806
1807 u8 (*preemph_max)(struct intel_dp *intel_dp);
1808 u8 (*voltage_max)(struct intel_dp *intel_dp,
1809 const struct intel_crtc_state *crtc_state);
1810
1811 /* Displayport compliance testing */
1812 struct intel_dp_compliance compliance;
1813
1814 /* Downstream facing port caps */
1815 struct {
1816 int min_tmds_clock, max_tmds_clock;
1817 int max_dotclock;
1818 int pcon_max_frl_bw;
1819 u8 max_bpc;
1820 bool ycbcr_444_to_420;
1821 bool ycbcr420_passthrough;
1822 bool rgb_to_ycbcr;
1823 } dfp;
1824
1825 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1826 struct pm_qos_request pm_qos;
1827
1828 /* Display stream compression testing */
1829 bool force_dsc_en;
1830 int force_dsc_output_format;
1831 bool force_dsc_fractional_bpp_en;
1832 int force_dsc_bpc;
1833
1834 bool hobl_failed;
1835 bool hobl_active;
1836
1837 struct intel_dp_pcon_frl frl;
1838
1839 struct intel_psr psr;
1840
1841 /* When we last wrote the OUI for eDP */
1842 unsigned long last_oui_write;
1843 };
1844
1845 enum lspcon_vendor {
1846 LSPCON_VENDOR_MCA,
1847 LSPCON_VENDOR_PARADE
1848 };
1849
1850 struct intel_lspcon {
1851 bool active;
1852 bool hdr_supported;
1853 enum drm_lspcon_mode mode;
1854 enum lspcon_vendor vendor;
1855 };
1856
1857 struct intel_digital_port {
1858 struct intel_encoder base;
1859 u32 saved_port_bits;
1860 struct intel_dp dp;
1861 struct intel_hdmi hdmi;
1862 struct intel_lspcon lspcon;
1863 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1864 bool release_cl2_override;
1865 u8 max_lanes;
1866 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1867 enum aux_ch aux_ch;
1868 enum intel_display_power_domain ddi_io_power_domain;
1869 intel_wakeref_t ddi_io_wakeref;
1870 intel_wakeref_t aux_wakeref;
1871
1872 struct intel_tc_port *tc;
1873
1874 /* protects num_hdcp_streams reference count, hdcp_port_data and hdcp_auth_status */
1875 struct mutex hdcp_mutex;
1876 /* the number of pipes using HDCP signalling out of this port */
1877 unsigned int num_hdcp_streams;
1878 /* port HDCP auth status */
1879 bool hdcp_auth_status;
1880 /* HDCP port data need to pass to security f/w */
1881 struct hdcp_port_data hdcp_port_data;
1882 /* Whether the MST topology supports HDCP Type 1 Content */
1883 bool hdcp_mst_type1_capable;
1884
1885 void (*write_infoframe)(struct intel_encoder *encoder,
1886 const struct intel_crtc_state *crtc_state,
1887 unsigned int type,
1888 const void *frame, ssize_t len);
1889 void (*read_infoframe)(struct intel_encoder *encoder,
1890 const struct intel_crtc_state *crtc_state,
1891 unsigned int type,
1892 void *frame, ssize_t len);
1893 void (*set_infoframes)(struct intel_encoder *encoder,
1894 bool enable,
1895 const struct intel_crtc_state *crtc_state,
1896 const struct drm_connector_state *conn_state);
1897 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1898 const struct intel_crtc_state *pipe_config);
1899 bool (*connected)(struct intel_encoder *encoder);
1900 };
1901
1902 struct intel_dp_mst_encoder {
1903 struct intel_encoder base;
1904 enum pipe pipe;
1905 struct intel_digital_port *primary;
1906 struct intel_connector *connector;
1907 };
1908
1909 static inline struct intel_encoder *
intel_attached_encoder(struct intel_connector * connector)1910 intel_attached_encoder(struct intel_connector *connector)
1911 {
1912 return connector->encoder;
1913 }
1914
intel_encoder_is_dig_port(struct intel_encoder * encoder)1915 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1916 {
1917 switch (encoder->type) {
1918 case INTEL_OUTPUT_DDI:
1919 case INTEL_OUTPUT_DP:
1920 case INTEL_OUTPUT_EDP:
1921 case INTEL_OUTPUT_HDMI:
1922 return true;
1923 default:
1924 return false;
1925 }
1926 }
1927
intel_encoder_is_mst(struct intel_encoder * encoder)1928 static inline bool intel_encoder_is_mst(struct intel_encoder *encoder)
1929 {
1930 return encoder->type == INTEL_OUTPUT_DP_MST;
1931 }
1932
1933 static inline struct intel_dp_mst_encoder *
enc_to_mst(struct intel_encoder * encoder)1934 enc_to_mst(struct intel_encoder *encoder)
1935 {
1936 return container_of(&encoder->base, struct intel_dp_mst_encoder,
1937 base.base);
1938 }
1939
1940 static inline struct intel_digital_port *
enc_to_dig_port(struct intel_encoder * encoder)1941 enc_to_dig_port(struct intel_encoder *encoder)
1942 {
1943 struct intel_encoder *intel_encoder = encoder;
1944
1945 if (intel_encoder_is_dig_port(intel_encoder))
1946 return container_of(&encoder->base, struct intel_digital_port,
1947 base.base);
1948 else if (intel_encoder_is_mst(intel_encoder))
1949 return enc_to_mst(encoder)->primary;
1950 else
1951 return NULL;
1952 }
1953
1954 static inline struct intel_digital_port *
intel_attached_dig_port(struct intel_connector * connector)1955 intel_attached_dig_port(struct intel_connector *connector)
1956 {
1957 return enc_to_dig_port(intel_attached_encoder(connector));
1958 }
1959
1960 static inline struct intel_hdmi *
enc_to_intel_hdmi(struct intel_encoder * encoder)1961 enc_to_intel_hdmi(struct intel_encoder *encoder)
1962 {
1963 return &enc_to_dig_port(encoder)->hdmi;
1964 }
1965
1966 static inline struct intel_hdmi *
intel_attached_hdmi(struct intel_connector * connector)1967 intel_attached_hdmi(struct intel_connector *connector)
1968 {
1969 return enc_to_intel_hdmi(intel_attached_encoder(connector));
1970 }
1971
enc_to_intel_dp(struct intel_encoder * encoder)1972 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)
1973 {
1974 return &enc_to_dig_port(encoder)->dp;
1975 }
1976
intel_attached_dp(struct intel_connector * connector)1977 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector)
1978 {
1979 return enc_to_intel_dp(intel_attached_encoder(connector));
1980 }
1981
intel_encoder_is_dp(struct intel_encoder * encoder)1982 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1983 {
1984 switch (encoder->type) {
1985 case INTEL_OUTPUT_DP:
1986 case INTEL_OUTPUT_EDP:
1987 return true;
1988 case INTEL_OUTPUT_DDI:
1989 /* Skip pure HDMI/DVI DDI encoders */
1990 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg);
1991 default:
1992 return false;
1993 }
1994 }
1995
1996 static inline struct intel_lspcon *
enc_to_intel_lspcon(struct intel_encoder * encoder)1997 enc_to_intel_lspcon(struct intel_encoder *encoder)
1998 {
1999 return &enc_to_dig_port(encoder)->lspcon;
2000 }
2001
2002 static inline struct intel_digital_port *
dp_to_dig_port(struct intel_dp * intel_dp)2003 dp_to_dig_port(struct intel_dp *intel_dp)
2004 {
2005 return container_of(intel_dp, struct intel_digital_port, dp);
2006 }
2007
2008 static inline struct intel_lspcon *
dp_to_lspcon(struct intel_dp * intel_dp)2009 dp_to_lspcon(struct intel_dp *intel_dp)
2010 {
2011 return &dp_to_dig_port(intel_dp)->lspcon;
2012 }
2013
2014 #define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
2015
2016 static inline struct intel_digital_port *
hdmi_to_dig_port(struct intel_hdmi * intel_hdmi)2017 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
2018 {
2019 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
2020 }
2021
2022 static inline struct intel_plane_state *
intel_atomic_get_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)2023 intel_atomic_get_plane_state(struct intel_atomic_state *state,
2024 struct intel_plane *plane)
2025 {
2026 struct drm_plane_state *ret =
2027 drm_atomic_get_plane_state(&state->base, &plane->base);
2028
2029 if (IS_ERR(ret))
2030 return ERR_CAST(ret);
2031
2032 return to_intel_plane_state(ret);
2033 }
2034
2035 static inline struct intel_plane_state *
intel_atomic_get_old_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)2036 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
2037 struct intel_plane *plane)
2038 {
2039 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
2040 &plane->base));
2041 }
2042
2043 static inline struct intel_plane_state *
intel_atomic_get_new_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)2044 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
2045 struct intel_plane *plane)
2046 {
2047 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
2048 &plane->base));
2049 }
2050
2051 static inline struct intel_crtc_state *
intel_atomic_get_old_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)2052 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
2053 struct intel_crtc *crtc)
2054 {
2055 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
2056 &crtc->base));
2057 }
2058
2059 static inline struct intel_crtc_state *
intel_atomic_get_new_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)2060 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
2061 struct intel_crtc *crtc)
2062 {
2063 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
2064 &crtc->base));
2065 }
2066
2067 static inline struct intel_digital_connector_state *
intel_atomic_get_new_connector_state(struct intel_atomic_state * state,struct intel_connector * connector)2068 intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
2069 struct intel_connector *connector)
2070 {
2071 return to_intel_digital_connector_state(
2072 drm_atomic_get_new_connector_state(&state->base,
2073 &connector->base));
2074 }
2075
2076 static inline struct intel_digital_connector_state *
intel_atomic_get_old_connector_state(struct intel_atomic_state * state,struct intel_connector * connector)2077 intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
2078 struct intel_connector *connector)
2079 {
2080 return to_intel_digital_connector_state(
2081 drm_atomic_get_old_connector_state(&state->base,
2082 &connector->base));
2083 }
2084
2085 /* intel_display.c */
2086 static inline bool
intel_crtc_has_type(const struct intel_crtc_state * crtc_state,enum intel_output_type type)2087 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
2088 enum intel_output_type type)
2089 {
2090 return crtc_state->output_types & BIT(type);
2091 }
2092
2093 static inline bool
intel_crtc_has_dp_encoder(const struct intel_crtc_state * crtc_state)2094 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
2095 {
2096 return crtc_state->output_types &
2097 (BIT(INTEL_OUTPUT_DP) |
2098 BIT(INTEL_OUTPUT_DP_MST) |
2099 BIT(INTEL_OUTPUT_EDP));
2100 }
2101
2102 static inline bool
intel_crtc_needs_modeset(const struct intel_crtc_state * crtc_state)2103 intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state)
2104 {
2105 return drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
2106 }
2107
2108 static inline bool
intel_crtc_needs_fastset(const struct intel_crtc_state * crtc_state)2109 intel_crtc_needs_fastset(const struct intel_crtc_state *crtc_state)
2110 {
2111 return crtc_state->update_pipe;
2112 }
2113
2114 static inline bool
intel_crtc_needs_color_update(const struct intel_crtc_state * crtc_state)2115 intel_crtc_needs_color_update(const struct intel_crtc_state *crtc_state)
2116 {
2117 return crtc_state->uapi.color_mgmt_changed ||
2118 intel_crtc_needs_fastset(crtc_state) ||
2119 intel_crtc_needs_modeset(crtc_state);
2120 }
2121
intel_plane_ggtt_offset(const struct intel_plane_state * plane_state)2122 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state)
2123 {
2124 return i915_ggtt_offset(plane_state->ggtt_vma);
2125 }
2126
2127 static inline struct intel_frontbuffer *
to_intel_frontbuffer(struct drm_framebuffer * fb)2128 to_intel_frontbuffer(struct drm_framebuffer *fb)
2129 {
2130 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
2131 }
2132
to_bpp_int(int bpp_x16)2133 static inline int to_bpp_int(int bpp_x16)
2134 {
2135 return bpp_x16 >> 4;
2136 }
2137
to_bpp_frac(int bpp_x16)2138 static inline int to_bpp_frac(int bpp_x16)
2139 {
2140 return bpp_x16 & 0xf;
2141 }
2142
2143 #define BPP_X16_FMT "%d.%04d"
2144 #define BPP_X16_ARGS(bpp_x16) to_bpp_int(bpp_x16), (to_bpp_frac(bpp_x16) * 625)
2145
to_bpp_int_roundup(int bpp_x16)2146 static inline int to_bpp_int_roundup(int bpp_x16)
2147 {
2148 return (bpp_x16 + 0xf) >> 4;
2149 }
2150
to_bpp_x16(int bpp)2151 static inline int to_bpp_x16(int bpp)
2152 {
2153 return bpp << 4;
2154 }
2155
2156 #endif /* __INTEL_DISPLAY_TYPES_H__ */
2157