1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Common library for ADIS16XXX devices
4 *
5 * Copyright 2012 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 */
8
9 #ifndef __IIO_ADIS_H__
10 #define __IIO_ADIS_H__
11
12 #include <linux/cleanup.h>
13 #include <linux/spi/spi.h>
14 #include <linux/interrupt.h>
15 #include <linux/iio/iio.h>
16 #include <linux/iio/types.h>
17
18 #define ADIS_WRITE_REG(reg) ((0x80 | (reg)))
19 #define ADIS_READ_REG(reg) ((reg) & 0x7f)
20
21 #define ADIS_PAGE_SIZE 0x80
22 #define ADIS_REG_PAGE_ID 0x00
23
24 struct adis;
25 struct iio_dev_attr;
26
27 /**
28 * struct adis_timeouts - ADIS chip variant timeouts
29 * @reset_ms - Wait time after rst pin goes inactive
30 * @sw_reset_ms - Wait time after sw reset command
31 * @self_test_ms - Wait time after self test command
32 */
33 struct adis_timeout {
34 u16 reset_ms;
35 u16 sw_reset_ms;
36 u16 self_test_ms;
37 };
38
39 /**
40 * struct adis_data - ADIS chip variant specific data
41 * @read_delay: SPI delay for read operations in us
42 * @write_delay: SPI delay for write operations in us
43 * @cs_change_delay: SPI delay between CS changes in us
44 * @glob_cmd_reg: Register address of the GLOB_CMD register
45 * @msc_ctrl_reg: Register address of the MSC_CTRL register
46 * @diag_stat_reg: Register address of the DIAG_STAT register
47 * @diag_stat_size: Length (in bytes) of the DIAG_STAT register. If 0 the
48 * default length is 2 bytes long.
49 * @prod_id_reg: Register address of the PROD_ID register
50 * @prod_id: Product ID code that should be expected when reading @prod_id_reg
51 * @self_test_mask: Bitmask of supported self-test operations
52 * @self_test_reg: Register address to request self test command
53 * @self_test_no_autoclear: True if device's self-test needs clear of ctrl reg
54 * @status_error_msgs: Array of error messages
55 * @status_error_mask: Bitmask of errors supported by the device
56 * @timeouts: Chip specific delays
57 * @enable_irq: Hook for ADIS devices that have a special IRQ enable/disable
58 * @unmasked_drdy: True for devices that cannot mask/unmask the data ready pin
59 * @has_paging: True if ADIS device has paged registers
60 * @burst_reg_cmd: Register command that triggers burst
61 * @burst_len: Burst size in the SPI RX buffer. If @burst_max_len is defined,
62 * this should be the minimum size supported by the device.
63 * @burst_max_len: Holds the maximum burst size when the device supports
64 * more than one burst mode with different sizes
65 * @burst_max_speed_hz: Maximum spi speed that can be used in burst mode
66 */
67 struct adis_data {
68 unsigned int read_delay;
69 unsigned int write_delay;
70 unsigned int cs_change_delay;
71
72 unsigned int glob_cmd_reg;
73 unsigned int msc_ctrl_reg;
74 unsigned int diag_stat_reg;
75 unsigned int diag_stat_size;
76 unsigned int prod_id_reg;
77
78 unsigned int prod_id;
79
80 unsigned int self_test_mask;
81 unsigned int self_test_reg;
82 bool self_test_no_autoclear;
83 const struct adis_timeout *timeouts;
84
85 const char * const *status_error_msgs;
86 unsigned int status_error_mask;
87
88 int (*enable_irq)(struct adis *adis, bool enable);
89 bool unmasked_drdy;
90
91 bool has_paging;
92 bool has_fifo;
93
94 unsigned int burst_reg_cmd;
95 unsigned int burst_len;
96 unsigned int burst_max_len;
97 unsigned int burst_max_speed_hz;
98 };
99
100 /**
101 * struct adis_ops: Custom ops for adis devices.
102 * @write: Custom spi write implementation.
103 * @read: Custom spi read implementation.
104 * @reset: Custom sw reset implementation. The custom implementation does not
105 * need to sleep after the reset. It's done by the library already.
106 */
107 struct adis_ops {
108 int (*write)(struct adis *adis, unsigned int reg, unsigned int value,
109 unsigned int size);
110 int (*read)(struct adis *adis, unsigned int reg, unsigned int *value,
111 unsigned int size);
112 int (*reset)(struct adis *adis);
113 };
114
115 /**
116 * struct adis - ADIS device instance data
117 * @spi: Reference to SPI device which owns this ADIS IIO device
118 * @trig: IIO trigger object data
119 * @data: ADIS chip variant specific data
120 * @burst_extra_len: Burst extra length. Should only be used by devices that can
121 * dynamically change their burst mode length.
122 * @ops: ops struct for custom read and write functions
123 * @state_lock: Lock used by the device to protect state
124 * @msg: SPI message object
125 * @xfer: SPI transfer objects to be used for a @msg
126 * @current_page: Some ADIS devices have registers, this selects current page
127 * @irq_flag: IRQ handling flags as passed to request_irq()
128 * @buffer: Data buffer for information read from the device
129 * @tx: DMA safe TX buffer for SPI transfers
130 * @rx: DMA safe RX buffer for SPI transfers
131 */
132 struct adis {
133 struct spi_device *spi;
134 struct iio_trigger *trig;
135
136 const struct adis_data *data;
137 unsigned int burst_extra_len;
138 const struct adis_ops *ops;
139 /**
140 * The state_lock is meant to be used during operations that require
141 * a sequence of SPI R/W in order to protect the SPI transfer
142 * information (fields 'xfer', 'msg' & 'current_page') between
143 * potential concurrent accesses.
144 * This lock is used by all "adis_{functions}" that have to read/write
145 * registers. These functions also have unlocked variants
146 * (see "__adis_{functions}"), which don't hold this lock.
147 * This allows users of the ADIS library to group SPI R/W into
148 * the drivers, but they also must manage this lock themselves.
149 */
150 struct mutex state_lock;
151 struct spi_message msg;
152 struct spi_transfer *xfer;
153 unsigned int current_page;
154 unsigned long irq_flag;
155 void *buffer;
156
157 u8 tx[10] __aligned(IIO_DMA_MINALIGN);
158 u8 rx[4];
159 };
160
161 int adis_init(struct adis *adis, struct iio_dev *indio_dev,
162 struct spi_device *spi, const struct adis_data *data);
163 int __adis_reset(struct adis *adis);
164
165 /**
166 * adis_reset() - Reset the device
167 * @adis: The adis device
168 *
169 * Returns 0 on success, a negative error code otherwise
170 */
adis_reset(struct adis * adis)171 static inline int adis_reset(struct adis *adis)
172 {
173 guard(mutex)(&adis->state_lock);
174 return __adis_reset(adis);
175 }
176
177 int __adis_write_reg(struct adis *adis, unsigned int reg,
178 unsigned int val, unsigned int size);
179 int __adis_read_reg(struct adis *adis, unsigned int reg,
180 unsigned int *val, unsigned int size);
181
182 /**
183 * __adis_write_reg_8() - Write single byte to a register (unlocked)
184 * @adis: The adis device
185 * @reg: The address of the register to be written
186 * @value: The value to write
187 */
__adis_write_reg_8(struct adis * adis,unsigned int reg,u8 val)188 static inline int __adis_write_reg_8(struct adis *adis, unsigned int reg,
189 u8 val)
190 {
191 return adis->ops->write(adis, reg, val, 1);
192 }
193
194 /**
195 * __adis_write_reg_16() - Write 2 bytes to a pair of registers (unlocked)
196 * @adis: The adis device
197 * @reg: The address of the lower of the two registers
198 * @value: Value to be written
199 */
__adis_write_reg_16(struct adis * adis,unsigned int reg,u16 val)200 static inline int __adis_write_reg_16(struct adis *adis, unsigned int reg,
201 u16 val)
202 {
203 return adis->ops->write(adis, reg, val, 2);
204 }
205
206 /**
207 * __adis_write_reg_32() - write 4 bytes to four registers (unlocked)
208 * @adis: The adis device
209 * @reg: The address of the lower of the four register
210 * @value: Value to be written
211 */
__adis_write_reg_32(struct adis * adis,unsigned int reg,u32 val)212 static inline int __adis_write_reg_32(struct adis *adis, unsigned int reg,
213 u32 val)
214 {
215 return adis->ops->write(adis, reg, val, 4);
216 }
217
218 /**
219 * __adis_read_reg_16() - read 2 bytes from a 16-bit register (unlocked)
220 * @adis: The adis device
221 * @reg: The address of the lower of the two registers
222 * @val: The value read back from the device
223 */
__adis_read_reg_16(struct adis * adis,unsigned int reg,u16 * val)224 static inline int __adis_read_reg_16(struct adis *adis, unsigned int reg,
225 u16 *val)
226 {
227 unsigned int tmp;
228 int ret;
229
230 ret = adis->ops->read(adis, reg, &tmp, 2);
231 if (ret == 0)
232 *val = tmp;
233
234 return ret;
235 }
236
237 /**
238 * __adis_read_reg_32() - read 4 bytes from a 32-bit register (unlocked)
239 * @adis: The adis device
240 * @reg: The address of the lower of the two registers
241 * @val: The value read back from the device
242 */
__adis_read_reg_32(struct adis * adis,unsigned int reg,u32 * val)243 static inline int __adis_read_reg_32(struct adis *adis, unsigned int reg,
244 u32 *val)
245 {
246 unsigned int tmp;
247 int ret;
248
249 ret = adis->ops->read(adis, reg, &tmp, 4);
250 if (ret == 0)
251 *val = tmp;
252
253 return ret;
254 }
255
256 /**
257 * adis_write_reg() - write N bytes to register
258 * @adis: The adis device
259 * @reg: The address of the lower of the two registers
260 * @value: The value to write to device (up to 4 bytes)
261 * @size: The size of the @value (in bytes)
262 */
adis_write_reg(struct adis * adis,unsigned int reg,unsigned int val,unsigned int size)263 static inline int adis_write_reg(struct adis *adis, unsigned int reg,
264 unsigned int val, unsigned int size)
265 {
266 guard(mutex)(&adis->state_lock);
267 return adis->ops->write(adis, reg, val, size);
268 }
269
270 /**
271 * adis_read_reg() - read N bytes from register
272 * @adis: The adis device
273 * @reg: The address of the lower of the two registers
274 * @val: The value read back from the device
275 * @size: The size of the @val buffer
276 */
adis_read_reg(struct adis * adis,unsigned int reg,unsigned int * val,unsigned int size)277 static int adis_read_reg(struct adis *adis, unsigned int reg,
278 unsigned int *val, unsigned int size)
279 {
280 guard(mutex)(&adis->state_lock);
281 return adis->ops->read(adis, reg, val, size);
282 }
283
284 /**
285 * adis_write_reg_8() - Write single byte to a register
286 * @adis: The adis device
287 * @reg: The address of the register to be written
288 * @value: The value to write
289 */
adis_write_reg_8(struct adis * adis,unsigned int reg,u8 val)290 static inline int adis_write_reg_8(struct adis *adis, unsigned int reg,
291 u8 val)
292 {
293 return adis_write_reg(adis, reg, val, 1);
294 }
295
296 /**
297 * adis_write_reg_16() - Write 2 bytes to a pair of registers
298 * @adis: The adis device
299 * @reg: The address of the lower of the two registers
300 * @value: Value to be written
301 */
adis_write_reg_16(struct adis * adis,unsigned int reg,u16 val)302 static inline int adis_write_reg_16(struct adis *adis, unsigned int reg,
303 u16 val)
304 {
305 return adis_write_reg(adis, reg, val, 2);
306 }
307
308 /**
309 * adis_write_reg_32() - write 4 bytes to four registers
310 * @adis: The adis device
311 * @reg: The address of the lower of the four register
312 * @value: Value to be written
313 */
adis_write_reg_32(struct adis * adis,unsigned int reg,u32 val)314 static inline int adis_write_reg_32(struct adis *adis, unsigned int reg,
315 u32 val)
316 {
317 return adis_write_reg(adis, reg, val, 4);
318 }
319
320 /**
321 * adis_read_reg_16() - read 2 bytes from a 16-bit register
322 * @adis: The adis device
323 * @reg: The address of the lower of the two registers
324 * @val: The value read back from the device
325 */
adis_read_reg_16(struct adis * adis,unsigned int reg,u16 * val)326 static inline int adis_read_reg_16(struct adis *adis, unsigned int reg,
327 u16 *val)
328 {
329 unsigned int tmp;
330 int ret;
331
332 ret = adis_read_reg(adis, reg, &tmp, 2);
333 if (ret == 0)
334 *val = tmp;
335
336 return ret;
337 }
338
339 /**
340 * adis_read_reg_32() - read 4 bytes from a 32-bit register
341 * @adis: The adis device
342 * @reg: The address of the lower of the two registers
343 * @val: The value read back from the device
344 */
adis_read_reg_32(struct adis * adis,unsigned int reg,u32 * val)345 static inline int adis_read_reg_32(struct adis *adis, unsigned int reg,
346 u32 *val)
347 {
348 unsigned int tmp;
349 int ret;
350
351 ret = adis_read_reg(adis, reg, &tmp, 4);
352 if (ret == 0)
353 *val = tmp;
354
355 return ret;
356 }
357
358 int __adis_update_bits_base(struct adis *adis, unsigned int reg, const u32 mask,
359 const u32 val, u8 size);
360 /**
361 * adis_update_bits_base() - ADIS Update bits function - Locked version
362 * @adis: The adis device
363 * @reg: The address of the lower of the two registers
364 * @mask: Bitmask to change
365 * @val: Value to be written
366 * @size: Size of the register to update
367 *
368 * Updates the desired bits of @reg in accordance with @mask and @val.
369 */
adis_update_bits_base(struct adis * adis,unsigned int reg,const u32 mask,const u32 val,u8 size)370 static inline int adis_update_bits_base(struct adis *adis, unsigned int reg,
371 const u32 mask, const u32 val, u8 size)
372 {
373 guard(mutex)(&adis->state_lock);
374 return __adis_update_bits_base(adis, reg, mask, val, size);
375 }
376
377 /**
378 * adis_update_bits() - Wrapper macro for adis_update_bits_base - Locked version
379 * @adis: The adis device
380 * @reg: The address of the lower of the two registers
381 * @mask: Bitmask to change
382 * @val: Value to be written
383 *
384 * This macro evaluates the sizeof of @val at compile time and calls
385 * adis_update_bits_base() accordingly. Be aware that using MACROS/DEFINES for
386 * @val can lead to undesired behavior if the register to update is 16bit.
387 */
388 #define adis_update_bits(adis, reg, mask, val) ({ \
389 BUILD_BUG_ON(sizeof(val) != 2 && sizeof(val) != 4); \
390 adis_update_bits_base(adis, reg, mask, val, sizeof(val)); \
391 })
392
393 /**
394 * adis_update_bits() - Wrapper macro for adis_update_bits_base
395 * @adis: The adis device
396 * @reg: The address of the lower of the two registers
397 * @mask: Bitmask to change
398 * @val: Value to be written
399 *
400 * This macro evaluates the sizeof of @val at compile time and calls
401 * adis_update_bits_base() accordingly. Be aware that using MACROS/DEFINES for
402 * @val can lead to undesired behavior if the register to update is 16bit.
403 */
404 #define __adis_update_bits(adis, reg, mask, val) ({ \
405 BUILD_BUG_ON(sizeof(val) != 2 && sizeof(val) != 4); \
406 __adis_update_bits_base(adis, reg, mask, val, sizeof(val)); \
407 })
408
409 int __adis_check_status(struct adis *adis);
410 int __adis_initial_startup(struct adis *adis);
411 int __adis_enable_irq(struct adis *adis, bool enable);
412
adis_enable_irq(struct adis * adis,bool enable)413 static inline int adis_enable_irq(struct adis *adis, bool enable)
414 {
415 guard(mutex)(&adis->state_lock);
416 return __adis_enable_irq(adis, enable);
417 }
418
adis_check_status(struct adis * adis)419 static inline int adis_check_status(struct adis *adis)
420 {
421 guard(mutex)(&adis->state_lock);
422 return __adis_check_status(adis);
423 }
424
425 #define adis_dev_auto_lock(adis) guard(mutex)(&(adis)->state_lock)
426 #define adis_dev_auto_scoped_lock(adis) \
427 scoped_guard(mutex, &(adis)->state_lock)
428
429 int adis_single_conversion(struct iio_dev *indio_dev,
430 const struct iio_chan_spec *chan,
431 unsigned int error_mask, int *val);
432
433 #define ADIS_VOLTAGE_CHAN(addr, si, chan, name, info_all, bits) { \
434 .type = IIO_VOLTAGE, \
435 .indexed = 1, \
436 .channel = (chan), \
437 .extend_name = name, \
438 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
439 BIT(IIO_CHAN_INFO_SCALE), \
440 .info_mask_shared_by_all = info_all, \
441 .address = (addr), \
442 .scan_index = (si), \
443 .scan_type = { \
444 .sign = 'u', \
445 .realbits = (bits), \
446 .storagebits = 16, \
447 .endianness = IIO_BE, \
448 }, \
449 }
450
451 #define ADIS_SUPPLY_CHAN(addr, si, info_all, bits) \
452 ADIS_VOLTAGE_CHAN(addr, si, 0, "supply", info_all, bits)
453
454 #define ADIS_AUX_ADC_CHAN(addr, si, info_all, bits) \
455 ADIS_VOLTAGE_CHAN(addr, si, 1, NULL, info_all, bits)
456
457 #define ADIS_TEMP_CHAN(addr, si, info_all, bits) { \
458 .type = IIO_TEMP, \
459 .indexed = 1, \
460 .channel = 0, \
461 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
462 BIT(IIO_CHAN_INFO_SCALE) | \
463 BIT(IIO_CHAN_INFO_OFFSET), \
464 .info_mask_shared_by_all = info_all, \
465 .address = (addr), \
466 .scan_index = (si), \
467 .scan_type = { \
468 .sign = 'u', \
469 .realbits = (bits), \
470 .storagebits = 16, \
471 .endianness = IIO_BE, \
472 }, \
473 }
474
475 #define ADIS_MOD_CHAN(_type, mod, addr, si, info_sep, info_all, bits) { \
476 .type = (_type), \
477 .modified = 1, \
478 .channel2 = IIO_MOD_ ## mod, \
479 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
480 (info_sep), \
481 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
482 .info_mask_shared_by_all = info_all, \
483 .address = (addr), \
484 .scan_index = (si), \
485 .scan_type = { \
486 .sign = 's', \
487 .realbits = (bits), \
488 .storagebits = 16, \
489 .endianness = IIO_BE, \
490 }, \
491 }
492
493 #define ADIS_ACCEL_CHAN(mod, addr, si, info_sep, info_all, bits) \
494 ADIS_MOD_CHAN(IIO_ACCEL, mod, addr, si, info_sep, info_all, bits)
495
496 #define ADIS_GYRO_CHAN(mod, addr, si, info_sep, info_all, bits) \
497 ADIS_MOD_CHAN(IIO_ANGL_VEL, mod, addr, si, info_sep, info_all, bits)
498
499 #define ADIS_INCLI_CHAN(mod, addr, si, info_sep, info_all, bits) \
500 ADIS_MOD_CHAN(IIO_INCLI, mod, addr, si, info_sep, info_all, bits)
501
502 #define ADIS_ROT_CHAN(mod, addr, si, info_sep, info_all, bits) \
503 ADIS_MOD_CHAN(IIO_ROT, mod, addr, si, info_sep, info_all, bits)
504
505 #define devm_adis_setup_buffer_and_trigger(adis, indio_dev, trigger_handler) \
506 devm_adis_setup_buffer_and_trigger_with_attrs((adis), (indio_dev), \
507 (trigger_handler), NULL, \
508 NULL)
509
510 #ifdef CONFIG_IIO_ADIS_LIB_BUFFER
511
512 int
513 devm_adis_setup_buffer_and_trigger_with_attrs(struct adis *adis,
514 struct iio_dev *indio_dev,
515 irq_handler_t trigger_handler,
516 const struct iio_buffer_setup_ops *ops,
517 const struct iio_dev_attr **buffer_attrs);
518
519 int devm_adis_probe_trigger(struct adis *adis, struct iio_dev *indio_dev);
520
521 int adis_update_scan_mode(struct iio_dev *indio_dev,
522 const unsigned long *scan_mask);
523
524 #else /* CONFIG_IIO_BUFFER */
525
526 static inline int
devm_adis_setup_buffer_and_trigger_with_attrs(struct adis * adis,struct iio_dev * indio_dev,irq_handler_t trigger_handler,const struct iio_buffer_setup_ops * ops,const struct iio_dev_attr ** buffer_attrs)527 devm_adis_setup_buffer_and_trigger_with_attrs(struct adis *adis,
528 struct iio_dev *indio_dev,
529 irq_handler_t trigger_handler,
530 const struct iio_buffer_setup_ops *ops,
531 const struct iio_dev_attr **buffer_attrs)
532 {
533 return 0;
534 }
535
devm_adis_probe_trigger(struct adis * adis,struct iio_dev * indio_dev)536 static inline int devm_adis_probe_trigger(struct adis *adis,
537 struct iio_dev *indio_dev)
538 {
539 return 0;
540 }
541
542 #define adis_update_scan_mode NULL
543
544 #endif /* CONFIG_IIO_BUFFER */
545
546 #ifdef CONFIG_DEBUG_FS
547
548 int adis_debugfs_reg_access(struct iio_dev *indio_dev,
549 unsigned int reg, unsigned int writeval,
550 unsigned int *readval);
551
552 #else
553
554 #define adis_debugfs_reg_access NULL
555
556 #endif
557
558 #endif
559