1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2019 HiSilicon Limited. */
3 #ifndef HISI_ACC_QM_H
4 #define HISI_ACC_QM_H
5
6 #include <linux/bitfield.h>
7 #include <linux/debugfs.h>
8 #include <linux/iopoll.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11
12 #define QM_QNUM_V1 4096
13 #define QM_QNUM_V2 1024
14 #define QM_MAX_VFS_NUM_V2 63
15
16 /* qm user domain */
17 #define QM_ARUSER_M_CFG_1 0x100088
18 #define AXUSER_SNOOP_ENABLE BIT(30)
19 #define AXUSER_CMD_TYPE GENMASK(14, 12)
20 #define AXUSER_CMD_SMMU_NORMAL 1
21 #define AXUSER_NS BIT(6)
22 #define AXUSER_NO BIT(5)
23 #define AXUSER_FP BIT(4)
24 #define AXUSER_SSV BIT(0)
25 #define AXUSER_BASE (AXUSER_SNOOP_ENABLE | \
26 FIELD_PREP(AXUSER_CMD_TYPE, \
27 AXUSER_CMD_SMMU_NORMAL) | \
28 AXUSER_NS | AXUSER_NO | AXUSER_FP)
29 #define QM_ARUSER_M_CFG_ENABLE 0x100090
30 #define ARUSER_M_CFG_ENABLE 0xfffffffe
31 #define QM_AWUSER_M_CFG_1 0x100098
32 #define QM_AWUSER_M_CFG_ENABLE 0x1000a0
33 #define AWUSER_M_CFG_ENABLE 0xfffffffe
34 #define QM_WUSER_M_CFG_ENABLE 0x1000a8
35 #define WUSER_M_CFG_ENABLE 0xffffffff
36
37 /* mailbox */
38 #define QM_MB_CMD_SQC 0x0
39 #define QM_MB_CMD_CQC 0x1
40 #define QM_MB_CMD_EQC 0x2
41 #define QM_MB_CMD_AEQC 0x3
42 #define QM_MB_CMD_SQC_BT 0x4
43 #define QM_MB_CMD_CQC_BT 0x5
44 #define QM_MB_CMD_SQC_VFT_V2 0x6
45 #define QM_MB_CMD_STOP_QP 0x8
46 #define QM_MB_CMD_SRC 0xc
47 #define QM_MB_CMD_DST 0xd
48
49 #define QM_MB_CMD_SEND_BASE 0x300
50 #define QM_MB_EVENT_SHIFT 8
51 #define QM_MB_BUSY_SHIFT 13
52 #define QM_MB_OP_SHIFT 14
53 #define QM_MB_CMD_DATA_ADDR_L 0x304
54 #define QM_MB_CMD_DATA_ADDR_H 0x308
55 #define QM_MB_MAX_WAIT_CNT 6000
56
57 /* doorbell */
58 #define QM_DOORBELL_CMD_SQ 0
59 #define QM_DOORBELL_CMD_CQ 1
60 #define QM_DOORBELL_CMD_EQ 2
61 #define QM_DOORBELL_CMD_AEQ 3
62
63 #define QM_DOORBELL_SQ_CQ_BASE_V2 0x1000
64 #define QM_DOORBELL_EQ_AEQ_BASE_V2 0x2000
65 #define QM_QP_MAX_NUM_SHIFT 11
66 #define QM_DB_CMD_SHIFT_V2 12
67 #define QM_DB_RAND_SHIFT_V2 16
68 #define QM_DB_INDEX_SHIFT_V2 32
69 #define QM_DB_PRIORITY_SHIFT_V2 48
70 #define QM_VF_STATE 0x60
71
72 /* qm cache */
73 #define QM_CACHE_CTL 0x100050
74 #define SQC_CACHE_ENABLE BIT(0)
75 #define CQC_CACHE_ENABLE BIT(1)
76 #define SQC_CACHE_WB_ENABLE BIT(4)
77 #define SQC_CACHE_WB_THRD GENMASK(10, 5)
78 #define CQC_CACHE_WB_ENABLE BIT(11)
79 #define CQC_CACHE_WB_THRD GENMASK(17, 12)
80 #define QM_AXI_M_CFG 0x1000ac
81 #define AXI_M_CFG 0xffff
82 #define QM_AXI_M_CFG_ENABLE 0x1000b0
83 #define AM_CFG_SINGLE_PORT_MAX_TRANS 0x300014
84 #define AXI_M_CFG_ENABLE 0xffffffff
85 #define QM_PEH_AXUSER_CFG 0x1000cc
86 #define QM_PEH_AXUSER_CFG_ENABLE 0x1000d0
87 #define PEH_AXUSER_CFG 0x401001
88 #define PEH_AXUSER_CFG_ENABLE 0xffffffff
89
90 #define QM_MIN_QNUM 2
91 #define HISI_ACC_SGL_SGE_NR_MAX 255
92 #define QM_SHAPER_CFG 0x100164
93 #define QM_SHAPER_ENABLE BIT(30)
94 #define QM_SHAPER_TYPE1_OFFSET 10
95
96 /* page number for queue file region */
97 #define QM_DOORBELL_PAGE_NR 1
98
99 /* uacce mode of the driver */
100 #define UACCE_MODE_NOUACCE 0 /* don't use uacce */
101 #define UACCE_MODE_SVA 1 /* use uacce sva mode */
102 #define UACCE_MODE_DESC "0(default) means only register to crypto, 1 means both register to crypto and uacce"
103
104 enum qm_stop_reason {
105 QM_NORMAL,
106 QM_SOFT_RESET,
107 QM_DOWN,
108 };
109
110 enum qm_state {
111 QM_WORK = 0,
112 QM_STOP,
113 };
114
115 enum qp_state {
116 QP_START = 1,
117 QP_STOP,
118 };
119
120 enum qm_hw_ver {
121 QM_HW_V1 = 0x20,
122 QM_HW_V2 = 0x21,
123 QM_HW_V3 = 0x30,
124 };
125
126 enum qm_fun_type {
127 QM_HW_PF,
128 QM_HW_VF,
129 };
130
131 enum qm_debug_file {
132 CURRENT_QM,
133 CURRENT_Q,
134 CLEAR_ENABLE,
135 DEBUG_FILE_NUM,
136 };
137
138 enum qm_vf_state {
139 QM_READY = 0,
140 QM_NOT_READY,
141 };
142
143 enum qm_misc_ctl_bits {
144 QM_DRIVER_REMOVING = 0x0,
145 QM_RST_SCHED,
146 QM_RESETTING,
147 QM_MODULE_PARAM,
148 };
149
150 enum qm_cap_bits {
151 QM_SUPPORT_DB_ISOLATION = 0x0,
152 QM_SUPPORT_FUNC_QOS,
153 QM_SUPPORT_STOP_QP,
154 QM_SUPPORT_MB_COMMAND,
155 QM_SUPPORT_SVA_PREFETCH,
156 QM_SUPPORT_RPM,
157 };
158
159 struct qm_dev_alg {
160 u64 alg_msk;
161 const char *alg;
162 };
163
164 struct dfx_diff_registers {
165 u32 *regs;
166 u32 reg_offset;
167 u32 reg_len;
168 };
169
170 struct qm_dfx {
171 atomic64_t err_irq_cnt;
172 atomic64_t aeq_irq_cnt;
173 atomic64_t abnormal_irq_cnt;
174 atomic64_t create_qp_err_cnt;
175 atomic64_t mb_err_cnt;
176 };
177
178 struct debugfs_file {
179 enum qm_debug_file index;
180 struct mutex lock;
181 struct qm_debug *debug;
182 };
183
184 struct qm_debug {
185 u32 curr_qm_qp_num;
186 u32 sqe_mask_offset;
187 u32 sqe_mask_len;
188 struct qm_dfx dfx;
189 struct dentry *debug_root;
190 struct dentry *qm_d;
191 struct debugfs_file files[DEBUG_FILE_NUM];
192 unsigned int *qm_last_words;
193 /* ACC engines recoreding last regs */
194 unsigned int *last_words;
195 struct dfx_diff_registers *qm_diff_regs;
196 struct dfx_diff_registers *acc_diff_regs;
197 };
198
199 struct qm_shaper_factor {
200 u32 func_qos;
201 u64 cir_b;
202 u64 cir_u;
203 u64 cir_s;
204 u64 cbs_s;
205 };
206
207 struct qm_dma {
208 void *va;
209 dma_addr_t dma;
210 size_t size;
211 };
212
213 struct hisi_qm_status {
214 u32 eq_head;
215 bool eqc_phase;
216 u32 aeq_head;
217 bool aeqc_phase;
218 atomic_t flags;
219 int stop_reason;
220 };
221
222 struct hisi_qm;
223
224 struct hisi_qm_err_info {
225 char *acpi_rst;
226 u32 msi_wr_port;
227 u32 ecc_2bits_mask;
228 u32 qm_shutdown_mask;
229 u32 dev_shutdown_mask;
230 u32 qm_reset_mask;
231 u32 dev_reset_mask;
232 u32 ce;
233 u32 nfe;
234 u32 fe;
235 };
236
237 struct hisi_qm_err_status {
238 u32 is_qm_ecc_mbit;
239 u32 is_dev_ecc_mbit;
240 };
241
242 struct hisi_qm_err_ini {
243 int (*hw_init)(struct hisi_qm *qm);
244 void (*hw_err_enable)(struct hisi_qm *qm);
245 void (*hw_err_disable)(struct hisi_qm *qm);
246 u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
247 void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts);
248 void (*open_axi_master_ooo)(struct hisi_qm *qm);
249 void (*close_axi_master_ooo)(struct hisi_qm *qm);
250 void (*open_sva_prefetch)(struct hisi_qm *qm);
251 void (*close_sva_prefetch)(struct hisi_qm *qm);
252 void (*log_dev_hw_err)(struct hisi_qm *qm, u32 err_sts);
253 void (*show_last_dfx_regs)(struct hisi_qm *qm);
254 void (*err_info_init)(struct hisi_qm *qm);
255 };
256
257 struct hisi_qm_cap_info {
258 u32 type;
259 /* Register offset */
260 u32 offset;
261 /* Bit offset in register */
262 u32 shift;
263 u32 mask;
264 u32 v1_val;
265 u32 v2_val;
266 u32 v3_val;
267 };
268
269 struct hisi_qm_cap_record {
270 u32 type;
271 u32 cap_val;
272 };
273
274 struct hisi_qm_cap_tables {
275 struct hisi_qm_cap_record *qm_cap_table;
276 struct hisi_qm_cap_record *dev_cap_table;
277 };
278
279 struct hisi_qm_list {
280 struct mutex lock;
281 struct list_head list;
282 int (*register_to_crypto)(struct hisi_qm *qm);
283 void (*unregister_from_crypto)(struct hisi_qm *qm);
284 };
285
286 struct hisi_qm_poll_data {
287 struct hisi_qm *qm;
288 struct work_struct work;
289 u16 *qp_finish_id;
290 u16 eqe_num;
291 };
292
293 /**
294 * struct qm_err_isolate
295 * @isolate_lock: protects device error log
296 * @err_threshold: user config error threshold which triggers isolation
297 * @is_isolate: device isolation state
298 * @uacce_hw_errs: index into qm device error list
299 */
300 struct qm_err_isolate {
301 struct mutex isolate_lock;
302 u32 err_threshold;
303 bool is_isolate;
304 struct list_head qm_hw_errs;
305 };
306
307 struct qm_rsv_buf {
308 struct qm_sqc *sqc;
309 struct qm_cqc *cqc;
310 struct qm_eqc *eqc;
311 struct qm_aeqc *aeqc;
312 dma_addr_t sqc_dma;
313 dma_addr_t cqc_dma;
314 dma_addr_t eqc_dma;
315 dma_addr_t aeqc_dma;
316 struct qm_dma qcdma;
317 };
318
319 struct hisi_qm {
320 enum qm_hw_ver ver;
321 enum qm_fun_type fun_type;
322 const char *dev_name;
323 struct pci_dev *pdev;
324 void __iomem *io_base;
325 void __iomem *db_io_base;
326
327 /* Capbility version, 0: not supports */
328 u32 cap_ver;
329 u32 sqe_size;
330 u32 qp_base;
331 u32 qp_num;
332 u32 qp_in_used;
333 u32 ctrl_qp_num;
334 u32 max_qp_num;
335 u32 vfs_num;
336 u32 db_interval;
337 u16 eq_depth;
338 u16 aeq_depth;
339 struct list_head list;
340 struct hisi_qm_list *qm_list;
341
342 struct qm_dma qdma;
343 struct qm_sqc *sqc;
344 struct qm_cqc *cqc;
345 struct qm_eqe *eqe;
346 struct qm_aeqe *aeqe;
347 dma_addr_t sqc_dma;
348 dma_addr_t cqc_dma;
349 dma_addr_t eqe_dma;
350 dma_addr_t aeqe_dma;
351 struct qm_rsv_buf xqc_buf;
352
353 struct hisi_qm_status status;
354 const struct hisi_qm_err_ini *err_ini;
355 struct hisi_qm_err_info err_info;
356 struct hisi_qm_err_status err_status;
357 /* driver removing and reset sched */
358 unsigned long misc_ctl;
359 /* Device capability bit */
360 unsigned long caps;
361
362 struct rw_semaphore qps_lock;
363 struct idr qp_idr;
364 struct hisi_qp *qp_array;
365 struct hisi_qm_poll_data *poll_data;
366
367 struct mutex mailbox_lock;
368
369 const struct hisi_qm_hw_ops *ops;
370
371 struct qm_debug debug;
372
373 u32 error_mask;
374
375 struct workqueue_struct *wq;
376 struct work_struct rst_work;
377 struct work_struct cmd_process;
378
379 bool use_sva;
380
381 resource_size_t phys_base;
382 resource_size_t db_phys_base;
383 struct uacce_device *uacce;
384 int mode;
385 struct qm_shaper_factor *factor;
386 u32 mb_qos;
387 u32 type_rate;
388 struct qm_err_isolate isolate_data;
389
390 struct hisi_qm_cap_tables cap_tables;
391 };
392
393 struct hisi_qp_status {
394 atomic_t used;
395 u16 sq_tail;
396 u16 cq_head;
397 bool cqc_phase;
398 atomic_t flags;
399 };
400
401 struct hisi_qp_ops {
402 int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm);
403 };
404
405 struct hisi_qp {
406 u32 qp_id;
407 u16 sq_depth;
408 u16 cq_depth;
409 u8 alg_type;
410 u8 req_type;
411
412 struct qm_dma qdma;
413 void *sqe;
414 struct qm_cqe *cqe;
415 dma_addr_t sqe_dma;
416 dma_addr_t cqe_dma;
417
418 struct hisi_qp_status qp_status;
419 struct hisi_qp_ops *hw_ops;
420 void *qp_ctx;
421 void (*req_cb)(struct hisi_qp *qp, void *data);
422 void (*event_cb)(struct hisi_qp *qp);
423
424 struct hisi_qm *qm;
425 bool is_resetting;
426 bool is_in_kernel;
427 u16 pasid;
428 struct uacce_queue *uacce_q;
429 };
430
q_num_set(const char * val,const struct kernel_param * kp,unsigned int device)431 static inline int q_num_set(const char *val, const struct kernel_param *kp,
432 unsigned int device)
433 {
434 struct pci_dev *pdev;
435 u32 n, q_num;
436 int ret;
437
438 if (!val)
439 return -EINVAL;
440
441 pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI, device, NULL);
442 if (!pdev) {
443 q_num = min_t(u32, QM_QNUM_V1, QM_QNUM_V2);
444 pr_info("No device found currently, suppose queue number is %u\n",
445 q_num);
446 } else {
447 if (pdev->revision == QM_HW_V1)
448 q_num = QM_QNUM_V1;
449 else
450 q_num = QM_QNUM_V2;
451
452 pci_dev_put(pdev);
453 }
454
455 ret = kstrtou32(val, 10, &n);
456 if (ret || n < QM_MIN_QNUM || n > q_num)
457 return -EINVAL;
458
459 return param_set_int(val, kp);
460 }
461
vfs_num_set(const char * val,const struct kernel_param * kp)462 static inline int vfs_num_set(const char *val, const struct kernel_param *kp)
463 {
464 u32 n;
465 int ret;
466
467 if (!val)
468 return -EINVAL;
469
470 ret = kstrtou32(val, 10, &n);
471 if (ret < 0)
472 return ret;
473
474 if (n > QM_MAX_VFS_NUM_V2)
475 return -EINVAL;
476
477 return param_set_int(val, kp);
478 }
479
mode_set(const char * val,const struct kernel_param * kp)480 static inline int mode_set(const char *val, const struct kernel_param *kp)
481 {
482 u32 n;
483 int ret;
484
485 if (!val)
486 return -EINVAL;
487
488 ret = kstrtou32(val, 10, &n);
489 if (ret != 0 || (n != UACCE_MODE_SVA &&
490 n != UACCE_MODE_NOUACCE))
491 return -EINVAL;
492
493 return param_set_int(val, kp);
494 }
495
uacce_mode_set(const char * val,const struct kernel_param * kp)496 static inline int uacce_mode_set(const char *val, const struct kernel_param *kp)
497 {
498 return mode_set(val, kp);
499 }
500
hisi_qm_init_list(struct hisi_qm_list * qm_list)501 static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
502 {
503 INIT_LIST_HEAD(&qm_list->list);
504 mutex_init(&qm_list->lock);
505 }
506
hisi_qm_add_list(struct hisi_qm * qm,struct hisi_qm_list * qm_list)507 static inline void hisi_qm_add_list(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
508 {
509 mutex_lock(&qm_list->lock);
510 list_add_tail(&qm->list, &qm_list->list);
511 mutex_unlock(&qm_list->lock);
512 }
513
hisi_qm_del_list(struct hisi_qm * qm,struct hisi_qm_list * qm_list)514 static inline void hisi_qm_del_list(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
515 {
516 mutex_lock(&qm_list->lock);
517 list_del(&qm->list);
518 mutex_unlock(&qm_list->lock);
519 }
520
521 int hisi_qm_init(struct hisi_qm *qm);
522 void hisi_qm_uninit(struct hisi_qm *qm);
523 int hisi_qm_start(struct hisi_qm *qm);
524 int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);
525 int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
526 int hisi_qm_stop_qp(struct hisi_qp *qp);
527 int hisi_qp_send(struct hisi_qp *qp, const void *msg);
528 void hisi_qm_debug_init(struct hisi_qm *qm);
529 void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
530 int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs);
531 int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen);
532 int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs);
533 void hisi_qm_dev_err_init(struct hisi_qm *qm);
534 void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
535 int hisi_qm_regs_debugfs_init(struct hisi_qm *qm,
536 struct dfx_diff_registers *dregs, u32 reg_len);
537 void hisi_qm_regs_debugfs_uninit(struct hisi_qm *qm, u32 reg_len);
538 void hisi_qm_acc_diff_regs_dump(struct hisi_qm *qm, struct seq_file *s,
539 struct dfx_diff_registers *dregs, u32 regs_len);
540
541 pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
542 pci_channel_state_t state);
543 pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
544 void hisi_qm_reset_prepare(struct pci_dev *pdev);
545 void hisi_qm_reset_done(struct pci_dev *pdev);
546
547 int hisi_qm_wait_mb_ready(struct hisi_qm *qm);
548 int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
549 bool op);
550
551 struct hisi_acc_sgl_pool;
552 struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
553 struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,
554 u32 index, dma_addr_t *hw_sgl_dma);
555 void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
556 struct hisi_acc_hw_sgl *hw_sgl);
557 struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
558 u32 count, u32 sge_nr);
559 void hisi_acc_free_sgl_pool(struct device *dev,
560 struct hisi_acc_sgl_pool *pool);
561 int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
562 u8 alg_type, int node, struct hisi_qp **qps);
563 void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
564 void hisi_qm_dev_shutdown(struct pci_dev *pdev);
565 void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
566 int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard);
567 void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard);
568 int hisi_qm_resume(struct device *dev);
569 int hisi_qm_suspend(struct device *dev);
570 void hisi_qm_pm_uninit(struct hisi_qm *qm);
571 void hisi_qm_pm_init(struct hisi_qm *qm);
572 int hisi_qm_get_dfx_access(struct hisi_qm *qm);
573 void hisi_qm_put_dfx_access(struct hisi_qm *qm);
574 void hisi_qm_regs_dump(struct seq_file *s, struct debugfs_regset32 *regset);
575 u32 hisi_qm_get_hw_info(struct hisi_qm *qm,
576 const struct hisi_qm_cap_info *info_table,
577 u32 index, bool is_read);
578 int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs,
579 u32 dev_algs_size);
580
581 /* Used by VFIO ACC live migration driver */
582 struct pci_driver *hisi_sec_get_pf_driver(void);
583 struct pci_driver *hisi_hpre_get_pf_driver(void);
584 struct pci_driver *hisi_zip_get_pf_driver(void);
585 #endif
586