1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de> 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/input.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/pwm/pwm.h> 10#include <dt-bindings/sound/fsl-imx-audmux.h> 11 12/ { 13 aliases { 14 can0 = &can2; 15 can1 = &can1; 16 ethernet0 = &fec; 17 lcdif-23bit-pins-a = &pinctrl_disp0_1; 18 lcdif-24bit-pins-a = &pinctrl_disp0_2; 19 pwm0 = &pwm1; 20 pwm1 = &pwm2; 21 reg-can-xcvr = ®_can_xcvr; 22 stk5led = &user_led; 23 usbotg = &usbotg; 24 sdhc0 = &usdhc1; 25 sdhc1 = &usdhc2; 26 }; 27 28 memory@10000000 { 29 device_type = "memory"; 30 reg = <0x10000000 0>; /* will be filled by U-Boot */ 31 }; 32 33 clocks { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 mclk: clock { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <26000000>; 41 }; 42 }; 43 44 gpio-keys { 45 compatible = "gpio-keys"; 46 47 power { 48 label = "Power Button"; 49 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; 50 linux,code = <KEY_POWER>; 51 wakeup-source; 52 }; 53 }; 54 55 leds { 56 compatible = "gpio-leds"; 57 58 user_led: led-user { 59 label = "Heartbeat"; 60 pinctrl-names = "default"; 61 pinctrl-0 = <&pinctrl_user_led>; 62 gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; 63 linux,default-trigger = "heartbeat"; 64 }; 65 }; 66 67 reg_3v3_etn: regulator-3v3-etn { 68 compatible = "regulator-fixed"; 69 regulator-name = "3V3_ETN"; 70 regulator-min-microvolt = <3300000>; 71 regulator-max-microvolt = <3300000>; 72 pinctrl-names = "default"; 73 pinctrl-0 = <&pinctrl_etnphy_power>; 74 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; 75 enable-active-high; 76 }; 77 78 reg_2v5: regulator-2v5 { 79 compatible = "regulator-fixed"; 80 regulator-name = "2V5"; 81 regulator-min-microvolt = <2500000>; 82 regulator-max-microvolt = <2500000>; 83 regulator-always-on; 84 }; 85 86 reg_3v3: regulator-3v3 { 87 compatible = "regulator-fixed"; 88 regulator-name = "3V3"; 89 regulator-min-microvolt = <3300000>; 90 regulator-max-microvolt = <3300000>; 91 regulator-always-on; 92 }; 93 94 reg_can_xcvr: regulator-can-xcvr { 95 compatible = "regulator-fixed"; 96 regulator-name = "CAN XCVR"; 97 regulator-min-microvolt = <3300000>; 98 regulator-max-microvolt = <3300000>; 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_flexcan_xcvr>; 101 gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; 102 }; 103 104 reg_lcd0_pwr: regulator-lcd0-pwr { 105 compatible = "regulator-fixed"; 106 regulator-name = "LCD0 POWER"; 107 regulator-min-microvolt = <3300000>; 108 regulator-max-microvolt = <3300000>; 109 pinctrl-names = "default"; 110 pinctrl-0 = <&pinctrl_lcd0_pwr>; 111 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; 112 enable-active-high; 113 status = "disabled"; 114 }; 115 116 reg_lcd1_pwr: regulator-lcd1-pwr { 117 compatible = "regulator-fixed"; 118 regulator-name = "LCD1 POWER"; 119 regulator-min-microvolt = <3300000>; 120 regulator-max-microvolt = <3300000>; 121 pinctrl-names = "default"; 122 pinctrl-0 = <&pinctrl_lcd1_pwr>; 123 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; 124 enable-active-high; 125 status = "disabled"; 126 }; 127 128 reg_usbh1_vbus: regulator-usbh1-vbus { 129 compatible = "regulator-fixed"; 130 regulator-name = "usbh1_vbus"; 131 regulator-min-microvolt = <5000000>; 132 regulator-max-microvolt = <5000000>; 133 pinctrl-names = "default"; 134 pinctrl-0 = <&pinctrl_usbh1_vbus>; 135 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; 136 enable-active-high; 137 }; 138 139 reg_usbotg_vbus: regulator-usbotg-vbus { 140 compatible = "regulator-fixed"; 141 regulator-name = "usbotg_vbus"; 142 regulator-min-microvolt = <5000000>; 143 regulator-max-microvolt = <5000000>; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pinctrl_usbotg_vbus>; 146 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 147 enable-active-high; 148 }; 149 150 sound { 151 compatible = "karo,imx6qdl-tx6-sgtl5000", 152 "simple-audio-card"; 153 simple-audio-card,name = "imx6qdl-tx6-sgtl5000-audio"; 154 pinctrl-names = "default"; 155 pinctrl-0 = <&pinctrl_audmux>; 156 simple-audio-card,format = "i2s"; 157 simple-audio-card,bitclock-master = <&codec_dai>; 158 simple-audio-card,frame-master = <&codec_dai>; 159 simple-audio-card,widgets = 160 "Microphone", "Mic Jack", 161 "Line", "Line In", 162 "Line", "Line Out", 163 "Headphone", "Headphone Jack"; 164 simple-audio-card,routing = 165 "MIC_IN", "Mic Jack", 166 "Mic Jack", "Mic Bias", 167 "Headphone Jack", "HP_OUT"; 168 169 cpu_dai: simple-audio-card,cpu { 170 sound-dai = <&ssi1>; 171 }; 172 173 codec_dai: simple-audio-card,codec { 174 sound-dai = <&sgtl5000>; 175 }; 176 }; 177}; 178 179&audmux { 180 status = "okay"; 181 182 mux-ssi1 { 183 fsl,audmux-port = <0>; 184 fsl,port-config = < 185 (IMX_AUDMUX_V2_PTCR_SYN | 186 IMX_AUDMUX_V2_PTCR_TFSEL(4) | 187 IMX_AUDMUX_V2_PTCR_TCSEL(4) | 188 IMX_AUDMUX_V2_PTCR_TFSDIR | 189 IMX_AUDMUX_V2_PTCR_TCLKDIR) 190 IMX_AUDMUX_V2_PDCR_RXDSEL(4) 191 >; 192 }; 193 194 mux-pins5 { 195 fsl,audmux-port = <4>; 196 fsl,port-config = < 197 IMX_AUDMUX_V2_PTCR_SYN 198 IMX_AUDMUX_V2_PDCR_RXDSEL(0) 199 >; 200 }; 201}; 202 203&can1 { 204 pinctrl-names = "default"; 205 pinctrl-0 = <&pinctrl_flexcan1>; 206 xceiver-supply = <®_can_xcvr>; 207 status = "okay"; 208}; 209 210&can2 { 211 pinctrl-names = "default"; 212 pinctrl-0 = <&pinctrl_flexcan2>; 213 xceiver-supply = <®_can_xcvr>; 214 status = "okay"; 215}; 216 217&ecspi1 { 218 pinctrl-names = "default"; 219 pinctrl-0 = <&pinctrl_ecspi1>; 220 cs-gpios = < 221 &gpio2 30 GPIO_ACTIVE_HIGH 222 &gpio3 19 GPIO_ACTIVE_HIGH 223 >; 224 status = "disabled"; 225}; 226 227&fec { 228 pinctrl-names = "default"; 229 pinctrl-0 = <&pinctrl_enet &pinctrl_enet_mdio &pinctrl_etnphy_rst>; 230 phy-mode = "rmii"; 231 phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; 232 phy-reset-post-delay = <10>; 233 phy-handle = <&etnphy>; 234 phy-supply = <®_3v3_etn>; 235 status = "okay"; 236 237 mdio { 238 #address-cells = <1>; 239 #size-cells = <0>; 240 241 etnphy: ethernet-phy@0 { 242 compatible = "ethernet-phy-ieee802.3-c22"; 243 reg = <0>; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&pinctrl_etnphy_int>; 246 interrupt-parent = <&gpio7>; 247 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 248 }; 249 }; 250}; 251 252&gpmi { 253 pinctrl-names = "default"; 254 pinctrl-0 = <&pinctrl_gpmi_nand>; 255 nand-on-flash-bbt; 256 fsl,no-blockmark-swap; 257 status = "okay"; 258}; 259 260&i2c1 { 261 pinctrl-names = "default", "gpio"; 262 pinctrl-0 = <&pinctrl_i2c1>; 263 pinctrl-1 = <&pinctrl_i2c1_gpio>; 264 scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; 265 sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; 266 clock-frequency = <400000>; 267 status = "okay"; 268 269 ds1339: rtc@68 { 270 compatible = "dallas,ds1339"; 271 reg = <0x68>; 272 trickle-resistor-ohms = <250>; 273 trickle-diode-disable; 274 }; 275}; 276 277&i2c3 { 278 pinctrl-names = "default", "gpio"; 279 pinctrl-0 = <&pinctrl_i2c3>; 280 pinctrl-1 = <&pinctrl_i2c3_gpio>; 281 scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 282 sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 283 clock-frequency = <400000>; 284 status = "okay"; 285 286 sgtl5000: sgtl5000@a { 287 compatible = "fsl,sgtl5000"; 288 #sound-dai-cells = <0>; 289 reg = <0x0a>; 290 VDDA-supply = <®_2v5>; 291 VDDIO-supply = <®_3v3>; 292 clocks = <&mclk>; 293 }; 294 295 polytouch: edt-ft5x06@38 { 296 compatible = "edt,edt-ft5x06"; 297 reg = <0x38>; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&pinctrl_edt_ft5x06>; 300 interrupt-parent = <&gpio6>; 301 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 302 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; 303 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; 304 wakeup-source; 305 }; 306 307 touchscreen: tsc2007@48 { 308 compatible = "ti,tsc2007"; 309 reg = <0x48>; 310 pinctrl-names = "default"; 311 pinctrl-0 = <&pinctrl_tsc2007>; 312 interrupt-parent = <&gpio3>; 313 interrupts = <26 0>; 314 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; 315 ti,x-plate-ohms = <660>; 316 wakeup-source; 317 }; 318}; 319 320&iomuxc { 321 pinctrl-names = "default"; 322 pinctrl-0 = <&pinctrl_hog>; 323 324 pinctrl_hog: hoggrp { 325 fsl,pins = < 326 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */ 327 >; 328 }; 329 330 pinctrl_audmux: audmuxgrp { 331 fsl,pins = < 332 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */ 333 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */ 334 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */ 335 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */ 336 >; 337 }; 338 339 pinctrl_disp0_1: disp0-1-grp { 340 fsl,pins = < 341 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 342 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 343 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 344 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 345 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */ 346 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 347 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 348 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 349 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 350 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 351 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 352 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 353 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 354 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 355 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 356 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 357 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 358 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 359 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 360 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 361 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 362 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 363 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 364 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 365 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 366 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 367 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 368 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 369 >; 370 }; 371 372 pinctrl_disp0_2: disp0-2-grp { 373 fsl,pins = < 374 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 375 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 376 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 377 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 378 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 379 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 380 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 381 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 382 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 383 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 384 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 385 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 386 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 387 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 388 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 389 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 390 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 391 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 392 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 393 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 394 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 395 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 396 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 397 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 398 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 399 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 400 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 401 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 402 >; 403 }; 404 405 pinctrl_ecspi1: ecspi1grp { 406 fsl,pins = < 407 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0 408 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0 409 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0 410 MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0 411 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */ 412 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */ 413 >; 414 }; 415 416 pinctrl_edt_ft5x06: edt-ft5x06grp { 417 fsl,pins = < 418 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */ 419 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */ 420 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */ 421 >; 422 }; 423 424 pinctrl_enet: enetgrp { 425 fsl,pins = < 426 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 427 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 428 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 429 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 430 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 431 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 432 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 433 >; 434 }; 435 436 pinctrl_enet_mdio: enet-mdiogrp { 437 fsl,pins = < 438 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 439 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 440 >; 441 }; 442 443 pinctrl_etnphy_int: etnphy-intgrp { 444 fsl,pins = < 445 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */ 446 >; 447 }; 448 449 pinctrl_etnphy_power: etnphy-pwrgrp { 450 fsl,pins = < 451 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */ 452 >; 453 }; 454 455 pinctrl_etnphy_rst: etnphy-rstgrp { 456 fsl,pins = < 457 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */ 458 >; 459 }; 460 461 pinctrl_flexcan1: flexcan1grp { 462 fsl,pins = < 463 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 464 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 465 >; 466 }; 467 468 pinctrl_flexcan2: flexcan2grp { 469 fsl,pins = < 470 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 471 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 472 >; 473 }; 474 475 pinctrl_flexcan_xcvr: flexcan-xcvrgrp { 476 fsl,pins = < 477 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */ 478 >; 479 }; 480 481 pinctrl_gpmi_nand: gpminandgrp { 482 fsl,pins = < 483 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 484 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 485 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 486 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 487 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 488 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 489 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 490 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 491 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 492 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 493 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 494 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 495 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 496 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 497 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 498 >; 499 }; 500 501 pinctrl_i2c1: i2c1grp { 502 fsl,pins = < 503 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 504 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 505 >; 506 }; 507 508 pinctrl_i2c1_gpio: i2c1-gpiogrp { 509 fsl,pins = < 510 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 511 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 512 >; 513 }; 514 515 pinctrl_i2c3: i2c3grp { 516 fsl,pins = < 517 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 518 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 519 >; 520 }; 521 522 pinctrl_i2c3_gpio: i2c3-gpiogrp { 523 fsl,pins = < 524 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 525 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 526 >; 527 }; 528 529 pinctrl_kpp: kppgrp { 530 fsl,pins = < 531 MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1 532 MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1 533 MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1 534 MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1 535 MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1 536 MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1 537 MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1 538 MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1 539 >; 540 }; 541 542 pinctrl_lcd0_pwr: lcd0-pwrgrp { 543 fsl,pins = < 544 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */ 545 >; 546 }; 547 548 pinctrl_lcd1_pwr: lcd-pwrgrp { 549 fsl,pins = < 550 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */ 551 >; 552 }; 553 554 pinctrl_pwm1: pwm1grp { 555 fsl,pins = < 556 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 557 >; 558 }; 559 560 pinctrl_pwm2: pwm2grp { 561 fsl,pins = < 562 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 563 >; 564 }; 565 566 pinctrl_tsc2007: tsc2007grp { 567 fsl,pins = < 568 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */ 569 >; 570 }; 571 572 pinctrl_uart1: uart1grp { 573 fsl,pins = < 574 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 575 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 576 >; 577 }; 578 579 pinctrl_uart1_rtscts: uart1_rtsctsgrp { 580 fsl,pins = < 581 MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1 582 MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1 583 >; 584 }; 585 586 pinctrl_uart2: uart2grp { 587 fsl,pins = < 588 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 589 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 590 >; 591 }; 592 593 pinctrl_uart2_rtscts: uart2_rtsctsgrp { 594 fsl,pins = < 595 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 596 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 597 >; 598 }; 599 600 pinctrl_uart3: uart3grp { 601 fsl,pins = < 602 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 603 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 604 >; 605 }; 606 607 pinctrl_uart3_rtscts: uart3_rtsctsgrp { 608 fsl,pins = < 609 MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1 610 MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1 611 >; 612 }; 613 614 pinctrl_usbh1_vbus: usbh1-vbusgrp { 615 fsl,pins = < 616 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */ 617 >; 618 }; 619 620 pinctrl_usbotg: usbotggrp { 621 fsl,pins = < 622 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059 623 >; 624 }; 625 626 pinctrl_usbotg_vbus: usbotg-vbusgrp { 627 fsl,pins = < 628 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */ 629 >; 630 }; 631 632 pinctrl_usdhc1: usdhc1grp { 633 fsl,pins = < 634 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1 635 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1 636 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1 637 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1 638 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1 639 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1 640 MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */ 641 >; 642 }; 643 644 pinctrl_usdhc2: usdhc2grp { 645 fsl,pins = < 646 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1 647 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1 648 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1 649 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1 650 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1 651 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1 652 MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */ 653 >; 654 }; 655 656 pinctrl_user_led: user-ledgrp { 657 fsl,pins = < 658 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */ 659 >; 660 }; 661}; 662 663&kpp { 664 pinctrl-names = "default"; 665 pinctrl-0 = <&pinctrl_kpp>; 666 /* sample keymap */ 667 /* row/col 0,1 are mapped to KPP row/col 6,7 */ 668 linux,keymap = < 669 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */ 670 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */ 671 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */ 672 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */ 673 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */ 674 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */ 675 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */ 676 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */ 677 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */ 678 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */ 679 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */ 680 >; 681 status = "okay"; 682}; 683 684&pwm1 { 685 pinctrl-names = "default"; 686 pinctrl-0 = <&pinctrl_pwm1>; 687 status = "disabled"; 688}; 689 690&pwm2 { 691 pinctrl-names = "default"; 692 pinctrl-0 = <&pinctrl_pwm2>; 693 status = "okay"; 694}; 695 696&ssi1 { 697 status = "okay"; 698}; 699 700&uart1 { 701 pinctrl-names = "default"; 702 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>; 703 uart-has-rtscts; 704 status = "okay"; 705}; 706 707&uart2 { 708 pinctrl-names = "default"; 709 pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>; 710 uart-has-rtscts; 711 status = "okay"; 712}; 713 714&uart3 { 715 pinctrl-names = "default"; 716 pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>; 717 uart-has-rtscts; 718 status = "okay"; 719}; 720 721&usbh1 { 722 vbus-supply = <®_usbh1_vbus>; 723 dr_mode = "host"; 724 disable-over-current; 725 status = "okay"; 726}; 727 728&usbotg { 729 vbus-supply = <®_usbotg_vbus>; 730 pinctrl-names = "default"; 731 pinctrl-0 = <&pinctrl_usbotg>; 732 dr_mode = "peripheral"; 733 disable-over-current; 734 status = "okay"; 735}; 736 737&usdhc1 { 738 pinctrl-names = "default"; 739 pinctrl-0 = <&pinctrl_usdhc1>; 740 bus-width = <4>; 741 no-1-8-v; 742 cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; 743 fsl,wp-controller; 744 status = "okay"; 745}; 746 747&usdhc2 { 748 pinctrl-names = "default"; 749 pinctrl-0 = <&pinctrl_usdhc2>; 750 bus-width = <4>; 751 no-1-8-v; 752 cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; 753 fsl,wp-controller; 754 status = "okay"; 755}; 756