1 /*
2 * IGD device quirks
3 *
4 * Copyright Red Hat, Inc. 2016
5 *
6 * Authors:
7 * Alex Williamson <alex.williamson@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 */
12
13 #include "qemu/osdep.h"
14 #include "qemu/units.h"
15 #include "qemu/error-report.h"
16 #include "qapi/error.h"
17 #include "qapi/qmp/qerror.h"
18 #include "hw/boards.h"
19 #include "hw/hw.h"
20 #include "hw/nvram/fw_cfg.h"
21 #include "pci.h"
22 #include "pci-quirks.h"
23 #include "trace.h"
24
25 /*
26 * Intel IGD support
27 *
28 * Obviously IGD is not a discrete device, this is evidenced not only by it
29 * being integrated into the CPU, but by the various chipset and BIOS
30 * dependencies that it brings along with it. Intel is trying to move away
31 * from this and Broadwell and newer devices can run in what Intel calls
32 * "Universal Pass-Through" mode, or UPT. Theoretically in UPT mode, nothing
33 * more is required beyond assigning the IGD device to a VM. There are
34 * however support limitations to this mode. It only supports IGD as a
35 * secondary graphics device in the VM and it doesn't officially support any
36 * physical outputs.
37 *
38 * The code here attempts to enable what we'll call legacy mode assignment,
39 * IGD retains most of the capabilities we expect for it to have on bare
40 * metal. To enable this mode, the IGD device must be assigned to the VM
41 * at PCI address 00:02.0, it must have a ROM, it very likely needs VGA
42 * support, we must have VM BIOS support for reserving and populating some
43 * of the required tables, and we need to tweak the chipset with revisions
44 * and IDs and an LPC/ISA bridge device. The intention is to make all of
45 * this happen automatically by installing the device at the correct VM PCI
46 * bus address. If any of the conditions are not met, we cross our fingers
47 * and hope the user knows better.
48 *
49 * NB - It is possible to enable physical outputs in UPT mode by supplying
50 * an OpRegion table. We don't do this by default because the guest driver
51 * behaves differently if an OpRegion is provided and no monitor is attached
52 * vs no OpRegion and a monitor being attached or not. Effectively, if a
53 * headless setup is desired, the OpRegion gets in the way of that.
54 */
55
56 /*
57 * This presumes the device is already known to be an Intel VGA device, so we
58 * take liberties in which device ID bits match which generation. This should
59 * not be taken as an indication that all the devices are supported, or even
60 * supportable, some of them don't even support VT-d.
61 * See linux:include/drm/i915_pciids.h for IDs.
62 */
igd_gen(VFIOPCIDevice * vdev)63 static int igd_gen(VFIOPCIDevice *vdev)
64 {
65 /*
66 * Device IDs for Broxton/Apollo Lake are 0x0a84, 0x1a84, 0x1a85, 0x5a84
67 * and 0x5a85, match bit 11:1 here
68 * Prefix 0x0a is taken by Haswell, this rule should be matched first.
69 */
70 if ((vdev->device_id & 0xffe) == 0xa84) {
71 return 9;
72 }
73
74 switch (vdev->device_id & 0xff00) {
75 case 0x0100: /* SandyBridge, IvyBridge */
76 return 6;
77 case 0x0400: /* Haswell */
78 case 0x0a00: /* Haswell */
79 case 0x0c00: /* Haswell */
80 case 0x0d00: /* Haswell */
81 case 0x0f00: /* Valleyview/Bay Trail */
82 return 7;
83 case 0x1600: /* Broadwell */
84 case 0x2200: /* Cherryview */
85 return 8;
86 case 0x1900: /* Skylake */
87 case 0x3100: /* Gemini Lake */
88 case 0x5900: /* Kaby Lake */
89 case 0x3e00: /* Coffee Lake */
90 case 0x9B00: /* Comet Lake */
91 return 9;
92 case 0x8A00: /* Ice Lake */
93 case 0x4500: /* Elkhart Lake */
94 case 0x4E00: /* Jasper Lake */
95 return 11;
96 case 0x9A00: /* Tiger Lake */
97 case 0x4C00: /* Rocket Lake */
98 case 0x4600: /* Alder Lake */
99 case 0xA700: /* Raptor Lake */
100 return 12;
101 }
102
103 /*
104 * Unfortunately, Intel changes it's specification quite often. This makes
105 * it impossible to use a suitable default value for unknown devices.
106 * Return -1 for not applying any generation-specific quirks.
107 */
108 return -1;
109 }
110
111 #define IGD_ASLS 0xfc /* ASL Storage Register */
112 #define IGD_GMCH 0x50 /* Graphics Control Register */
113 #define IGD_BDSM 0x5c /* Base Data of Stolen Memory */
114 #define IGD_BDSM_GEN11 0xc0 /* Base Data of Stolen Memory of gen 11 and later */
115
116 #define IGD_GMCH_GEN6_GMS_SHIFT 3 /* SNB_GMCH in i915 */
117 #define IGD_GMCH_GEN6_GMS_MASK 0x1f
118 #define IGD_GMCH_GEN8_GMS_SHIFT 8 /* BDW_GMCH in i915 */
119 #define IGD_GMCH_GEN8_GMS_MASK 0xff
120
igd_stolen_memory_size(int gen,uint32_t gmch)121 static uint64_t igd_stolen_memory_size(int gen, uint32_t gmch)
122 {
123 uint64_t gms;
124
125 if (gen < 8) {
126 gms = (gmch >> IGD_GMCH_GEN6_GMS_SHIFT) & IGD_GMCH_GEN6_GMS_MASK;
127 } else {
128 gms = (gmch >> IGD_GMCH_GEN8_GMS_SHIFT) & IGD_GMCH_GEN8_GMS_MASK;
129 }
130
131 if (gen < 9) {
132 return gms * 32 * MiB;
133 } else {
134 if (gms < 0xf0) {
135 return gms * 32 * MiB;
136 } else {
137 return (gms - 0xf0 + 1) * 4 * MiB;
138 }
139 }
140
141 return 0;
142 }
143
144 /*
145 * The OpRegion includes the Video BIOS Table, which seems important for
146 * telling the driver what sort of outputs it has. Without this, the device
147 * may work in the guest, but we may not get output. This also requires BIOS
148 * support to reserve and populate a section of guest memory sufficient for
149 * the table and to write the base address of that memory to the ASLS register
150 * of the IGD device.
151 */
vfio_pci_igd_opregion_init(VFIOPCIDevice * vdev,struct vfio_region_info * info,Error ** errp)152 static bool vfio_pci_igd_opregion_init(VFIOPCIDevice *vdev,
153 struct vfio_region_info *info,
154 Error **errp)
155 {
156 int ret;
157
158 vdev->igd_opregion = g_malloc0(info->size);
159 ret = pread(vdev->vbasedev.fd, vdev->igd_opregion,
160 info->size, info->offset);
161 if (ret != info->size) {
162 error_setg(errp, "failed to read IGD OpRegion");
163 g_free(vdev->igd_opregion);
164 vdev->igd_opregion = NULL;
165 return false;
166 }
167
168 /*
169 * Provide fw_cfg with a copy of the OpRegion which the VM firmware is to
170 * allocate 32bit reserved memory for, copy these contents into, and write
171 * the reserved memory base address to the device ASLS register at 0xFC.
172 * Alignment of this reserved region seems flexible, but using a 4k page
173 * alignment seems to work well. This interface assumes a single IGD
174 * device, which may be at VM address 00:02.0 in legacy mode or another
175 * address in UPT mode.
176 *
177 * NB, there may be future use cases discovered where the VM should have
178 * direct interaction with the host OpRegion, in which case the write to
179 * the ASLS register would trigger MemoryRegion setup to enable that.
180 */
181 fw_cfg_add_file(fw_cfg_find(), "etc/igd-opregion",
182 vdev->igd_opregion, info->size);
183
184 trace_vfio_pci_igd_opregion_enabled(vdev->vbasedev.name);
185
186 return true;
187 }
188
vfio_pci_igd_opregion_detect(VFIOPCIDevice * vdev,struct vfio_region_info ** opregion)189 static bool vfio_pci_igd_opregion_detect(VFIOPCIDevice *vdev,
190 struct vfio_region_info **opregion)
191 {
192 int ret;
193
194 ret = vfio_device_get_region_info_type(&vdev->vbasedev,
195 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL,
196 VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, opregion);
197 if (ret) {
198 return false;
199 }
200
201 /* Hotplugging is not supported for opregion access */
202 if (vdev->pdev.qdev.hotplugged) {
203 warn_report("IGD device detected, but OpRegion is not supported "
204 "on hotplugged device.");
205 return false;
206 }
207
208 return true;
209 }
210
211 /*
212 * The rather short list of registers that we copy from the host devices.
213 * The LPC/ISA bridge values are definitely needed to support the vBIOS, the
214 * host bridge values may or may not be needed depending on the guest OS.
215 * Since we're only munging revision and subsystem values on the host bridge,
216 * we don't require our own device. The LPC/ISA bridge needs to be our very
217 * own though.
218 */
219 typedef struct {
220 uint8_t offset;
221 uint8_t len;
222 } IGDHostInfo;
223
224 static const IGDHostInfo igd_host_bridge_infos[] = {
225 {PCI_REVISION_ID, 2},
226 {PCI_SUBSYSTEM_VENDOR_ID, 2},
227 {PCI_SUBSYSTEM_ID, 2},
228 };
229
230 static const IGDHostInfo igd_lpc_bridge_infos[] = {
231 {PCI_VENDOR_ID, 2},
232 {PCI_DEVICE_ID, 2},
233 {PCI_REVISION_ID, 2},
234 {PCI_SUBSYSTEM_VENDOR_ID, 2},
235 {PCI_SUBSYSTEM_ID, 2},
236 };
237
vfio_pci_igd_copy(VFIOPCIDevice * vdev,PCIDevice * pdev,struct vfio_region_info * info,const IGDHostInfo * list,int len)238 static int vfio_pci_igd_copy(VFIOPCIDevice *vdev, PCIDevice *pdev,
239 struct vfio_region_info *info,
240 const IGDHostInfo *list, int len)
241 {
242 int i, ret;
243
244 for (i = 0; i < len; i++) {
245 ret = pread(vdev->vbasedev.fd, pdev->config + list[i].offset,
246 list[i].len, info->offset + list[i].offset);
247 if (ret != list[i].len) {
248 error_report("IGD copy failed: %m");
249 return -errno;
250 }
251 }
252
253 return 0;
254 }
255
256 /*
257 * Stuff a few values into the host bridge.
258 */
vfio_pci_igd_host_init(VFIOPCIDevice * vdev,struct vfio_region_info * info)259 static int vfio_pci_igd_host_init(VFIOPCIDevice *vdev,
260 struct vfio_region_info *info)
261 {
262 PCIBus *bus;
263 PCIDevice *host_bridge;
264 int ret;
265
266 bus = pci_device_root_bus(&vdev->pdev);
267 host_bridge = pci_find_device(bus, 0, PCI_DEVFN(0, 0));
268
269 if (!host_bridge) {
270 error_report("Can't find host bridge");
271 return -ENODEV;
272 }
273
274 ret = vfio_pci_igd_copy(vdev, host_bridge, info, igd_host_bridge_infos,
275 ARRAY_SIZE(igd_host_bridge_infos));
276 if (!ret) {
277 trace_vfio_pci_igd_host_bridge_enabled(vdev->vbasedev.name);
278 }
279
280 return ret;
281 }
282
283 /*
284 * IGD LPC/ISA bridge support code. The vBIOS needs this, but we can't write
285 * arbitrary values into just any bridge, so we must create our own. We try
286 * to handle if the user has created it for us, which they might want to do
287 * to enable multifunction so we don't occupy the whole PCI slot.
288 */
vfio_pci_igd_lpc_bridge_realize(PCIDevice * pdev,Error ** errp)289 static void vfio_pci_igd_lpc_bridge_realize(PCIDevice *pdev, Error **errp)
290 {
291 if (pdev->devfn != PCI_DEVFN(0x1f, 0)) {
292 error_setg(errp, "VFIO dummy ISA/LPC bridge must have address 1f.0");
293 }
294 }
295
vfio_pci_igd_lpc_bridge_class_init(ObjectClass * klass,const void * data)296 static void vfio_pci_igd_lpc_bridge_class_init(ObjectClass *klass,
297 const void *data)
298 {
299 DeviceClass *dc = DEVICE_CLASS(klass);
300 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
301
302 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
303 dc->desc = "VFIO dummy ISA/LPC bridge for IGD assignment";
304 dc->hotpluggable = false;
305 k->realize = vfio_pci_igd_lpc_bridge_realize;
306 k->class_id = PCI_CLASS_BRIDGE_ISA;
307 }
308
309 static const TypeInfo vfio_pci_igd_lpc_bridge_info = {
310 .name = "vfio-pci-igd-lpc-bridge",
311 .parent = TYPE_PCI_DEVICE,
312 .class_init = vfio_pci_igd_lpc_bridge_class_init,
313 .interfaces = (const InterfaceInfo[]) {
314 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
315 { },
316 },
317 };
318
vfio_pci_igd_register_types(void)319 static void vfio_pci_igd_register_types(void)
320 {
321 type_register_static(&vfio_pci_igd_lpc_bridge_info);
322 }
323
type_init(vfio_pci_igd_register_types)324 type_init(vfio_pci_igd_register_types)
325
326 static int vfio_pci_igd_lpc_init(VFIOPCIDevice *vdev,
327 struct vfio_region_info *info)
328 {
329 PCIDevice *lpc_bridge;
330 int ret;
331
332 lpc_bridge = pci_find_device(pci_device_root_bus(&vdev->pdev),
333 0, PCI_DEVFN(0x1f, 0));
334 if (!lpc_bridge) {
335 lpc_bridge = pci_create_simple(pci_device_root_bus(&vdev->pdev),
336 PCI_DEVFN(0x1f, 0), "vfio-pci-igd-lpc-bridge");
337 }
338
339 ret = vfio_pci_igd_copy(vdev, lpc_bridge, info, igd_lpc_bridge_infos,
340 ARRAY_SIZE(igd_lpc_bridge_infos));
341 if (!ret) {
342 trace_vfio_pci_igd_lpc_bridge_enabled(vdev->vbasedev.name);
343 }
344
345 return ret;
346 }
347
vfio_pci_igd_setup_lpc_bridge(VFIOPCIDevice * vdev,Error ** errp)348 static bool vfio_pci_igd_setup_lpc_bridge(VFIOPCIDevice *vdev, Error **errp)
349 {
350 struct vfio_region_info *host = NULL;
351 struct vfio_region_info *lpc = NULL;
352 PCIDevice *lpc_bridge;
353 int ret;
354
355 /*
356 * Copying IDs or creating new devices are not supported on hotplug
357 */
358 if (vdev->pdev.qdev.hotplugged) {
359 error_setg(errp, "IGD LPC is not supported on hotplugged device");
360 return false;
361 }
362
363 /*
364 * We need to create an LPC/ISA bridge at PCI bus address 00:1f.0 that we
365 * can stuff host values into, so if there's already one there and it's not
366 * one we can hack on, this quirk is no-go. Sorry Q35.
367 */
368 lpc_bridge = pci_find_device(pci_device_root_bus(&vdev->pdev),
369 0, PCI_DEVFN(0x1f, 0));
370 if (lpc_bridge && !object_dynamic_cast(OBJECT(lpc_bridge),
371 "vfio-pci-igd-lpc-bridge")) {
372 error_setg(errp,
373 "Cannot create LPC bridge due to existing device at 1f.0");
374 return false;
375 }
376
377 /*
378 * Check whether we have all the vfio device specific regions to
379 * support LPC quirk (added in Linux v4.6).
380 */
381 ret = vfio_device_get_region_info_type(&vdev->vbasedev,
382 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL,
383 VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG, &lpc);
384 if (ret) {
385 error_setg(errp, "IGD LPC bridge access is not supported by kernel");
386 return false;
387 }
388
389 ret = vfio_device_get_region_info_type(&vdev->vbasedev,
390 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL,
391 VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG, &host);
392 if (ret) {
393 error_setg(errp, "IGD host bridge access is not supported by kernel");
394 return false;
395 }
396
397 /* Create/modify LPC bridge */
398 ret = vfio_pci_igd_lpc_init(vdev, lpc);
399 if (ret) {
400 error_setg(errp, "Failed to create/modify LPC bridge for IGD");
401 return false;
402 }
403
404 /* Stuff some host values into the VM PCI host bridge */
405 ret = vfio_pci_igd_host_init(vdev, host);
406 if (ret) {
407 error_setg(errp, "Failed to modify host bridge for IGD");
408 return false;
409 }
410
411 return true;
412 }
413
vfio_pci_igd_override_gms(int gen,uint32_t gms,uint32_t * gmch)414 static bool vfio_pci_igd_override_gms(int gen, uint32_t gms, uint32_t *gmch)
415 {
416 bool ret = false;
417
418 if (gen == -1) {
419 error_report("x-igd-gms is not supported on this device");
420 } else if (gen < 8) {
421 if (gms <= 0x10) {
422 *gmch &= ~(IGD_GMCH_GEN6_GMS_MASK << IGD_GMCH_GEN6_GMS_SHIFT);
423 *gmch |= gms << IGD_GMCH_GEN6_GMS_SHIFT;
424 ret = true;
425 } else {
426 error_report(QERR_INVALID_PARAMETER_VALUE, "x-igd-gms", "0~0x10");
427 }
428 } else if (gen == 8) {
429 if (gms <= 0x40) {
430 *gmch &= ~(IGD_GMCH_GEN8_GMS_MASK << IGD_GMCH_GEN8_GMS_SHIFT);
431 *gmch |= gms << IGD_GMCH_GEN8_GMS_SHIFT;
432 ret = true;
433 } else {
434 error_report(QERR_INVALID_PARAMETER_VALUE, "x-igd-gms", "0~0x40");
435 }
436 } else {
437 /* 0x0 to 0x40: 32MB increments starting at 0MB */
438 /* 0xf0 to 0xfe: 4MB increments starting at 4MB */
439 if ((gms <= 0x40) || (gms >= 0xf0 && gms <= 0xfe)) {
440 *gmch &= ~(IGD_GMCH_GEN8_GMS_MASK << IGD_GMCH_GEN8_GMS_SHIFT);
441 *gmch |= gms << IGD_GMCH_GEN8_GMS_SHIFT;
442 ret = true;
443 } else {
444 error_report(QERR_INVALID_PARAMETER_VALUE,
445 "x-igd-gms", "0~0x40 or 0xf0~0xfe");
446 }
447 }
448
449 return ret;
450 }
451
452 #define IGD_GGC_MMIO_OFFSET 0x108040
453 #define IGD_BDSM_MMIO_OFFSET 0x1080C0
454
vfio_probe_igd_bar0_quirk(VFIOPCIDevice * vdev,int nr)455 void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, int nr)
456 {
457 VFIOQuirk *ggc_quirk, *bdsm_quirk;
458 VFIOConfigMirrorQuirk *ggc_mirror, *bdsm_mirror;
459 int gen;
460
461 if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) ||
462 !vfio_is_vga(vdev) || nr != 0) {
463 return;
464 }
465
466 /* Only on IGD Gen6-12 device needs quirks in BAR 0 */
467 gen = igd_gen(vdev);
468 if (gen < 6) {
469 return;
470 }
471
472 if (vdev->igd_gms) {
473 ggc_quirk = vfio_quirk_alloc(1);
474 ggc_mirror = ggc_quirk->data = g_malloc0(sizeof(*ggc_mirror));
475 ggc_mirror->mem = ggc_quirk->mem;
476 ggc_mirror->vdev = vdev;
477 ggc_mirror->bar = nr;
478 ggc_mirror->offset = IGD_GGC_MMIO_OFFSET;
479 ggc_mirror->config_offset = IGD_GMCH;
480
481 memory_region_init_io(ggc_mirror->mem, OBJECT(vdev),
482 &vfio_generic_mirror_quirk, ggc_mirror,
483 "vfio-igd-ggc-quirk", 2);
484 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem,
485 ggc_mirror->offset, ggc_mirror->mem,
486 1);
487
488 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, ggc_quirk, next);
489 }
490
491 bdsm_quirk = vfio_quirk_alloc(1);
492 bdsm_mirror = bdsm_quirk->data = g_malloc0(sizeof(*bdsm_mirror));
493 bdsm_mirror->mem = bdsm_quirk->mem;
494 bdsm_mirror->vdev = vdev;
495 bdsm_mirror->bar = nr;
496 bdsm_mirror->offset = IGD_BDSM_MMIO_OFFSET;
497 bdsm_mirror->config_offset = (gen < 11) ? IGD_BDSM : IGD_BDSM_GEN11;
498
499 memory_region_init_io(bdsm_mirror->mem, OBJECT(vdev),
500 &vfio_generic_mirror_quirk, bdsm_mirror,
501 "vfio-igd-bdsm-quirk", (gen < 11) ? 4 : 8);
502 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem,
503 bdsm_mirror->offset, bdsm_mirror->mem,
504 1);
505
506 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, bdsm_quirk, next);
507 }
508
vfio_pci_igd_config_quirk(VFIOPCIDevice * vdev,Error ** errp)509 static bool vfio_pci_igd_config_quirk(VFIOPCIDevice *vdev, Error **errp)
510 {
511 struct vfio_region_info *opregion = NULL;
512 int ret, gen;
513 uint64_t gms_size = 0;
514 uint64_t *bdsm_size;
515 uint32_t gmch;
516 bool legacy_mode_enabled = false;
517 Error *err = NULL;
518
519 if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) ||
520 !vfio_is_vga(vdev)) {
521 return true;
522 }
523
524 /* IGD device always comes with OpRegion */
525 if (!vfio_pci_igd_opregion_detect(vdev, &opregion)) {
526 return true;
527 }
528 info_report("OpRegion detected on Intel display %x.", vdev->device_id);
529
530 gen = igd_gen(vdev);
531 gmch = vfio_pci_read_config(&vdev->pdev, IGD_GMCH, 4);
532
533 /*
534 * For backward compatibility, enable legacy mode when
535 * - Device geneation is 6 to 9 (including both)
536 * - Machine type is i440fx (pc_piix)
537 * - IGD device is at guest BDF 00:02.0
538 * - Not manually disabled by x-igd-legacy-mode=off
539 */
540 if ((vdev->igd_legacy_mode != ON_OFF_AUTO_OFF) &&
541 (gen >= 6 && gen <= 9) &&
542 !strcmp(MACHINE_GET_CLASS(qdev_get_machine())->family, "pc_piix") &&
543 (&vdev->pdev == pci_find_device(pci_device_root_bus(&vdev->pdev),
544 0, PCI_DEVFN(0x2, 0)))) {
545 /*
546 * IGD legacy mode requires:
547 * - VBIOS in ROM BAR or file
548 * - VGA IO/MMIO ranges are claimed by IGD
549 * - OpRegion
550 * - Same LPC bridge and Host bridge VID/DID/SVID/SSID as host
551 */
552 struct vfio_region_info *rom = NULL;
553
554 legacy_mode_enabled = true;
555 info_report("IGD legacy mode enabled, "
556 "use x-igd-legacy-mode=off to disable it if unwanted.");
557
558 /*
559 * Most of what we're doing here is to enable the ROM to run, so if
560 * there's no ROM, there's no point in setting up this quirk.
561 * NB. We only seem to get BIOS ROMs, so UEFI VM would need CSM support.
562 */
563 ret = vfio_device_get_region_info(&vdev->vbasedev,
564 VFIO_PCI_ROM_REGION_INDEX, &rom);
565 if ((ret || !rom->size) && !vdev->pdev.romfile) {
566 error_setg(&err, "Device has no ROM");
567 goto error;
568 }
569
570 /*
571 * If IGD VGA Disable is clear (expected) and VGA is not already
572 * enabled, try to enable it. Probably shouldn't be using legacy mode
573 * without VGA, but also no point in us enabling VGA if disabled in
574 * hardware.
575 */
576 if (!(gmch & 0x2) && !vdev->vga && !vfio_populate_vga(vdev, &err)) {
577 error_setg(&err, "Unable to enable VGA access");
578 goto error;
579 }
580
581 /* Enable OpRegion and LPC bridge quirk */
582 vdev->features |= VFIO_FEATURE_ENABLE_IGD_OPREGION;
583 vdev->features |= VFIO_FEATURE_ENABLE_IGD_LPC;
584 } else if (vdev->igd_legacy_mode == ON_OFF_AUTO_ON) {
585 error_setg(&err,
586 "Machine is not i440fx, assigned BDF is not 00:02.0, "
587 "or device %04x (gen %d) doesn't support legacy mode",
588 vdev->device_id, gen);
589 goto error;
590 }
591
592 /* Setup OpRegion access */
593 if ((vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) &&
594 !vfio_pci_igd_opregion_init(vdev, opregion, errp)) {
595 goto error;
596 }
597
598 /* Setup LPC bridge / Host bridge PCI IDs */
599 if ((vdev->features & VFIO_FEATURE_ENABLE_IGD_LPC) &&
600 !vfio_pci_igd_setup_lpc_bridge(vdev, errp)) {
601 goto error;
602 }
603
604 /*
605 * ASLS (OpRegion address) is read-only, emulated
606 * It contains HPA, guest firmware need to reprogram it with GPA.
607 */
608 pci_set_long(vdev->pdev.config + IGD_ASLS, 0);
609 pci_set_long(vdev->pdev.wmask + IGD_ASLS, ~0);
610 pci_set_long(vdev->emulated_config_bits + IGD_ASLS, ~0);
611
612 /*
613 * Allow user to override dsm size using x-igd-gms option, in multiples of
614 * 32MiB. This option should only be used when the desired size cannot be
615 * set from DVMT Pre-Allocated option in host BIOS.
616 */
617 if (vdev->igd_gms) {
618 if (!vfio_pci_igd_override_gms(gen, vdev->igd_gms, &gmch)) {
619 return false;
620 }
621
622 /* GMCH is read-only, emulated */
623 pci_set_long(vdev->pdev.config + IGD_GMCH, gmch);
624 pci_set_long(vdev->pdev.wmask + IGD_GMCH, 0);
625 pci_set_long(vdev->emulated_config_bits + IGD_GMCH, ~0);
626 }
627
628 if (gen > 0) {
629 gms_size = igd_stolen_memory_size(gen, gmch);
630
631 /* BDSM is read-write, emulated. BIOS needs to be able to write it */
632 if (gen < 11) {
633 pci_set_long(vdev->pdev.config + IGD_BDSM, 0);
634 pci_set_long(vdev->pdev.wmask + IGD_BDSM, ~0);
635 pci_set_long(vdev->emulated_config_bits + IGD_BDSM, ~0);
636 } else {
637 pci_set_quad(vdev->pdev.config + IGD_BDSM_GEN11, 0);
638 pci_set_quad(vdev->pdev.wmask + IGD_BDSM_GEN11, ~0);
639 pci_set_quad(vdev->emulated_config_bits + IGD_BDSM_GEN11, ~0);
640 }
641 }
642
643 /*
644 * Request reserved memory for stolen memory via fw_cfg. VM firmware
645 * must allocate a 1MB aligned reserved memory region below 4GB with
646 * the requested size (in bytes) for use by the IGD device. The base
647 * address of this reserved memory region must be written to the
648 * device BDSM register.
649 * For newer device without BDSM register, this fw_cfg item is 0.
650 */
651 bdsm_size = g_malloc(sizeof(*bdsm_size));
652 *bdsm_size = cpu_to_le64(gms_size);
653 fw_cfg_add_file(fw_cfg_find(), "etc/igd-bdsm-size",
654 bdsm_size, sizeof(*bdsm_size));
655
656 trace_vfio_pci_igd_bdsm_enabled(vdev->vbasedev.name, (gms_size / MiB));
657
658 return true;
659
660 error:
661 /*
662 * When legacy mode is implicity enabled, continue on error,
663 * to keep compatibility
664 */
665 if (legacy_mode_enabled && (vdev->igd_legacy_mode == ON_OFF_AUTO_AUTO)) {
666 error_report_err(err);
667 error_report("IGD legacy mode disabled");
668 return true;
669 }
670
671 error_propagate(errp, err);
672 return false;
673 }
674
675 /*
676 * KVMGT/GVT-g vGPU exposes an emulated OpRegion. So far, users have to specify
677 * x-igd-opregion=on to enable the access.
678 * TODO: Check VID/DID and enable opregion access automatically
679 */
vfio_pci_kvmgt_config_quirk(VFIOPCIDevice * vdev,Error ** errp)680 static bool vfio_pci_kvmgt_config_quirk(VFIOPCIDevice *vdev, Error **errp)
681 {
682 struct vfio_region_info *opregion = NULL;
683 int gen;
684
685 if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) ||
686 !vfio_is_vga(vdev)) {
687 return true;
688 }
689
690 /* FIXME: Cherryview is Gen8, but don't support GVT-g */
691 gen = igd_gen(vdev);
692 if (gen != 8 && gen != 9) {
693 return true;
694 }
695
696 if (!vfio_pci_igd_opregion_detect(vdev, &opregion)) {
697 /* Should never reach here, KVMGT always emulates OpRegion */
698 return false;
699 }
700
701 if ((vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) &&
702 !vfio_pci_igd_opregion_init(vdev, opregion, errp)) {
703 return false;
704 }
705
706 return true;
707 }
708
vfio_probe_igd_config_quirk(VFIOPCIDevice * vdev,Error ** errp)709 bool vfio_probe_igd_config_quirk(VFIOPCIDevice *vdev, Error **errp)
710 {
711 /* KVMGT/GVT-g vGPU is exposed as mdev */
712 if (vdev->vbasedev.mdev) {
713 return vfio_pci_kvmgt_config_quirk(vdev, errp);
714 }
715
716 return vfio_pci_igd_config_quirk(vdev, errp);
717 }
718