1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */ 3 4 #ifndef _HINIC3_NIC_DEV_H_ 5 #define _HINIC3_NIC_DEV_H_ 6 7 #include <linux/if_vlan.h> 8 #include <linux/netdevice.h> 9 10 #include "hinic3_hw_cfg.h" 11 #include "hinic3_hwdev.h" 12 #include "hinic3_mgmt_interface.h" 13 14 #define HINIC3_VLAN_BITMAP_BYTE_SIZE(nic_dev) (sizeof(*(nic_dev)->vlan_bitmap)) 15 #define HINIC3_VLAN_BITMAP_SIZE(nic_dev) \ 16 (VLAN_N_VID / HINIC3_VLAN_BITMAP_BYTE_SIZE(nic_dev)) 17 18 enum hinic3_flags { 19 HINIC3_INTF_UP, 20 HINIC3_MAC_FILTER_CHANGED, 21 HINIC3_RSS_ENABLE, 22 HINIC3_UPDATE_MAC_FILTER, 23 }; 24 25 enum hinic3_event_work_flags { 26 HINIC3_EVENT_WORK_TX_TIMEOUT, 27 }; 28 29 enum hinic3_rx_mode_state { 30 HINIC3_HW_PROMISC_ON, 31 HINIC3_HW_ALLMULTI_ON, 32 HINIC3_PROMISC_FORCE_ON, 33 HINIC3_ALLMULTI_FORCE_ON, 34 }; 35 36 enum hinic3_mac_filter_state { 37 HINIC3_MAC_WAIT_HW_SYNC, 38 HINIC3_MAC_HW_SYNCING, 39 HINIC3_MAC_HW_SYNCED, 40 HINIC3_MAC_WAIT_HW_UNSYNC, 41 HINIC3_MAC_HW_UNSYNCED, 42 }; 43 44 struct hinic3_mac_filter { 45 struct list_head list; 46 u8 addr[ETH_ALEN]; 47 unsigned long state; 48 }; 49 50 enum hinic3_rss_hash_type { 51 HINIC3_RSS_HASH_ENGINE_TYPE_XOR = 0, 52 HINIC3_RSS_HASH_ENGINE_TYPE_TOEP = 1, 53 }; 54 55 struct hinic3_rss_type { 56 u8 tcp_ipv6_ext; 57 u8 ipv6_ext; 58 u8 tcp_ipv6; 59 u8 ipv6; 60 u8 tcp_ipv4; 61 u8 ipv4; 62 u8 udp_ipv6; 63 u8 udp_ipv4; 64 }; 65 66 struct hinic3_irq_cfg { 67 struct net_device *netdev; 68 u16 msix_entry_idx; 69 /* provided by OS */ 70 u32 irq_id; 71 char irq_name[IFNAMSIZ + 16]; 72 struct napi_struct napi; 73 cpumask_t affinity_mask; 74 struct hinic3_txq *txq; 75 struct hinic3_rxq *rxq; 76 u16 total_events; 77 }; 78 79 struct hinic3_dyna_txrxq_params { 80 u16 num_qps; 81 u32 sq_depth; 82 u32 rq_depth; 83 84 struct hinic3_dyna_txq_res *txqs_res; 85 struct hinic3_dyna_rxq_res *rxqs_res; 86 struct hinic3_irq_cfg *irq_cfg; 87 }; 88 89 struct hinic3_intr_coal_info { 90 u8 pending_limit; 91 u8 coalesce_timer_cfg; 92 u8 resend_timer_cfg; 93 94 u8 rx_pending_limit_low; 95 u8 rx_pending_limit_high; 96 }; 97 98 struct hinic3_nic_dev { 99 struct pci_dev *pdev; 100 struct net_device *netdev; 101 struct hinic3_hwdev *hwdev; 102 struct hinic3_nic_io *nic_io; 103 104 u16 max_qps; 105 u16 rx_buf_len; 106 u32 lro_replenish_thld; 107 unsigned long *vlan_bitmap; 108 unsigned long flags; 109 struct hinic3_nic_service_cap nic_svc_cap; 110 111 struct hinic3_dyna_txrxq_params q_params; 112 struct hinic3_txq *txqs; 113 struct hinic3_rxq *rxqs; 114 115 enum hinic3_rss_hash_type rss_hash_type; 116 struct hinic3_rss_type rss_type; 117 u8 *rss_hkey; 118 u16 *rss_indir; 119 120 u16 num_qp_irq; 121 struct msix_entry *qps_msix_entries; 122 123 struct hinic3_intr_coal_info *intr_coalesce; 124 u32 adaptive_rx_coal; 125 126 struct workqueue_struct *workq; 127 struct delayed_work periodic_work; 128 struct work_struct rx_mode_work; 129 /* lock for enable/disable port */ 130 struct mutex port_state_mutex; 131 132 struct list_head uc_filter_list; 133 struct list_head mc_filter_list; 134 unsigned long rx_mod_state; 135 int netdev_uc_cnt; 136 int netdev_mc_cnt; 137 138 /* flag bits defined by hinic3_event_work_flags */ 139 unsigned long event_flag; 140 bool link_status_up; 141 }; 142 143 void hinic3_set_netdev_ops(struct net_device *netdev); 144 int hinic3_set_hw_features(struct net_device *netdev); 145 int hinic3_qps_irq_init(struct net_device *netdev); 146 void hinic3_qps_irq_uninit(struct net_device *netdev); 147 148 void hinic3_set_rx_mode_work(struct work_struct *work); 149 void hinic3_clean_mac_list_filter(struct net_device *netdev); 150 151 #endif 152