1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2021-2021 Hisilicon Limited.
3
4 #ifndef __HCLGE_COMM_CMD_H
5 #define __HCLGE_COMM_CMD_H
6 #include <linux/types.h>
7
8 #include "hnae3.h"
9
10 #define HCLGE_COMM_CMD_FLAG_IN BIT(0)
11 #define HCLGE_COMM_CMD_FLAG_NEXT BIT(2)
12 #define HCLGE_COMM_CMD_FLAG_WR BIT(3)
13 #define HCLGE_COMM_CMD_FLAG_NO_INTR BIT(4)
14
15 #define HCLGE_COMM_SEND_SYNC(flag) \
16 ((flag) & HCLGE_COMM_CMD_FLAG_NO_INTR)
17
18 #define HCLGE_COMM_LINK_EVENT_REPORT_EN_B 0
19 #define HCLGE_COMM_NCSI_ERROR_REPORT_EN_B 1
20 #define HCLGE_COMM_PHY_IMP_EN_B 2
21 #define HCLGE_COMM_MAC_STATS_EXT_EN_B 3
22 #define HCLGE_COMM_SYNC_RX_RING_HEAD_EN_B 4
23 #define HCLGE_COMM_LLRS_FEC_EN_B 5
24
25 #define hclge_comm_dev_phy_imp_supported(ae_dev) \
26 test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (ae_dev)->caps)
27
28 #define HCLGE_COMM_TYPE_CRQ 0
29 #define HCLGE_COMM_TYPE_CSQ 1
30
31 #define HCLGE_COMM_CMDQ_CLEAR_WAIT_TIME 200
32
33 /* bar registers for cmdq */
34 #define HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG 0x27000
35 #define HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG 0x27004
36 #define HCLGE_COMM_NIC_CSQ_DEPTH_REG 0x27008
37 #define HCLGE_COMM_NIC_CSQ_TAIL_REG 0x27010
38 #define HCLGE_COMM_NIC_CSQ_HEAD_REG 0x27014
39 #define HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG 0x27018
40 #define HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG 0x2701C
41 #define HCLGE_COMM_NIC_CRQ_DEPTH_REG 0x27020
42 #define HCLGE_COMM_NIC_CRQ_TAIL_REG 0x27024
43 #define HCLGE_COMM_NIC_CRQ_HEAD_REG 0x27028
44 /* Vector0 interrupt CMDQ event source register(RW) */
45 #define HCLGE_COMM_VECTOR0_CMDQ_SRC_REG 0x27100
46 /* Vector0 interrupt CMDQ event status register(RO) */
47 #define HCLGE_COMM_VECTOR0_CMDQ_STATE_REG 0x27104
48 #define HCLGE_COMM_CMDQ_INTR_EN_REG 0x27108
49 #define HCLGE_COMM_CMDQ_INTR_GEN_REG 0x2710C
50 #define HCLGE_COMM_CMDQ_INTR_STS_REG 0x27104
51
52 /* this bit indicates that the driver is ready for hardware reset */
53 #define HCLGE_COMM_NIC_SW_RST_RDY_B 16
54 #define HCLGE_COMM_NIC_SW_RST_RDY BIT(HCLGE_COMM_NIC_SW_RST_RDY_B)
55 #define HCLGE_COMM_NIC_CMQ_DESC_NUM_S 3
56 #define HCLGE_COMM_NIC_CMQ_DESC_NUM 1024
57 #define HCLGE_COMM_CMDQ_TX_TIMEOUT_DEFAULT 30000
58 #define HCLGE_COMM_CMDQ_TX_TIMEOUT_500MS 500000
59
60 enum hclge_opcode_type {
61 /* Generic commands */
62 HCLGE_OPC_QUERY_FW_VER = 0x0001,
63 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020,
64 HCLGE_OPC_GBL_RST_STATUS = 0x0021,
65 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022,
66 HCLGE_OPC_QUERY_PF_RSRC = 0x0023,
67 HCLGE_OPC_QUERY_VF_RSRC = 0x0024,
68 HCLGE_OPC_GET_CFG_PARAM = 0x0025,
69 HCLGE_OPC_PF_RST_DONE = 0x0026,
70 HCLGE_OPC_QUERY_VF_RST_RDY = 0x0027,
71
72 HCLGE_OPC_STATS_64_BIT = 0x0030,
73 HCLGE_OPC_STATS_32_BIT = 0x0031,
74 HCLGE_OPC_STATS_MAC = 0x0032,
75 HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033,
76 HCLGE_OPC_STATS_MAC_ALL = 0x0034,
77
78 HCLGE_OPC_QUERY_REG_NUM = 0x0040,
79 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041,
80 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042,
81 HCLGE_OPC_DFX_BD_NUM = 0x0043,
82 HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044,
83 HCLGE_OPC_DFX_SSU_REG_0 = 0x0045,
84 HCLGE_OPC_DFX_SSU_REG_1 = 0x0046,
85 HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047,
86 HCLGE_OPC_DFX_RPU_REG_0 = 0x0048,
87 HCLGE_OPC_DFX_RPU_REG_1 = 0x0049,
88 HCLGE_OPC_DFX_NCSI_REG = 0x004A,
89 HCLGE_OPC_DFX_RTC_REG = 0x004B,
90 HCLGE_OPC_DFX_PPP_REG = 0x004C,
91 HCLGE_OPC_DFX_RCB_REG = 0x004D,
92 HCLGE_OPC_DFX_TQP_REG = 0x004E,
93 HCLGE_OPC_DFX_SSU_REG_2 = 0x004F,
94
95 HCLGE_OPC_QUERY_DEV_SPECS = 0x0050,
96 HCLGE_OPC_GET_QUEUE_ERR_VF = 0x0067,
97
98 /* MAC command */
99 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301,
100 HCLGE_OPC_CONFIG_AN_MODE = 0x0304,
101 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307,
102 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
103 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309,
104 HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310,
105 HCLGE_OPC_MAC_TNL_INT_EN = 0x0311,
106 HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312,
107 HCLGE_OPC_COMMON_LOOPBACK = 0x0315,
108 HCLGE_OPC_QUERY_FEC_STATS = 0x0316,
109 HCLGE_OPC_CONFIG_FEC_MODE = 0x031A,
110 HCLGE_OPC_QUERY_ROH_TYPE_INFO = 0x0389,
111
112 /* PTP commands */
113 HCLGE_OPC_PTP_INT_EN = 0x0501,
114 HCLGE_OPC_PTP_MODE_CFG = 0x0507,
115
116 /* PFC/Pause commands */
117 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701,
118 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702,
119 HCLGE_OPC_CFG_MAC_PARA = 0x0703,
120 HCLGE_OPC_CFG_PFC_PARA = 0x0704,
121 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705,
122 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706,
123 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707,
124 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708,
125 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709,
126 HCLGE_OPC_QOS_MAP = 0x070A,
127
128 /* ETS/scheduler commands */
129 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804,
130 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805,
131 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806,
132 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807,
133 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808,
134 HCLGE_OPC_TM_PG_WEIGHT = 0x0809,
135 HCLGE_OPC_TM_QS_WEIGHT = 0x080A,
136 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B,
137 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C,
138 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D,
139 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E,
140 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F,
141 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810,
142 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812,
143 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,
144 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814,
145 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
146 HCLGE_OPC_TM_NODES = 0x0816,
147 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843,
148 HCLGE_OPC_QSET_DFX_STS = 0x0844,
149 HCLGE_OPC_PRI_DFX_STS = 0x0845,
150 HCLGE_OPC_PG_DFX_STS = 0x0846,
151 HCLGE_OPC_PORT_DFX_STS = 0x0847,
152 HCLGE_OPC_SCH_NQ_CNT = 0x0848,
153 HCLGE_OPC_SCH_RQ_CNT = 0x0849,
154 HCLGE_OPC_TM_INTERNAL_STS = 0x0850,
155 HCLGE_OPC_TM_INTERNAL_CNT = 0x0851,
156 HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852,
157 HCLGE_OPC_TM_FLUSH = 0x0872,
158
159 /* Packet buffer allocate commands */
160 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901,
161 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902,
162 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903,
163 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904,
164 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905,
165 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906,
166
167 /* TQP management command */
168 HCLGE_OPC_SET_TQP_MAP = 0x0A01,
169
170 /* TQP commands */
171 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01,
172 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02,
173 HCLGE_OPC_QUERY_TX_STATS = 0x0B03,
174 HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04,
175 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11,
176 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12,
177 HCLGE_OPC_QUERY_RX_STATS = 0x0B13,
178 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16,
179 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17,
180 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
181 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22,
182
183 /* PPU commands */
184 HCLGE_OPC_PPU_PF_OTHER_INT_DFX = 0x0B4A,
185
186 /* TSO command */
187 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01,
188 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10,
189
190 /* RSS commands */
191 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01,
192 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07,
193 HCLGE_OPC_RSS_TC_MODE = 0x0D08,
194 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02,
195
196 /* Promisuous mode command */
197 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01,
198
199 /* Vlan offload commands */
200 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01,
201 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02,
202
203 /* Interrupts commands */
204 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503,
205 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504,
206
207 /* MAC commands */
208 HCLGE_OPC_MAC_VLAN_ADD = 0x1000,
209 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001,
210 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002,
211 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003,
212 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004,
213 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010,
214 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011,
215
216 /* MAC VLAN commands */
217 HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033,
218
219 /* VLAN commands */
220 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100,
221 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101,
222 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102,
223 HCLGE_OPC_PORT_VLAN_BYPASS = 0x1103,
224
225 /* Flow Director commands */
226 HCLGE_OPC_FD_MODE_CTRL = 0x1200,
227 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201,
228 HCLGE_OPC_FD_KEY_CONFIG = 0x1202,
229 HCLGE_OPC_FD_TCAM_OP = 0x1203,
230 HCLGE_OPC_FD_AD_OP = 0x1204,
231 HCLGE_OPC_FD_CNT_OP = 0x1205,
232 HCLGE_OPC_FD_USER_DEF_OP = 0x1207,
233 HCLGE_OPC_FD_QB_CTRL = 0x1210,
234 HCLGE_OPC_FD_QB_AD_OP = 0x1211,
235
236 /* MDIO command */
237 HCLGE_OPC_MDIO_CONFIG = 0x1900,
238
239 /* QCN commands */
240 HCLGE_OPC_QCN_MOD_CFG = 0x1A01,
241 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02,
242 HCLGE_OPC_QCN_SHAPPING_CFG = 0x1A03,
243 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04,
244 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05,
245 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06,
246 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07,
247 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08,
248
249 /* Mailbox command */
250 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000,
251 HCLGEVF_OPC_MBX_VF_TO_PF = 0x2001,
252
253 /* Led command */
254 HCLGE_OPC_LED_STATUS_CFG = 0xB000,
255
256 /* clear hardware resource command */
257 HCLGE_OPC_CLEAR_HW_RESOURCE = 0x700B,
258
259 /* NCL config command */
260 HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011,
261
262 /* IMP stats command */
263 HCLGE_OPC_IMP_STATS_BD = 0x7012,
264 HCLGE_OPC_IMP_STATS_INFO = 0x7013,
265 HCLGE_OPC_IMP_COMPAT_CFG = 0x701A,
266
267 /* SFP command */
268 HCLGE_OPC_GET_SFP_EEPROM = 0x7100,
269 HCLGE_OPC_GET_SFP_EXIST = 0x7101,
270 HCLGE_OPC_GET_SFP_INFO = 0x7104,
271
272 /* Error INT commands */
273 HCLGE_MAC_COMMON_INT_EN = 0x030E,
274 HCLGE_TM_SCH_ECC_INT_EN = 0x0829,
275 HCLGE_SSU_ECC_INT_CMD = 0x0989,
276 HCLGE_SSU_COMMON_INT_CMD = 0x098C,
277 HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40,
278 HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41,
279 HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42,
280 HCLGE_COMMON_ECC_INT_CFG = 0x1505,
281 HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510,
282 HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511,
283 HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512,
284 HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
285 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
286 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
287 HCLGE_QUERY_ALL_ERR_BD_NUM = 0x1516,
288 HCLGE_QUERY_ALL_ERR_INFO = 0x1517,
289 HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580,
290 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
291 HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584,
292 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD = 0x1585,
293 HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD = 0x1586,
294 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803,
295 HCLGE_IGU_COMMON_INT_EN = 0x1806,
296 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14,
297 HCLGE_PPP_CMD0_INT_CMD = 0x2100,
298 HCLGE_PPP_CMD1_INT_CMD = 0x2101,
299 HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105,
300 HCLGE_OPC_WOL_GET_SUPPORTED_MODE = 0x2201,
301 HCLGE_OPC_WOL_CFG = 0x2202,
302 HCLGE_NCSI_INT_EN = 0x2401,
303
304 /* ROH MAC commands */
305 HCLGE_OPC_MAC_ADDR_CHECK = 0x9004,
306
307 /* PHY command */
308 HCLGE_OPC_PHY_LINK_KSETTING = 0x7025,
309 HCLGE_OPC_PHY_REG = 0x7026,
310
311 /* Query link diagnosis info command */
312 HCLGE_OPC_QUERY_LINK_DIAGNOSIS = 0x702A,
313 };
314
315 enum hclge_comm_cmd_return_status {
316 HCLGE_COMM_CMD_EXEC_SUCCESS = 0,
317 HCLGE_COMM_CMD_NO_AUTH = 1,
318 HCLGE_COMM_CMD_NOT_SUPPORTED = 2,
319 HCLGE_COMM_CMD_QUEUE_FULL = 3,
320 HCLGE_COMM_CMD_NEXT_ERR = 4,
321 HCLGE_COMM_CMD_UNEXE_ERR = 5,
322 HCLGE_COMM_CMD_PARA_ERR = 6,
323 HCLGE_COMM_CMD_RESULT_ERR = 7,
324 HCLGE_COMM_CMD_TIMEOUT = 8,
325 HCLGE_COMM_CMD_HILINK_ERR = 9,
326 HCLGE_COMM_CMD_QUEUE_ILLEGAL = 10,
327 HCLGE_COMM_CMD_INVALID = 11,
328 };
329
330 enum HCLGE_COMM_CAP_BITS {
331 HCLGE_COMM_CAP_UDP_GSO_B,
332 HCLGE_COMM_CAP_QB_B,
333 HCLGE_COMM_CAP_FD_FORWARD_TC_B,
334 HCLGE_COMM_CAP_PTP_B,
335 HCLGE_COMM_CAP_INT_QL_B,
336 HCLGE_COMM_CAP_HW_TX_CSUM_B,
337 HCLGE_COMM_CAP_TX_PUSH_B,
338 HCLGE_COMM_CAP_PHY_IMP_B,
339 HCLGE_COMM_CAP_TQP_TXRX_INDEP_B,
340 HCLGE_COMM_CAP_HW_PAD_B,
341 HCLGE_COMM_CAP_STASH_B,
342 HCLGE_COMM_CAP_UDP_TUNNEL_CSUM_B,
343 HCLGE_COMM_CAP_RAS_IMP_B = 12,
344 HCLGE_COMM_CAP_FEC_B = 13,
345 HCLGE_COMM_CAP_PAUSE_B = 14,
346 HCLGE_COMM_CAP_RXD_ADV_LAYOUT_B = 15,
347 HCLGE_COMM_CAP_PORT_VLAN_BYPASS_B = 17,
348 HCLGE_COMM_CAP_CQ_B = 18,
349 HCLGE_COMM_CAP_GRO_B = 20,
350 HCLGE_COMM_CAP_FD_B = 21,
351 HCLGE_COMM_CAP_FEC_STATS_B = 25,
352 HCLGE_COMM_CAP_VF_FAULT_B = 26,
353 HCLGE_COMM_CAP_LANE_NUM_B = 27,
354 HCLGE_COMM_CAP_WOL_B = 28,
355 HCLGE_COMM_CAP_TM_FLUSH_B = 31,
356 };
357
358 enum HCLGE_COMM_API_CAP_BITS {
359 HCLGE_COMM_API_CAP_FLEX_RSS_TBL_B,
360 };
361
362 /* capabilities bits map between imp firmware and local driver */
363 struct hclge_comm_caps_bit_map {
364 u16 imp_bit;
365 u16 local_bit;
366 };
367
368 struct hclge_cmdq_tx_timeout_map {
369 u32 opcode;
370 u32 tx_timeout;
371 };
372
373 struct hclge_comm_firmware_compat_cmd {
374 __le32 compat;
375 u8 rsv[20];
376 };
377
378 enum hclge_comm_cmd_state {
379 HCLGE_COMM_STATE_CMD_DISABLE,
380 };
381
382 struct hclge_comm_errcode {
383 u32 imp_errcode;
384 int common_errno;
385 };
386
387 #define HCLGE_COMM_QUERY_CAP_LENGTH 3
388 struct hclge_comm_query_version_cmd {
389 __le32 firmware;
390 __le32 hardware;
391 __le32 api_caps;
392 __le32 caps[HCLGE_COMM_QUERY_CAP_LENGTH]; /* capabilities of device */
393 };
394
395 #define HCLGE_DESC_DATA_LEN 6
396 struct hclge_desc {
397 __le16 opcode;
398 __le16 flag;
399 __le16 retval;
400 __le16 rsv;
401 __le32 data[HCLGE_DESC_DATA_LEN];
402 };
403
404 struct hclge_comm_cmq_ring {
405 dma_addr_t desc_dma_addr;
406 struct hclge_desc *desc;
407 struct pci_dev *pdev;
408 u32 head;
409 u32 tail;
410
411 u16 buf_size;
412 u16 desc_num;
413 int next_to_use;
414 int next_to_clean;
415 u8 ring_type; /* cmq ring type */
416 spinlock_t lock; /* Command queue lock */
417 };
418
419 enum hclge_comm_cmd_status {
420 HCLGE_COMM_STATUS_SUCCESS = 0,
421 HCLGE_COMM_ERR_CSQ_FULL = -1,
422 HCLGE_COMM_ERR_CSQ_TIMEOUT = -2,
423 HCLGE_COMM_ERR_CSQ_ERROR = -3,
424 };
425
426 struct hclge_comm_cmq {
427 struct hclge_comm_cmq_ring csq;
428 struct hclge_comm_cmq_ring crq;
429 u16 tx_timeout;
430 enum hclge_comm_cmd_status last_status;
431 };
432
433 struct hclge_comm_hw {
434 void __iomem *io_base;
435 void __iomem *mem_base;
436 struct hclge_comm_cmq cmq;
437 unsigned long comm_state;
438 };
439
hclge_comm_write_reg(void __iomem * base,u32 reg,u32 value)440 static inline void hclge_comm_write_reg(void __iomem *base, u32 reg, u32 value)
441 {
442 writel(value, base + reg);
443 }
444
hclge_comm_read_reg(u8 __iomem * base,u32 reg)445 static inline u32 hclge_comm_read_reg(u8 __iomem *base, u32 reg)
446 {
447 u8 __iomem *reg_addr = READ_ONCE(base);
448
449 return readl(reg_addr + reg);
450 }
451
452 #define hclge_comm_write_dev(a, reg, value) \
453 hclge_comm_write_reg((a)->io_base, reg, value)
454 #define hclge_comm_read_dev(a, reg) \
455 hclge_comm_read_reg((a)->io_base, reg)
456
457 void hclge_comm_cmd_init_regs(struct hclge_comm_hw *hw);
458 int hclge_comm_cmd_query_version_and_capability(struct hnae3_ae_dev *ae_dev,
459 struct hclge_comm_hw *hw,
460 u32 *fw_version, bool is_pf);
461 int hclge_comm_alloc_cmd_queue(struct hclge_comm_hw *hw, int ring_type);
462 int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc,
463 int num);
464 void hclge_comm_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
465 int hclge_comm_firmware_compat_config(struct hnae3_ae_dev *ae_dev,
466 struct hclge_comm_hw *hw, bool en);
467 void hclge_comm_free_cmd_desc(struct hclge_comm_cmq_ring *ring);
468 void hclge_comm_cmd_setup_basic_desc(struct hclge_desc *desc,
469 enum hclge_opcode_type opcode,
470 bool is_read);
471 void hclge_comm_cmd_uninit(struct hnae3_ae_dev *ae_dev,
472 struct hclge_comm_hw *hw);
473 int hclge_comm_cmd_queue_init(struct pci_dev *pdev, struct hclge_comm_hw *hw);
474 int hclge_comm_cmd_init(struct hnae3_ae_dev *ae_dev, struct hclge_comm_hw *hw,
475 u32 *fw_version, bool is_pf,
476 unsigned long reset_pending);
477
478 #endif
479