1 /*
2 * QEMU GT64120 PCI host
3 *
4 * (Datasheet GT-64120 Rev 1.4 from Sep 14, 1999)
5 *
6 * Copyright (c) 2006,2007 Aurelien Jarno
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "qemu/units.h"
30 #include "qemu/log.h"
31 #include "hw/qdev-properties.h"
32 #include "hw/registerfields.h"
33 #include "hw/pci/pci_device.h"
34 #include "hw/pci/pci_host.h"
35 #include "hw/misc/empty_slot.h"
36 #include "migration/vmstate.h"
37 #include "hw/intc/i8259.h"
38 #include "hw/irq.h"
39 #include "trace.h"
40 #include "qom/object.h"
41
42 #define GT_REGS (0x1000 >> 2)
43
44 /* CPU Configuration */
45 #define GT_CPU (0x000 >> 2)
46 #define GT_MULTI (0x120 >> 2)
47
48 REG32(GT_CPU, 0x000)
49 FIELD(GT_CPU, Endianness, 12, 1)
50
51 /* CPU Address Decode */
52 #define GT_SCS10LD (0x008 >> 2)
53 #define GT_SCS10HD (0x010 >> 2)
54 #define GT_SCS32LD (0x018 >> 2)
55 #define GT_SCS32HD (0x020 >> 2)
56 #define GT_CS20LD (0x028 >> 2)
57 #define GT_CS20HD (0x030 >> 2)
58 #define GT_CS3BOOTLD (0x038 >> 2)
59 #define GT_CS3BOOTHD (0x040 >> 2)
60 #define GT_PCI0IOLD (0x048 >> 2)
61 #define GT_PCI0IOHD (0x050 >> 2)
62 #define GT_PCI0M0LD (0x058 >> 2)
63 #define GT_PCI0M0HD (0x060 >> 2)
64 #define GT_PCI0M1LD (0x080 >> 2)
65 #define GT_PCI0M1HD (0x088 >> 2)
66 #define GT_PCI1IOLD (0x090 >> 2)
67 #define GT_PCI1IOHD (0x098 >> 2)
68 #define GT_PCI1M0LD (0x0a0 >> 2)
69 #define GT_PCI1M0HD (0x0a8 >> 2)
70 #define GT_PCI1M1LD (0x0b0 >> 2)
71 #define GT_PCI1M1HD (0x0b8 >> 2)
72 #define GT_ISD (0x068 >> 2)
73
74 #define GT_SCS10AR (0x0d0 >> 2)
75 #define GT_SCS32AR (0x0d8 >> 2)
76 #define GT_CS20R (0x0e0 >> 2)
77 #define GT_CS3BOOTR (0x0e8 >> 2)
78
79 #define GT_PCI0IOREMAP (0x0f0 >> 2)
80 #define GT_PCI0M0REMAP (0x0f8 >> 2)
81 #define GT_PCI0M1REMAP (0x100 >> 2)
82 #define GT_PCI1IOREMAP (0x108 >> 2)
83 #define GT_PCI1M0REMAP (0x110 >> 2)
84 #define GT_PCI1M1REMAP (0x118 >> 2)
85
86 /* CPU Error Report */
87 #define GT_CPUERR_ADDRLO (0x070 >> 2)
88 #define GT_CPUERR_ADDRHI (0x078 >> 2)
89 #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
90 #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
91 #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
92
93 /* CPU Sync Barrier */
94 #define GT_PCI0SYNC (0x0c0 >> 2)
95 #define GT_PCI1SYNC (0x0c8 >> 2)
96
97 /* SDRAM and Device Address Decode */
98 #define GT_SCS0LD (0x400 >> 2)
99 #define GT_SCS0HD (0x404 >> 2)
100 #define GT_SCS1LD (0x408 >> 2)
101 #define GT_SCS1HD (0x40c >> 2)
102 #define GT_SCS2LD (0x410 >> 2)
103 #define GT_SCS2HD (0x414 >> 2)
104 #define GT_SCS3LD (0x418 >> 2)
105 #define GT_SCS3HD (0x41c >> 2)
106 #define GT_CS0LD (0x420 >> 2)
107 #define GT_CS0HD (0x424 >> 2)
108 #define GT_CS1LD (0x428 >> 2)
109 #define GT_CS1HD (0x42c >> 2)
110 #define GT_CS2LD (0x430 >> 2)
111 #define GT_CS2HD (0x434 >> 2)
112 #define GT_CS3LD (0x438 >> 2)
113 #define GT_CS3HD (0x43c >> 2)
114 #define GT_BOOTLD (0x440 >> 2)
115 #define GT_BOOTHD (0x444 >> 2)
116 #define GT_ADERR (0x470 >> 2)
117
118 /* SDRAM Configuration */
119 #define GT_SDRAM_CFG (0x448 >> 2)
120 #define GT_SDRAM_OPMODE (0x474 >> 2)
121 #define GT_SDRAM_BM (0x478 >> 2)
122 #define GT_SDRAM_ADDRDECODE (0x47c >> 2)
123
124 /* SDRAM Parameters */
125 #define GT_SDRAM_B0 (0x44c >> 2)
126 #define GT_SDRAM_B1 (0x450 >> 2)
127 #define GT_SDRAM_B2 (0x454 >> 2)
128 #define GT_SDRAM_B3 (0x458 >> 2)
129
130 /* Device Parameters */
131 #define GT_DEV_B0 (0x45c >> 2)
132 #define GT_DEV_B1 (0x460 >> 2)
133 #define GT_DEV_B2 (0x464 >> 2)
134 #define GT_DEV_B3 (0x468 >> 2)
135 #define GT_DEV_BOOT (0x46c >> 2)
136
137 /* ECC */
138 #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
139 #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
140 #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
141 #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
142 #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
143
144 /* DMA Record */
145 #define GT_DMA0_CNT (0x800 >> 2)
146 #define GT_DMA1_CNT (0x804 >> 2)
147 #define GT_DMA2_CNT (0x808 >> 2)
148 #define GT_DMA3_CNT (0x80c >> 2)
149 #define GT_DMA0_SA (0x810 >> 2)
150 #define GT_DMA1_SA (0x814 >> 2)
151 #define GT_DMA2_SA (0x818 >> 2)
152 #define GT_DMA3_SA (0x81c >> 2)
153 #define GT_DMA0_DA (0x820 >> 2)
154 #define GT_DMA1_DA (0x824 >> 2)
155 #define GT_DMA2_DA (0x828 >> 2)
156 #define GT_DMA3_DA (0x82c >> 2)
157 #define GT_DMA0_NEXT (0x830 >> 2)
158 #define GT_DMA1_NEXT (0x834 >> 2)
159 #define GT_DMA2_NEXT (0x838 >> 2)
160 #define GT_DMA3_NEXT (0x83c >> 2)
161 #define GT_DMA0_CUR (0x870 >> 2)
162 #define GT_DMA1_CUR (0x874 >> 2)
163 #define GT_DMA2_CUR (0x878 >> 2)
164 #define GT_DMA3_CUR (0x87c >> 2)
165
166 /* DMA Channel Control */
167 #define GT_DMA0_CTRL (0x840 >> 2)
168 #define GT_DMA1_CTRL (0x844 >> 2)
169 #define GT_DMA2_CTRL (0x848 >> 2)
170 #define GT_DMA3_CTRL (0x84c >> 2)
171
172 /* DMA Arbiter */
173 #define GT_DMA_ARB (0x860 >> 2)
174
175 /* Timer/Counter */
176 #define GT_TC0 (0x850 >> 2)
177 #define GT_TC1 (0x854 >> 2)
178 #define GT_TC2 (0x858 >> 2)
179 #define GT_TC3 (0x85c >> 2)
180 #define GT_TC_CONTROL (0x864 >> 2)
181
182 /* PCI Internal */
183 #define GT_PCI0_CMD (0xc00 >> 2)
184 #define GT_PCI0_TOR (0xc04 >> 2)
185 #define GT_PCI0_BS_SCS10 (0xc08 >> 2)
186 #define GT_PCI0_BS_SCS32 (0xc0c >> 2)
187 #define GT_PCI0_BS_CS20 (0xc10 >> 2)
188 #define GT_PCI0_BS_CS3BT (0xc14 >> 2)
189 #define GT_PCI1_IACK (0xc30 >> 2)
190 #define GT_PCI0_IACK (0xc34 >> 2)
191 #define GT_PCI0_BARE (0xc3c >> 2)
192 #define GT_PCI0_PREFMBR (0xc40 >> 2)
193 #define GT_PCI0_SCS10_BAR (0xc48 >> 2)
194 #define GT_PCI0_SCS32_BAR (0xc4c >> 2)
195 #define GT_PCI0_CS20_BAR (0xc50 >> 2)
196 #define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
197 #define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
198 #define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
199 #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
200 #define GT_PCI1_CMD (0xc80 >> 2)
201 #define GT_PCI1_TOR (0xc84 >> 2)
202 #define GT_PCI1_BS_SCS10 (0xc88 >> 2)
203 #define GT_PCI1_BS_SCS32 (0xc8c >> 2)
204 #define GT_PCI1_BS_CS20 (0xc90 >> 2)
205 #define GT_PCI1_BS_CS3BT (0xc94 >> 2)
206 #define GT_PCI1_BARE (0xcbc >> 2)
207 #define GT_PCI1_PREFMBR (0xcc0 >> 2)
208 #define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
209 #define GT_PCI1_SCS32_BAR (0xccc >> 2)
210 #define GT_PCI1_CS20_BAR (0xcd0 >> 2)
211 #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
212 #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
213 #define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
214 #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
215 #define GT_PCI1_CFGADDR (0xcf0 >> 2)
216 #define GT_PCI1_CFGDATA (0xcf4 >> 2)
217 #define GT_PCI0_CFGADDR (0xcf8 >> 2)
218 #define GT_PCI0_CFGDATA (0xcfc >> 2)
219
220 REG32(GT_PCI0_CMD, 0xc00)
221 FIELD(GT_PCI0_CMD, MByteSwap, 0, 1)
222 FIELD(GT_PCI0_CMD, SByteSwap, 16, 1)
223 #define R_GT_PCI0_CMD_ByteSwap_MASK \
224 (R_GT_PCI0_CMD_MByteSwap_MASK | R_GT_PCI0_CMD_SByteSwap_MASK)
225 REG32(GT_PCI1_CMD, 0xc80)
226 FIELD(GT_PCI1_CMD, MByteSwap, 0, 1)
227 FIELD(GT_PCI1_CMD, SByteSwap, 16, 1)
228 #define R_GT_PCI1_CMD_ByteSwap_MASK \
229 (R_GT_PCI1_CMD_MByteSwap_MASK | R_GT_PCI1_CMD_SByteSwap_MASK)
230
231 /* Interrupts */
232 #define GT_INTRCAUSE (0xc18 >> 2)
233 #define GT_INTRMASK (0xc1c >> 2)
234 #define GT_PCI0_ICMASK (0xc24 >> 2)
235 #define GT_PCI0_SERR0MASK (0xc28 >> 2)
236 #define GT_CPU_INTSEL (0xc70 >> 2)
237 #define GT_PCI0_INTSEL (0xc74 >> 2)
238 #define GT_HINTRCAUSE (0xc98 >> 2)
239 #define GT_HINTRMASK (0xc9c >> 2)
240 #define GT_PCI0_HICMASK (0xca4 >> 2)
241 #define GT_PCI1_SERR1MASK (0xca8 >> 2)
242
243 #define PCI_MAPPING_ENTRY(regname) \
244 hwaddr regname ##_start; \
245 hwaddr regname ##_length; \
246 MemoryRegion regname ##_mem
247
248 #define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
249
250 OBJECT_DECLARE_SIMPLE_TYPE(GT64120State, GT64120_PCI_HOST_BRIDGE)
251
252 struct GT64120State {
253 PCIHostState parent_obj;
254
255 uint32_t regs[GT_REGS];
256 PCI_MAPPING_ENTRY(PCI0IO);
257 PCI_MAPPING_ENTRY(PCI0M0);
258 PCI_MAPPING_ENTRY(PCI0M1);
259 PCI_MAPPING_ENTRY(ISD);
260 MemoryRegion pci0_mem;
261 AddressSpace pci0_mem_as;
262
263 /* properties */
264 bool cpu_little_endian;
265 };
266
267 /* Adjust range to avoid touching space which isn't mappable via PCI */
268 /*
269 * XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
270 * 0x1fc00000 - 0x1fd00000
271 */
check_reserved_space(hwaddr * start,hwaddr * length)272 static void check_reserved_space(hwaddr *start, hwaddr *length)
273 {
274 hwaddr begin = *start;
275 hwaddr end = *start + *length;
276
277 if (end >= 0x1e000000LL && end < 0x1f100000LL) {
278 end = 0x1e000000LL;
279 }
280 if (begin >= 0x1e000000LL && begin < 0x1f100000LL) {
281 begin = 0x1f100000LL;
282 }
283 if (end >= 0x1fc00000LL && end < 0x1fd00000LL) {
284 end = 0x1fc00000LL;
285 }
286 if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) {
287 begin = 0x1fd00000LL;
288 }
289 /* XXX: This is broken when a reserved range splits the requested range */
290 if (end >= 0x1f100000LL && begin < 0x1e000000LL) {
291 end = 0x1e000000LL;
292 }
293 if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) {
294 end = 0x1fc00000LL;
295 }
296
297 *start = begin;
298 *length = end - begin;
299 }
300
gt64120_isd_mapping(GT64120State * s)301 static void gt64120_isd_mapping(GT64120State *s)
302 {
303 /* Bits 14:0 of ISD map to bits 35:21 of the start address. */
304 hwaddr start = ((hwaddr)s->regs[GT_ISD] << 21) & 0xFFFE00000ull;
305 hwaddr length = 0x1000;
306
307 memory_region_transaction_begin();
308
309 if (s->ISD_length) {
310 memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
311 }
312 check_reserved_space(&start, &length);
313 length = 0x1000;
314 /* Map new address */
315 trace_gt64120_isd_remap(s->ISD_length, s->ISD_start, length, start);
316 s->ISD_start = start;
317 s->ISD_length = length;
318 memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
319
320 memory_region_transaction_commit();
321 }
322
gt64120_pci_mapping(GT64120State * s)323 static void gt64120_pci_mapping(GT64120State *s)
324 {
325 memory_region_transaction_begin();
326
327 /* Update PCI0IO mapping */
328 if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) {
329 /* Unmap old IO address */
330 if (s->PCI0IO_length) {
331 memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem);
332 object_unparent(OBJECT(&s->PCI0IO_mem));
333 }
334 /* Map new IO address */
335 s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
336 s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) -
337 (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
338 if (s->PCI0IO_length) {
339 memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io",
340 get_system_io(), 0, s->PCI0IO_length);
341 memory_region_add_subregion(get_system_memory(), s->PCI0IO_start,
342 &s->PCI0IO_mem);
343 }
344 }
345
346 /* Update PCI0M0 mapping */
347 if ((s->regs[GT_PCI0M0LD] & 0x7f) <= s->regs[GT_PCI0M0HD]) {
348 /* Unmap old MEM address */
349 if (s->PCI0M0_length) {
350 memory_region_del_subregion(get_system_memory(), &s->PCI0M0_mem);
351 object_unparent(OBJECT(&s->PCI0M0_mem));
352 }
353 /* Map new mem address */
354 s->PCI0M0_start = s->regs[GT_PCI0M0LD] << 21;
355 s->PCI0M0_length = ((s->regs[GT_PCI0M0HD] + 1) -
356 (s->regs[GT_PCI0M0LD] & 0x7f)) << 21;
357 if (s->PCI0M0_length) {
358 memory_region_init_alias(&s->PCI0M0_mem, OBJECT(s), "pci0-mem0",
359 &s->pci0_mem, s->PCI0M0_start,
360 s->PCI0M0_length);
361 memory_region_add_subregion(get_system_memory(), s->PCI0M0_start,
362 &s->PCI0M0_mem);
363 }
364 }
365
366 /* Update PCI0M1 mapping */
367 if ((s->regs[GT_PCI0M1LD] & 0x7f) <= s->regs[GT_PCI0M1HD]) {
368 /* Unmap old MEM address */
369 if (s->PCI0M1_length) {
370 memory_region_del_subregion(get_system_memory(), &s->PCI0M1_mem);
371 object_unparent(OBJECT(&s->PCI0M1_mem));
372 }
373 /* Map new mem address */
374 s->PCI0M1_start = s->regs[GT_PCI0M1LD] << 21;
375 s->PCI0M1_length = ((s->regs[GT_PCI0M1HD] + 1) -
376 (s->regs[GT_PCI0M1LD] & 0x7f)) << 21;
377 if (s->PCI0M1_length) {
378 memory_region_init_alias(&s->PCI0M1_mem, OBJECT(s), "pci0-mem1",
379 &s->pci0_mem, s->PCI0M1_start,
380 s->PCI0M1_length);
381 memory_region_add_subregion(get_system_memory(), s->PCI0M1_start,
382 &s->PCI0M1_mem);
383 }
384 }
385
386 memory_region_transaction_commit();
387 }
388
gt64120_post_load(void * opaque,int version_id)389 static int gt64120_post_load(void *opaque, int version_id)
390 {
391 GT64120State *s = opaque;
392
393 gt64120_isd_mapping(s);
394 gt64120_pci_mapping(s);
395
396 return 0;
397 }
398
399 static const VMStateDescription vmstate_gt64120 = {
400 .name = "gt64120",
401 .version_id = 1,
402 .minimum_version_id = 1,
403 .post_load = gt64120_post_load,
404 .fields = (const VMStateField[]) {
405 VMSTATE_UINT32_ARRAY(regs, GT64120State, GT_REGS),
406 VMSTATE_END_OF_LIST()
407 }
408 };
409
gt64120_writel(void * opaque,hwaddr addr,uint64_t val,unsigned size)410 static void gt64120_writel(void *opaque, hwaddr addr,
411 uint64_t val, unsigned size)
412 {
413 GT64120State *s = opaque;
414 uint32_t saddr = addr >> 2;
415
416 trace_gt64120_write(addr, val);
417 if (!(s->regs[GT_CPU] & 0x00001000)) {
418 val = bswap32(val);
419 }
420
421 switch (saddr) {
422
423 /* CPU Configuration */
424 case GT_CPU:
425 s->regs[GT_CPU] = val;
426 break;
427 case GT_MULTI:
428 /* Read-only register as only one GT64xxx is present on the CPU bus */
429 break;
430
431 /* CPU Address Decode */
432 case GT_PCI0IOLD:
433 s->regs[GT_PCI0IOLD] = val & 0x00007fff;
434 s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
435 gt64120_pci_mapping(s);
436 break;
437 case GT_PCI0M0LD:
438 s->regs[GT_PCI0M0LD] = val & 0x00007fff;
439 s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
440 gt64120_pci_mapping(s);
441 break;
442 case GT_PCI0M1LD:
443 s->regs[GT_PCI0M1LD] = val & 0x00007fff;
444 s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
445 gt64120_pci_mapping(s);
446 break;
447 case GT_PCI1IOLD:
448 s->regs[GT_PCI1IOLD] = val & 0x00007fff;
449 s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
450 break;
451 case GT_PCI1M0LD:
452 s->regs[GT_PCI1M0LD] = val & 0x00007fff;
453 s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
454 break;
455 case GT_PCI1M1LD:
456 s->regs[GT_PCI1M1LD] = val & 0x00007fff;
457 s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
458 break;
459 case GT_PCI0M0HD:
460 case GT_PCI0M1HD:
461 case GT_PCI0IOHD:
462 s->regs[saddr] = val & 0x0000007f;
463 gt64120_pci_mapping(s);
464 break;
465 case GT_PCI1IOHD:
466 case GT_PCI1M0HD:
467 case GT_PCI1M1HD:
468 s->regs[saddr] = val & 0x0000007f;
469 break;
470 case GT_ISD:
471 s->regs[saddr] = val & 0x00007fff;
472 gt64120_isd_mapping(s);
473 break;
474
475 case GT_PCI0IOREMAP:
476 case GT_PCI0M0REMAP:
477 case GT_PCI0M1REMAP:
478 case GT_PCI1IOREMAP:
479 case GT_PCI1M0REMAP:
480 case GT_PCI1M1REMAP:
481 s->regs[saddr] = val & 0x000007ff;
482 break;
483
484 /* CPU Error Report */
485 case GT_CPUERR_ADDRLO:
486 case GT_CPUERR_ADDRHI:
487 case GT_CPUERR_DATALO:
488 case GT_CPUERR_DATAHI:
489 case GT_CPUERR_PARITY:
490 /* Read-only registers, do nothing */
491 qemu_log_mask(LOG_GUEST_ERROR,
492 "gt64120: Read-only register write "
493 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
494 saddr << 2, size, size << 1, val);
495 break;
496
497 /* CPU Sync Barrier */
498 case GT_PCI0SYNC:
499 case GT_PCI1SYNC:
500 /* Read-only registers, do nothing */
501 qemu_log_mask(LOG_GUEST_ERROR,
502 "gt64120: Read-only register write "
503 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
504 saddr << 2, size, size << 1, val);
505 break;
506
507 /* SDRAM and Device Address Decode */
508 case GT_SCS0LD:
509 case GT_SCS0HD:
510 case GT_SCS1LD:
511 case GT_SCS1HD:
512 case GT_SCS2LD:
513 case GT_SCS2HD:
514 case GT_SCS3LD:
515 case GT_SCS3HD:
516 case GT_CS0LD:
517 case GT_CS0HD:
518 case GT_CS1LD:
519 case GT_CS1HD:
520 case GT_CS2LD:
521 case GT_CS2HD:
522 case GT_CS3LD:
523 case GT_CS3HD:
524 case GT_BOOTLD:
525 case GT_BOOTHD:
526 case GT_ADERR:
527 /* SDRAM Configuration */
528 case GT_SDRAM_CFG:
529 case GT_SDRAM_OPMODE:
530 case GT_SDRAM_BM:
531 case GT_SDRAM_ADDRDECODE:
532 /* Accept and ignore SDRAM interleave configuration */
533 s->regs[saddr] = val;
534 break;
535
536 /* Device Parameters */
537 case GT_DEV_B0:
538 case GT_DEV_B1:
539 case GT_DEV_B2:
540 case GT_DEV_B3:
541 case GT_DEV_BOOT:
542 /* Not implemented */
543 qemu_log_mask(LOG_UNIMP,
544 "gt64120: Unimplemented device register write "
545 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
546 saddr << 2, size, size << 1, val);
547 break;
548
549 /* ECC */
550 case GT_ECC_ERRDATALO:
551 case GT_ECC_ERRDATAHI:
552 case GT_ECC_MEM:
553 case GT_ECC_CALC:
554 case GT_ECC_ERRADDR:
555 /* Read-only registers, do nothing */
556 qemu_log_mask(LOG_GUEST_ERROR,
557 "gt64120: Read-only register write "
558 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
559 saddr << 2, size, size << 1, val);
560 break;
561
562 /* DMA Record */
563 case GT_DMA0_CNT:
564 case GT_DMA1_CNT:
565 case GT_DMA2_CNT:
566 case GT_DMA3_CNT:
567 case GT_DMA0_SA:
568 case GT_DMA1_SA:
569 case GT_DMA2_SA:
570 case GT_DMA3_SA:
571 case GT_DMA0_DA:
572 case GT_DMA1_DA:
573 case GT_DMA2_DA:
574 case GT_DMA3_DA:
575 case GT_DMA0_NEXT:
576 case GT_DMA1_NEXT:
577 case GT_DMA2_NEXT:
578 case GT_DMA3_NEXT:
579 case GT_DMA0_CUR:
580 case GT_DMA1_CUR:
581 case GT_DMA2_CUR:
582 case GT_DMA3_CUR:
583
584 /* DMA Channel Control */
585 case GT_DMA0_CTRL:
586 case GT_DMA1_CTRL:
587 case GT_DMA2_CTRL:
588 case GT_DMA3_CTRL:
589
590 /* DMA Arbiter */
591 case GT_DMA_ARB:
592 /* Not implemented */
593 qemu_log_mask(LOG_UNIMP,
594 "gt64120: Unimplemented DMA register write "
595 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
596 saddr << 2, size, size << 1, val);
597 break;
598
599 /* Timer/Counter */
600 case GT_TC0:
601 case GT_TC1:
602 case GT_TC2:
603 case GT_TC3:
604 case GT_TC_CONTROL:
605 /* Not implemented */
606 qemu_log_mask(LOG_UNIMP,
607 "gt64120: Unimplemented timer register write "
608 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
609 saddr << 2, size, size << 1, val);
610 break;
611
612 /* PCI Internal */
613 case GT_PCI0_CMD:
614 case GT_PCI1_CMD:
615 s->regs[saddr] = val & 0x0401fc0f;
616 break;
617 case GT_PCI0_TOR:
618 case GT_PCI0_BS_SCS10:
619 case GT_PCI0_BS_SCS32:
620 case GT_PCI0_BS_CS20:
621 case GT_PCI0_BS_CS3BT:
622 case GT_PCI1_IACK:
623 case GT_PCI0_IACK:
624 case GT_PCI0_BARE:
625 case GT_PCI0_PREFMBR:
626 case GT_PCI0_SCS10_BAR:
627 case GT_PCI0_SCS32_BAR:
628 case GT_PCI0_CS20_BAR:
629 case GT_PCI0_CS3BT_BAR:
630 case GT_PCI0_SSCS10_BAR:
631 case GT_PCI0_SSCS32_BAR:
632 case GT_PCI0_SCS3BT_BAR:
633 case GT_PCI1_TOR:
634 case GT_PCI1_BS_SCS10:
635 case GT_PCI1_BS_SCS32:
636 case GT_PCI1_BS_CS20:
637 case GT_PCI1_BS_CS3BT:
638 case GT_PCI1_BARE:
639 case GT_PCI1_PREFMBR:
640 case GT_PCI1_SCS10_BAR:
641 case GT_PCI1_SCS32_BAR:
642 case GT_PCI1_CS20_BAR:
643 case GT_PCI1_CS3BT_BAR:
644 case GT_PCI1_SSCS10_BAR:
645 case GT_PCI1_SSCS32_BAR:
646 case GT_PCI1_SCS3BT_BAR:
647 case GT_PCI1_CFGADDR:
648 case GT_PCI1_CFGDATA:
649 /* not implemented */
650 qemu_log_mask(LOG_UNIMP,
651 "gt64120: Unimplemented PCI register write "
652 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
653 saddr << 2, size, size << 1, val);
654 break;
655 case GT_PCI0_CFGADDR:
656 case GT_PCI0_CFGDATA:
657 /* Mapped via in gt64120_pci_mapping() */
658 g_assert_not_reached();
659
660 /* Interrupts */
661 case GT_INTRCAUSE:
662 /* not really implemented */
663 s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
664 s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
665 trace_gt64120_write_intreg("INTRCAUSE", size, val);
666 break;
667 case GT_INTRMASK:
668 s->regs[saddr] = val & 0x3c3ffffe;
669 trace_gt64120_write_intreg("INTRMASK", size, val);
670 break;
671 case GT_PCI0_ICMASK:
672 s->regs[saddr] = val & 0x03fffffe;
673 trace_gt64120_write_intreg("ICMASK", size, val);
674 break;
675 case GT_PCI0_SERR0MASK:
676 s->regs[saddr] = val & 0x0000003f;
677 trace_gt64120_write_intreg("SERR0MASK", size, val);
678 break;
679
680 /* Reserved when only PCI_0 is configured. */
681 case GT_HINTRCAUSE:
682 case GT_CPU_INTSEL:
683 case GT_PCI0_INTSEL:
684 case GT_HINTRMASK:
685 case GT_PCI0_HICMASK:
686 case GT_PCI1_SERR1MASK:
687 /* not implemented */
688 break;
689
690 /* SDRAM Parameters */
691 case GT_SDRAM_B0:
692 case GT_SDRAM_B1:
693 case GT_SDRAM_B2:
694 case GT_SDRAM_B3:
695 /*
696 * We don't simulate electrical parameters of the SDRAM.
697 * Accept, but ignore the values.
698 */
699 s->regs[saddr] = val;
700 break;
701
702 default:
703 qemu_log_mask(LOG_GUEST_ERROR,
704 "gt64120: Illegal register write "
705 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
706 saddr << 2, size, size << 1, val);
707 break;
708 }
709 }
710
gt64120_readl(void * opaque,hwaddr addr,unsigned size)711 static uint64_t gt64120_readl(void *opaque,
712 hwaddr addr, unsigned size)
713 {
714 GT64120State *s = opaque;
715 uint32_t val;
716 uint32_t saddr = addr >> 2;
717
718 switch (saddr) {
719
720 /* CPU Configuration */
721 case GT_MULTI:
722 /*
723 * Only one GT64xxx is present on the CPU bus, return
724 * the initial value.
725 */
726 val = s->regs[saddr];
727 break;
728
729 /* CPU Error Report */
730 case GT_CPUERR_ADDRLO:
731 case GT_CPUERR_ADDRHI:
732 case GT_CPUERR_DATALO:
733 case GT_CPUERR_DATAHI:
734 case GT_CPUERR_PARITY:
735 /* Emulated memory has no error, always return the initial values. */
736 val = s->regs[saddr];
737 break;
738
739 /* CPU Sync Barrier */
740 case GT_PCI0SYNC:
741 case GT_PCI1SYNC:
742 /*
743 * Reading those register should empty all FIFO on the PCI
744 * bus, which are not emulated. The return value should be
745 * a random value that should be ignored.
746 */
747 val = 0xc000ffee;
748 break;
749
750 /* ECC */
751 case GT_ECC_ERRDATALO:
752 case GT_ECC_ERRDATAHI:
753 case GT_ECC_MEM:
754 case GT_ECC_CALC:
755 case GT_ECC_ERRADDR:
756 /* Emulated memory has no error, always return the initial values. */
757 val = s->regs[saddr];
758 break;
759
760 case GT_CPU:
761 case GT_SCS10LD:
762 case GT_SCS10HD:
763 case GT_SCS32LD:
764 case GT_SCS32HD:
765 case GT_CS20LD:
766 case GT_CS20HD:
767 case GT_CS3BOOTLD:
768 case GT_CS3BOOTHD:
769 case GT_SCS10AR:
770 case GT_SCS32AR:
771 case GT_CS20R:
772 case GT_CS3BOOTR:
773 case GT_PCI0IOLD:
774 case GT_PCI0M0LD:
775 case GT_PCI0M1LD:
776 case GT_PCI1IOLD:
777 case GT_PCI1M0LD:
778 case GT_PCI1M1LD:
779 case GT_PCI0IOHD:
780 case GT_PCI0M0HD:
781 case GT_PCI0M1HD:
782 case GT_PCI1IOHD:
783 case GT_PCI1M0HD:
784 case GT_PCI1M1HD:
785 case GT_PCI0IOREMAP:
786 case GT_PCI0M0REMAP:
787 case GT_PCI0M1REMAP:
788 case GT_PCI1IOREMAP:
789 case GT_PCI1M0REMAP:
790 case GT_PCI1M1REMAP:
791 case GT_ISD:
792 val = s->regs[saddr];
793 break;
794 case GT_PCI0_IACK:
795 /* Read the IRQ number */
796 val = pic_read_irq(isa_pic);
797 break;
798
799 /* SDRAM and Device Address Decode */
800 case GT_SCS0LD:
801 case GT_SCS0HD:
802 case GT_SCS1LD:
803 case GT_SCS1HD:
804 case GT_SCS2LD:
805 case GT_SCS2HD:
806 case GT_SCS3LD:
807 case GT_SCS3HD:
808 case GT_CS0LD:
809 case GT_CS0HD:
810 case GT_CS1LD:
811 case GT_CS1HD:
812 case GT_CS2LD:
813 case GT_CS2HD:
814 case GT_CS3LD:
815 case GT_CS3HD:
816 case GT_BOOTLD:
817 case GT_BOOTHD:
818 case GT_ADERR:
819 val = s->regs[saddr];
820 break;
821
822 /* SDRAM Configuration */
823 case GT_SDRAM_CFG:
824 case GT_SDRAM_OPMODE:
825 case GT_SDRAM_BM:
826 case GT_SDRAM_ADDRDECODE:
827 val = s->regs[saddr];
828 break;
829
830 /* SDRAM Parameters */
831 case GT_SDRAM_B0:
832 case GT_SDRAM_B1:
833 case GT_SDRAM_B2:
834 case GT_SDRAM_B3:
835 /*
836 * We don't simulate electrical parameters of the SDRAM.
837 * Just return the last written value.
838 */
839 val = s->regs[saddr];
840 break;
841
842 /* Device Parameters */
843 case GT_DEV_B0:
844 case GT_DEV_B1:
845 case GT_DEV_B2:
846 case GT_DEV_B3:
847 case GT_DEV_BOOT:
848 val = s->regs[saddr];
849 break;
850
851 /* DMA Record */
852 case GT_DMA0_CNT:
853 case GT_DMA1_CNT:
854 case GT_DMA2_CNT:
855 case GT_DMA3_CNT:
856 case GT_DMA0_SA:
857 case GT_DMA1_SA:
858 case GT_DMA2_SA:
859 case GT_DMA3_SA:
860 case GT_DMA0_DA:
861 case GT_DMA1_DA:
862 case GT_DMA2_DA:
863 case GT_DMA3_DA:
864 case GT_DMA0_NEXT:
865 case GT_DMA1_NEXT:
866 case GT_DMA2_NEXT:
867 case GT_DMA3_NEXT:
868 case GT_DMA0_CUR:
869 case GT_DMA1_CUR:
870 case GT_DMA2_CUR:
871 case GT_DMA3_CUR:
872 val = s->regs[saddr];
873 break;
874
875 /* DMA Channel Control */
876 case GT_DMA0_CTRL:
877 case GT_DMA1_CTRL:
878 case GT_DMA2_CTRL:
879 case GT_DMA3_CTRL:
880 val = s->regs[saddr];
881 break;
882
883 /* DMA Arbiter */
884 case GT_DMA_ARB:
885 val = s->regs[saddr];
886 break;
887
888 /* Timer/Counter */
889 case GT_TC0:
890 case GT_TC1:
891 case GT_TC2:
892 case GT_TC3:
893 case GT_TC_CONTROL:
894 val = s->regs[saddr];
895 break;
896
897 /* PCI Internal */
898 case GT_PCI0_CFGADDR:
899 case GT_PCI0_CFGDATA:
900 /* Mapped via in gt64120_pci_mapping() */
901 g_assert_not_reached();
902
903 case GT_PCI0_CMD:
904 case GT_PCI0_TOR:
905 case GT_PCI0_BS_SCS10:
906 case GT_PCI0_BS_SCS32:
907 case GT_PCI0_BS_CS20:
908 case GT_PCI0_BS_CS3BT:
909 case GT_PCI1_IACK:
910 case GT_PCI0_BARE:
911 case GT_PCI0_PREFMBR:
912 case GT_PCI0_SCS10_BAR:
913 case GT_PCI0_SCS32_BAR:
914 case GT_PCI0_CS20_BAR:
915 case GT_PCI0_CS3BT_BAR:
916 case GT_PCI0_SSCS10_BAR:
917 case GT_PCI0_SSCS32_BAR:
918 case GT_PCI0_SCS3BT_BAR:
919 case GT_PCI1_CMD:
920 case GT_PCI1_TOR:
921 case GT_PCI1_BS_SCS10:
922 case GT_PCI1_BS_SCS32:
923 case GT_PCI1_BS_CS20:
924 case GT_PCI1_BS_CS3BT:
925 case GT_PCI1_BARE:
926 case GT_PCI1_PREFMBR:
927 case GT_PCI1_SCS10_BAR:
928 case GT_PCI1_SCS32_BAR:
929 case GT_PCI1_CS20_BAR:
930 case GT_PCI1_CS3BT_BAR:
931 case GT_PCI1_SSCS10_BAR:
932 case GT_PCI1_SSCS32_BAR:
933 case GT_PCI1_SCS3BT_BAR:
934 case GT_PCI1_CFGADDR:
935 case GT_PCI1_CFGDATA:
936 val = s->regs[saddr];
937 break;
938
939 /* Interrupts */
940 case GT_INTRCAUSE:
941 val = s->regs[saddr];
942 trace_gt64120_read_intreg("INTRCAUSE", size, val);
943 break;
944 case GT_INTRMASK:
945 val = s->regs[saddr];
946 trace_gt64120_read_intreg("INTRMASK", size, val);
947 break;
948 case GT_PCI0_ICMASK:
949 val = s->regs[saddr];
950 trace_gt64120_read_intreg("ICMASK", size, val);
951 break;
952 case GT_PCI0_SERR0MASK:
953 val = s->regs[saddr];
954 trace_gt64120_read_intreg("SERR0MASK", size, val);
955 break;
956
957 /* Reserved when only PCI_0 is configured. */
958 case GT_HINTRCAUSE:
959 case GT_CPU_INTSEL:
960 case GT_PCI0_INTSEL:
961 case GT_HINTRMASK:
962 case GT_PCI0_HICMASK:
963 case GT_PCI1_SERR1MASK:
964 val = s->regs[saddr];
965 break;
966
967 default:
968 val = s->regs[saddr];
969 qemu_log_mask(LOG_GUEST_ERROR,
970 "gt64120: Illegal register read "
971 "reg:0x%03x size:%u value:0x%0*x\n",
972 saddr << 2, size, size << 1, val);
973 break;
974 }
975
976 if (!(s->regs[GT_CPU] & 0x00001000)) {
977 val = bswap32(val);
978 }
979 trace_gt64120_read(addr, val);
980
981 return val;
982 }
983
984 static const MemoryRegionOps isd_mem_ops = {
985 .read = gt64120_readl,
986 .write = gt64120_writel,
987 .endianness = DEVICE_NATIVE_ENDIAN,
988 .impl = {
989 .min_access_size = 4,
990 .max_access_size = 4,
991 },
992 };
993
bswap(const GT64120State * s)994 static bool bswap(const GT64120State *s)
995 {
996 PCIHostState *phb = PCI_HOST_BRIDGE(s);
997 /*check for bus == 0 && device == 0, Bits 11:15 = Device , Bits 16:23 = Bus*/
998 bool is_phb_dev0 = extract32(phb->config_reg, 11, 13) == 0;
999 bool le_mode = FIELD_EX32(s->regs[GT_PCI0_CMD], GT_PCI0_CMD, MByteSwap);
1000 /* Only swap for non-bridge devices in big-endian mode */
1001 return !le_mode && !is_phb_dev0;
1002 }
1003
gt64120_pci_data_read(void * opaque,hwaddr addr,unsigned size)1004 static uint64_t gt64120_pci_data_read(void *opaque, hwaddr addr, unsigned size)
1005 {
1006 GT64120State *s = opaque;
1007 uint32_t val = pci_host_data_le_ops.read(opaque, addr, size);
1008
1009 if (bswap(s)) {
1010 val = bswap32(val);
1011 }
1012 return val;
1013 }
1014
gt64120_pci_data_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)1015 static void gt64120_pci_data_write(void *opaque, hwaddr addr,
1016 uint64_t val, unsigned size)
1017 {
1018 GT64120State *s = opaque;
1019
1020 if (bswap(s)) {
1021 val = bswap32(val);
1022 }
1023 pci_host_data_le_ops.write(opaque, addr, val, size);
1024 }
1025
1026 static const MemoryRegionOps gt64120_pci_data_ops = {
1027 .read = gt64120_pci_data_read,
1028 .write = gt64120_pci_data_write,
1029 .endianness = DEVICE_LITTLE_ENDIAN,
1030 .valid = {
1031 .min_access_size = 4,
1032 .max_access_size = 4,
1033 },
1034 };
1035
gt64120_reset(DeviceState * dev)1036 static void gt64120_reset(DeviceState *dev)
1037 {
1038 GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
1039
1040 /* FIXME: Malta specific hw assumptions ahead */
1041
1042 /* CPU Configuration */
1043 s->regs[GT_CPU] = s->cpu_little_endian ? R_GT_CPU_Endianness_MASK : 0;
1044 s->regs[GT_MULTI] = 0x00000003;
1045
1046 /* CPU Address decode */
1047 s->regs[GT_SCS10LD] = 0x00000000;
1048 s->regs[GT_SCS10HD] = 0x00000007;
1049 s->regs[GT_SCS32LD] = 0x00000008;
1050 s->regs[GT_SCS32HD] = 0x0000000f;
1051 s->regs[GT_CS20LD] = 0x000000e0;
1052 s->regs[GT_CS20HD] = 0x00000070;
1053 s->regs[GT_CS3BOOTLD] = 0x000000f8;
1054 s->regs[GT_CS3BOOTHD] = 0x0000007f;
1055
1056 s->regs[GT_PCI0IOLD] = 0x00000080;
1057 s->regs[GT_PCI0IOHD] = 0x0000000f;
1058 s->regs[GT_PCI0M0LD] = 0x00000090;
1059 s->regs[GT_PCI0M0HD] = 0x0000001f;
1060 s->regs[GT_ISD] = 0x000000a0;
1061 s->regs[GT_PCI0M1LD] = 0x00000790;
1062 s->regs[GT_PCI0M1HD] = 0x0000001f;
1063 s->regs[GT_PCI1IOLD] = 0x00000100;
1064 s->regs[GT_PCI1IOHD] = 0x0000000f;
1065 s->regs[GT_PCI1M0LD] = 0x00000110;
1066 s->regs[GT_PCI1M0HD] = 0x0000001f;
1067 s->regs[GT_PCI1M1LD] = 0x00000120;
1068 s->regs[GT_PCI1M1HD] = 0x0000002f;
1069
1070 s->regs[GT_SCS10AR] = 0x00000000;
1071 s->regs[GT_SCS32AR] = 0x00000008;
1072 s->regs[GT_CS20R] = 0x000000e0;
1073 s->regs[GT_CS3BOOTR] = 0x000000f8;
1074
1075 s->regs[GT_PCI0IOREMAP] = 0x00000080;
1076 s->regs[GT_PCI0M0REMAP] = 0x00000090;
1077 s->regs[GT_PCI0M1REMAP] = 0x00000790;
1078 s->regs[GT_PCI1IOREMAP] = 0x00000100;
1079 s->regs[GT_PCI1M0REMAP] = 0x00000110;
1080 s->regs[GT_PCI1M1REMAP] = 0x00000120;
1081
1082 /* CPU Error Report */
1083 s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
1084 s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
1085 s->regs[GT_CPUERR_DATALO] = 0xffffffff;
1086 s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
1087 s->regs[GT_CPUERR_PARITY] = 0x000000ff;
1088
1089 /* CPU Sync Barrier */
1090 s->regs[GT_PCI0SYNC] = 0x00000000;
1091 s->regs[GT_PCI1SYNC] = 0x00000000;
1092
1093 /* SDRAM and Device Address Decode */
1094 s->regs[GT_SCS0LD] = 0x00000000;
1095 s->regs[GT_SCS0HD] = 0x00000007;
1096 s->regs[GT_SCS1LD] = 0x00000008;
1097 s->regs[GT_SCS1HD] = 0x0000000f;
1098 s->regs[GT_SCS2LD] = 0x00000010;
1099 s->regs[GT_SCS2HD] = 0x00000017;
1100 s->regs[GT_SCS3LD] = 0x00000018;
1101 s->regs[GT_SCS3HD] = 0x0000001f;
1102 s->regs[GT_CS0LD] = 0x000000c0;
1103 s->regs[GT_CS0HD] = 0x000000c7;
1104 s->regs[GT_CS1LD] = 0x000000c8;
1105 s->regs[GT_CS1HD] = 0x000000cf;
1106 s->regs[GT_CS2LD] = 0x000000d0;
1107 s->regs[GT_CS2HD] = 0x000000df;
1108 s->regs[GT_CS3LD] = 0x000000f0;
1109 s->regs[GT_CS3HD] = 0x000000fb;
1110 s->regs[GT_BOOTLD] = 0x000000fc;
1111 s->regs[GT_BOOTHD] = 0x000000ff;
1112 s->regs[GT_ADERR] = 0xffffffff;
1113
1114 /* SDRAM Configuration */
1115 s->regs[GT_SDRAM_CFG] = 0x00000200;
1116 s->regs[GT_SDRAM_OPMODE] = 0x00000000;
1117 s->regs[GT_SDRAM_BM] = 0x00000007;
1118 s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
1119
1120 /* SDRAM Parameters */
1121 s->regs[GT_SDRAM_B0] = 0x00000005;
1122 s->regs[GT_SDRAM_B1] = 0x00000005;
1123 s->regs[GT_SDRAM_B2] = 0x00000005;
1124 s->regs[GT_SDRAM_B3] = 0x00000005;
1125
1126 /* ECC */
1127 s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1128 s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1129 s->regs[GT_ECC_MEM] = 0x00000000;
1130 s->regs[GT_ECC_CALC] = 0x00000000;
1131 s->regs[GT_ECC_ERRADDR] = 0x00000000;
1132
1133 /* Device Parameters */
1134 s->regs[GT_DEV_B0] = 0x386fffff;
1135 s->regs[GT_DEV_B1] = 0x386fffff;
1136 s->regs[GT_DEV_B2] = 0x386fffff;
1137 s->regs[GT_DEV_B3] = 0x386fffff;
1138 s->regs[GT_DEV_BOOT] = 0x146fffff;
1139
1140 /* DMA registers are all zeroed at reset */
1141
1142 /* Timer/Counter */
1143 s->regs[GT_TC0] = 0xffffffff;
1144 s->regs[GT_TC1] = 0x00ffffff;
1145 s->regs[GT_TC2] = 0x00ffffff;
1146 s->regs[GT_TC3] = 0x00ffffff;
1147 s->regs[GT_TC_CONTROL] = 0x00000000;
1148
1149 /* PCI Internal */
1150 s->regs[GT_PCI0_CMD] = s->cpu_little_endian ? R_GT_PCI0_CMD_ByteSwap_MASK : 0;
1151 s->regs[GT_PCI0_TOR] = 0x0000070f;
1152 s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1153 s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1154 s->regs[GT_PCI0_BS_CS20] = 0x01fff000;
1155 s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
1156 s->regs[GT_PCI1_IACK] = 0x00000000;
1157 s->regs[GT_PCI0_IACK] = 0x00000000;
1158 s->regs[GT_PCI0_BARE] = 0x0000000f;
1159 s->regs[GT_PCI0_PREFMBR] = 0x00000040;
1160 s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1161 s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1162 s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1163 s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1164 s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1165 s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1166 s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1167 s->regs[GT_PCI1_CMD] = s->cpu_little_endian ? R_GT_PCI1_CMD_ByteSwap_MASK : 0;
1168 s->regs[GT_PCI1_TOR] = 0x0000070f;
1169 s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1170 s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1171 s->regs[GT_PCI1_BS_CS20] = 0x01fff000;
1172 s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1173 s->regs[GT_PCI1_BARE] = 0x0000000f;
1174 s->regs[GT_PCI1_PREFMBR] = 0x00000040;
1175 s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1176 s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1177 s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1178 s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1179 s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1180 s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1181 s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1182 s->regs[GT_PCI1_CFGADDR] = 0x00000000;
1183 s->regs[GT_PCI1_CFGDATA] = 0x00000000;
1184 s->regs[GT_PCI0_CFGADDR] = 0x00000000;
1185
1186 /* Interrupt registers are all zeroed at reset */
1187
1188 gt64120_isd_mapping(s);
1189 gt64120_pci_mapping(s);
1190 }
1191
gt64120_realize(DeviceState * dev,Error ** errp)1192 static void gt64120_realize(DeviceState *dev, Error **errp)
1193 {
1194 GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
1195 PCIHostState *phb = PCI_HOST_BRIDGE(dev);
1196
1197 memory_region_init_io(&s->ISD_mem, OBJECT(dev), &isd_mem_ops, s,
1198 "gt64120-isd", 0x1000);
1199 memory_region_init(&s->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB);
1200 address_space_init(&s->pci0_mem_as, &s->pci0_mem, "pci0-mem");
1201 phb->bus = pci_root_bus_new(dev, "pci",
1202 &s->pci0_mem,
1203 get_system_io(),
1204 PCI_DEVFN(18, 0), TYPE_PCI_BUS);
1205
1206 pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
1207 memory_region_init_io(&phb->conf_mem, OBJECT(phb),
1208 &pci_host_conf_le_ops,
1209 s, "pci-conf-idx", 4);
1210 memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGADDR << 2,
1211 &phb->conf_mem, 1);
1212
1213 memory_region_init_io(&phb->data_mem, OBJECT(phb),
1214 >64120_pci_data_ops,
1215 s, "pci-conf-data", 4);
1216 memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGDATA << 2,
1217 &phb->data_mem, 1);
1218
1219
1220 /*
1221 * The whole address space decoded by the GT-64120A doesn't generate
1222 * exception when accessing invalid memory. Create an empty slot to
1223 * emulate this feature.
1224 */
1225 empty_slot_init("GT64120", 0, 0x20000000);
1226 }
1227
gt64120_pci_realize(PCIDevice * d,Error ** errp)1228 static void gt64120_pci_realize(PCIDevice *d, Error **errp)
1229 {
1230 /* Values from chapter 17.16 "PCI Configuration" */
1231
1232 pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff008); /* SCS[1:0] */
1233 pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff008); /* SCS[3:2] */
1234 pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff008); /* CS[2:0] */
1235 pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff008); /* CS[3], BootCS */
1236 pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff000); /* ISD MMIO */
1237 pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001); /* ISD I/O */
1238 }
1239
gt64120_pci_reset_hold(Object * obj,ResetType type)1240 static void gt64120_pci_reset_hold(Object *obj, ResetType type)
1241 {
1242 PCIDevice *d = PCI_DEVICE(obj);
1243
1244 /* Values from chapter 17.16 "PCI Configuration" */
1245
1246 pci_set_word(d->config + PCI_COMMAND, 0);
1247 pci_set_word(d->config + PCI_STATUS,
1248 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
1249 pci_config_set_prog_interface(d->config, 0);
1250
1251 pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
1252 pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
1253 pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
1254 pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
1255 pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
1256 pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
1257
1258 pci_set_byte(d->config + 0x3d, 0x01);
1259 }
1260
gt64120_pci_class_init(ObjectClass * klass,const void * data)1261 static void gt64120_pci_class_init(ObjectClass *klass, const void *data)
1262 {
1263 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1264 DeviceClass *dc = DEVICE_CLASS(klass);
1265 ResettableClass *rc = RESETTABLE_CLASS(klass);
1266
1267 rc->phases.hold = gt64120_pci_reset_hold;
1268 k->realize = gt64120_pci_realize;
1269 k->vendor_id = PCI_VENDOR_ID_MARVELL;
1270 k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X;
1271 k->revision = 0x10;
1272 k->class_id = PCI_CLASS_BRIDGE_HOST;
1273 /*
1274 * PCI-facing part of the host bridge, not usable without the
1275 * host-facing part, which can't be device_add'ed, yet.
1276 */
1277 dc->user_creatable = false;
1278 }
1279
1280 static const TypeInfo gt64120_pci_info = {
1281 .name = "gt64120_pci",
1282 .parent = TYPE_PCI_DEVICE,
1283 .instance_size = sizeof(PCIDevice),
1284 .class_init = gt64120_pci_class_init,
1285 .interfaces = (const InterfaceInfo[]) {
1286 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1287 { },
1288 },
1289 };
1290
1291 static const Property gt64120_properties[] = {
1292 DEFINE_PROP_BOOL("cpu-little-endian", GT64120State,
1293 cpu_little_endian, false),
1294 };
1295
gt64120_class_init(ObjectClass * klass,const void * data)1296 static void gt64120_class_init(ObjectClass *klass, const void *data)
1297 {
1298 DeviceClass *dc = DEVICE_CLASS(klass);
1299
1300 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
1301 device_class_set_props(dc, gt64120_properties);
1302 dc->realize = gt64120_realize;
1303 device_class_set_legacy_reset(dc, gt64120_reset);
1304 dc->vmsd = &vmstate_gt64120;
1305 }
1306
1307 static const TypeInfo gt64120_info = {
1308 .name = TYPE_GT64120_PCI_HOST_BRIDGE,
1309 .parent = TYPE_PCI_HOST_BRIDGE,
1310 .instance_size = sizeof(GT64120State),
1311 .class_init = gt64120_class_init,
1312 };
1313
gt64120_pci_register_types(void)1314 static void gt64120_pci_register_types(void)
1315 {
1316 type_register_static(>64120_info);
1317 type_register_static(>64120_pci_info);
1318 }
1319
1320 type_init(gt64120_pci_register_types)
1321