1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #ifndef HRT_GDC_v2_defs_h_ 8 #define HRT_GDC_v2_defs_h_ 9 10 #define HRT_GDC_IS_V2 11 12 #define HRT_GDC_N 1024 /* Top-level design constant, equal to the number of entries in the LUT */ 13 #define HRT_GDC_FRAC_BITS 10 /* Number of fractional bits in the GDC block, driven by the size of the LUT */ 14 15 #define HRT_GDC_BLI_FRAC_BITS 4 /* Number of fractional bits for the bi-linear interpolation type */ 16 #define HRT_GDC_BLI_COEF_ONE BIT(HRT_GDC_BLI_FRAC_BITS) 17 18 #define HRT_GDC_BCI_COEF_BITS 14 /* 14 bits per coefficient */ 19 #define HRT_GDC_BCI_COEF_ONE (1 << (HRT_GDC_BCI_COEF_BITS - 2)) /* We represent signed 10 bit coefficients. */ 20 /* The supported range is [-256, .., +256] */ 21 /* in 14-bit signed notation, */ 22 /* We need all ten bits (MSB must be zero). */ 23 /* -s is inserted to solve this issue, and */ 24 /* therefore "1" is equal to +256. */ 25 #define HRT_GDC_BCI_COEF_MASK ((1 << HRT_GDC_BCI_COEF_BITS) - 1) 26 27 #define HRT_GDC_LUT_BYTES (HRT_GDC_N * 4 * 2) /* 1024 addresses, 4 coefficients per address, */ 28 /* 2 bytes per coefficient */ 29 30 #define _HRT_GDC_REG_ALIGN 4 31 32 // 31 30 29 25 24 0 33 // |-----|---|--------|------------------------| 34 // | CMD | C | Reg_ID | Value | 35 36 // There are just two commands possible for the GDC block: 37 // 1 - Configure reg 38 // 0 - Data token 39 40 // C - Reserved bit 41 // Used in protocol to indicate whether it is C-run or other type of runs 42 // In case of C-run, this bit has a value of 1, for all the other runs, it is 0. 43 44 // Reg_ID - Address of the register to be configured 45 46 // Value - Value to store to the addressed register, maximum of 24 bits 47 48 // Configure reg command is not followed by any other token. 49 // The address of the register and the data to be filled in is contained in the same token 50 51 // When the first data token is received, it must be: 52 // 1. FRX and FRY (device configured in one of the scaling modes) ***DEFAULT MODE***, or, 53 // 2. P0'X (device configured in one of the tetragon modes) 54 // After the first data token is received, pre-defined number of tokens with the following meaning follow: 55 // 1. two tokens: SRC address ; DST address 56 // 2. nine tokens: P0'Y, .., P3'Y ; SRC address ; DST address 57 58 #define HRT_GDC_CONFIG_CMD 1 59 #define HRT_GDC_DATA_CMD 0 60 61 #define HRT_GDC_CMD_POS 31 62 #define HRT_GDC_CMD_BITS 1 63 #define HRT_GDC_CRUN_POS 30 64 #define HRT_GDC_REG_ID_POS 25 65 #define HRT_GDC_REG_ID_BITS 5 66 #define HRT_GDC_DATA_POS 0 67 #define HRT_GDC_DATA_BITS 25 68 69 #define HRT_GDC_FRYIPXFRX_BITS 26 70 #define HRT_GDC_P0X_BITS 23 71 72 #define HRT_GDC_MAX_OXDIM (8192 - 64) 73 #define HRT_GDC_MAX_OYDIM 4095 74 #define HRT_GDC_MAX_IXDIM (8192 - 64) 75 #define HRT_GDC_MAX_IYDIM 4095 76 #define HRT_GDC_MAX_DS_FAC 16 77 #define HRT_GDC_MAX_DX (HRT_GDC_MAX_DS_FAC * HRT_GDC_N - 1) 78 #define HRT_GDC_MAX_DY HRT_GDC_MAX_DX 79 80 /* GDC lookup tables entries are 10 bits values, but they're 81 stored 2 by 2 as 32 bit values, yielding 16 bits per entry. 82 A GDC lookup table contains 64 * 4 elements */ 83 84 #define HRT_GDC_PERF_1_1_pix 0 85 #define HRT_GDC_PERF_2_1_pix 1 86 #define HRT_GDC_PERF_1_2_pix 2 87 #define HRT_GDC_PERF_2_2_pix 3 88 89 #define HRT_GDC_NND_MODE 0 90 #define HRT_GDC_BLI_MODE 1 91 #define HRT_GDC_BCI_MODE 2 92 #define HRT_GDC_LUT_MODE 3 93 94 #define HRT_GDC_SCAN_STB 0 95 #define HRT_GDC_SCAN_STR 1 96 97 #define HRT_GDC_MODE_SCALING 0 98 #define HRT_GDC_MODE_TETRAGON 1 99 100 #define HRT_GDC_LUT_COEFF_OFFSET 16 101 #define HRT_GDC_FRY_BIT_OFFSET 16 102 // FRYIPXFRX is the only register where we store two values in one field, 103 // to save one token in the scaling protocol. 104 // Like this, we have three tokens in the scaling protocol, 105 // Otherwise, we would have had four. 106 // The register bit-map is: 107 // 31 26 25 16 15 10 9 0 108 // |------|----------|------|----------| 109 // | XXXX | FRY | IPX | FRX | 110 111 #define HRT_GDC_CE_FSM0_POS 0 112 #define HRT_GDC_CE_FSM0_LEN 2 113 #define HRT_GDC_CE_OPY_POS 2 114 #define HRT_GDC_CE_OPY_LEN 14 115 #define HRT_GDC_CE_OPX_POS 16 116 #define HRT_GDC_CE_OPX_LEN 16 117 // CHK_ENGINE register bit-map: 118 // 31 16 15 2 1 0 119 // |----------------|-----------|----| 120 // | OPX | OPY |FSM0| 121 // However, for the time being at least, 122 // this implementation is meaningless in hss model, 123 // So, we just return 0 124 125 #define HRT_GDC_CHK_ENGINE_IDX 0 126 #define HRT_GDC_WOIX_IDX 1 127 #define HRT_GDC_WOIY_IDX 2 128 #define HRT_GDC_BPP_IDX 3 129 #define HRT_GDC_FRYIPXFRX_IDX 4 130 #define HRT_GDC_OXDIM_IDX 5 131 #define HRT_GDC_OYDIM_IDX 6 132 #define HRT_GDC_SRC_ADDR_IDX 7 133 #define HRT_GDC_SRC_END_ADDR_IDX 8 134 #define HRT_GDC_SRC_WRAP_ADDR_IDX 9 135 #define HRT_GDC_SRC_STRIDE_IDX 10 136 #define HRT_GDC_DST_ADDR_IDX 11 137 #define HRT_GDC_DST_STRIDE_IDX 12 138 #define HRT_GDC_DX_IDX 13 139 #define HRT_GDC_DY_IDX 14 140 #define HRT_GDC_P0X_IDX 15 141 #define HRT_GDC_P0Y_IDX 16 142 #define HRT_GDC_P1X_IDX 17 143 #define HRT_GDC_P1Y_IDX 18 144 #define HRT_GDC_P2X_IDX 19 145 #define HRT_GDC_P2Y_IDX 20 146 #define HRT_GDC_P3X_IDX 21 147 #define HRT_GDC_P3Y_IDX 22 148 #define HRT_GDC_PERF_POINT_IDX 23 // 1x1 ; 1x2 ; 2x1 ; 2x2 pixels per cc 149 #define HRT_GDC_INTERP_TYPE_IDX 24 // NND ; BLI ; BCI ; LUT 150 #define HRT_GDC_SCAN_IDX 25 // 0 = STB (Slide To Bottom) ; 1 = STR (Slide To Right) 151 #define HRT_GDC_PROC_MODE_IDX 26 // 0 = Scaling ; 1 = Tetragon 152 153 #define HRT_GDC_LUT_IDX 32 154 155 #endif /* HRT_GDC_v2_defs_h_ */ 156