1 /* Freescale Enhanced Local Bus Controller NAND driver
2 *
3 * Copyright © 2006-2007, 2010 Freescale Semiconductor
4 *
5 * Authors: Nick Spence <nick.spence@freescale.com>,
6 * Scott Wood <scottwood@freescale.com>
7 * Jack Lan <jack.lan@freescale.com>
8 * Roy Zang <tie-fei.zang@freescale.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25 #include <linux/module.h>
26 #include <linux/types.h>
27 #include <linux/init.h>
28 #include <linux/kernel.h>
29 #include <linux/string.h>
30 #include <linux/ioport.h>
31 #include <linux/of_platform.h>
32 #include <linux/platform_device.h>
33 #include <linux/slab.h>
34 #include <linux/interrupt.h>
35
36 #include <linux/mtd/mtd.h>
37 #include <linux/mtd/nand.h>
38 #include <linux/mtd/nand_ecc.h>
39 #include <linux/mtd/partitions.h>
40
41 #include <asm/io.h>
42 #include <asm/fsl_lbc.h>
43
44 #define MAX_BANKS 8
45 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
46 #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
47
48 /* mtd information per set */
49
50 struct fsl_elbc_mtd {
51 struct mtd_info mtd;
52 struct nand_chip chip;
53 struct fsl_lbc_ctrl *ctrl;
54
55 struct device *dev;
56 int bank; /* Chip select bank number */
57 u8 __iomem *vbase; /* Chip select base virtual address */
58 int page_size; /* NAND page size (0=512, 1=2048) */
59 unsigned int fmr; /* FCM Flash Mode Register value */
60 };
61
62 /* Freescale eLBC FCM controller information */
63
64 struct fsl_elbc_fcm_ctrl {
65 struct nand_hw_control controller;
66 struct fsl_elbc_mtd *chips[MAX_BANKS];
67
68 u8 __iomem *addr; /* Address of assigned FCM buffer */
69 unsigned int page; /* Last page written to / read from */
70 unsigned int read_bytes; /* Number of bytes read during command */
71 unsigned int column; /* Saved column from SEQIN */
72 unsigned int index; /* Pointer to next byte to 'read' */
73 unsigned int status; /* status read from LTESR after last op */
74 unsigned int mdr; /* UPM/FCM Data Register value */
75 unsigned int use_mdr; /* Non zero if the MDR is to be set */
76 unsigned int oob; /* Non zero if operating on OOB data */
77 unsigned int counter; /* counter for the initializations */
78 };
79
80 /* These map to the positions used by the FCM hardware ECC generator */
81
82 /* Small Page FLASH with FMR[ECCM] = 0 */
83 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
84 .eccbytes = 3,
85 .eccpos = {6, 7, 8},
86 .oobfree = { {0, 5}, {9, 7} },
87 };
88
89 /* Small Page FLASH with FMR[ECCM] = 1 */
90 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
91 .eccbytes = 3,
92 .eccpos = {8, 9, 10},
93 .oobfree = { {0, 5}, {6, 2}, {11, 5} },
94 };
95
96 /* Large Page FLASH with FMR[ECCM] = 0 */
97 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
98 .eccbytes = 12,
99 .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
100 .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
101 };
102
103 /* Large Page FLASH with FMR[ECCM] = 1 */
104 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
105 .eccbytes = 12,
106 .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
107 .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
108 };
109
110 /*
111 * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
112 * 1, so we have to adjust bad block pattern. This pattern should be used for
113 * x8 chips only. So far hardware does not support x16 chips anyway.
114 */
115 static u8 scan_ff_pattern[] = { 0xff, };
116
117 static struct nand_bbt_descr largepage_memorybased = {
118 .options = 0,
119 .offs = 0,
120 .len = 1,
121 .pattern = scan_ff_pattern,
122 };
123
124 /*
125 * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
126 * interfere with ECC positions, that's why we implement our own descriptors.
127 * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
128 */
129 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
130 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
131
132 static struct nand_bbt_descr bbt_main_descr = {
133 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
134 NAND_BBT_2BIT | NAND_BBT_VERSION,
135 .offs = 11,
136 .len = 4,
137 .veroffs = 15,
138 .maxblocks = 4,
139 .pattern = bbt_pattern,
140 };
141
142 static struct nand_bbt_descr bbt_mirror_descr = {
143 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
144 NAND_BBT_2BIT | NAND_BBT_VERSION,
145 .offs = 11,
146 .len = 4,
147 .veroffs = 15,
148 .maxblocks = 4,
149 .pattern = mirror_pattern,
150 };
151
152 /*=================================*/
153
154 /*
155 * Set up the FCM hardware block and page address fields, and the fcm
156 * structure addr field to point to the correct FCM buffer in memory
157 */
set_addr(struct mtd_info * mtd,int column,int page_addr,int oob)158 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
159 {
160 struct nand_chip *chip = mtd->priv;
161 struct fsl_elbc_mtd *priv = chip->priv;
162 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
163 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
164 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
165 int buf_num;
166
167 elbc_fcm_ctrl->page = page_addr;
168
169 if (priv->page_size) {
170 /*
171 * large page size chip : FPAR[PI] save the lowest 6 bits,
172 * FBAR[BLK] save the other bits.
173 */
174 out_be32(&lbc->fbar, page_addr >> 6);
175 out_be32(&lbc->fpar,
176 ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
177 (oob ? FPAR_LP_MS : 0) | column);
178 buf_num = (page_addr & 1) << 2;
179 } else {
180 /*
181 * small page size chip : FPAR[PI] save the lowest 5 bits,
182 * FBAR[BLK] save the other bits.
183 */
184 out_be32(&lbc->fbar, page_addr >> 5);
185 out_be32(&lbc->fpar,
186 ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
187 (oob ? FPAR_SP_MS : 0) | column);
188 buf_num = page_addr & 7;
189 }
190
191 elbc_fcm_ctrl->addr = priv->vbase + buf_num * 1024;
192 elbc_fcm_ctrl->index = column;
193
194 /* for OOB data point to the second half of the buffer */
195 if (oob)
196 elbc_fcm_ctrl->index += priv->page_size ? 2048 : 512;
197
198 dev_vdbg(priv->dev, "set_addr: bank=%d, "
199 "elbc_fcm_ctrl->addr=0x%p (0x%p), "
200 "index %x, pes %d ps %d\n",
201 buf_num, elbc_fcm_ctrl->addr, priv->vbase,
202 elbc_fcm_ctrl->index,
203 chip->phys_erase_shift, chip->page_shift);
204 }
205
206 /*
207 * execute FCM command and wait for it to complete
208 */
fsl_elbc_run_command(struct mtd_info * mtd)209 static int fsl_elbc_run_command(struct mtd_info *mtd)
210 {
211 struct nand_chip *chip = mtd->priv;
212 struct fsl_elbc_mtd *priv = chip->priv;
213 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
214 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
215 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
216
217 /* Setup the FMR[OP] to execute without write protection */
218 out_be32(&lbc->fmr, priv->fmr | 3);
219 if (elbc_fcm_ctrl->use_mdr)
220 out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr);
221
222 dev_vdbg(priv->dev,
223 "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
224 in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
225 dev_vdbg(priv->dev,
226 "fsl_elbc_run_command: fbar=%08x fpar=%08x "
227 "fbcr=%08x bank=%d\n",
228 in_be32(&lbc->fbar), in_be32(&lbc->fpar),
229 in_be32(&lbc->fbcr), priv->bank);
230
231 ctrl->irq_status = 0;
232 /* execute special operation */
233 out_be32(&lbc->lsor, priv->bank);
234
235 /* wait for FCM complete flag or timeout */
236 wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
237 FCM_TIMEOUT_MSECS * HZ/1000);
238 elbc_fcm_ctrl->status = ctrl->irq_status;
239 /* store mdr value in case it was needed */
240 if (elbc_fcm_ctrl->use_mdr)
241 elbc_fcm_ctrl->mdr = in_be32(&lbc->mdr);
242
243 elbc_fcm_ctrl->use_mdr = 0;
244
245 if (elbc_fcm_ctrl->status != LTESR_CC) {
246 dev_info(priv->dev,
247 "command failed: fir %x fcr %x status %x mdr %x\n",
248 in_be32(&lbc->fir), in_be32(&lbc->fcr),
249 elbc_fcm_ctrl->status, elbc_fcm_ctrl->mdr);
250 return -EIO;
251 }
252
253 if (chip->ecc.mode != NAND_ECC_HW)
254 return 0;
255
256 if (elbc_fcm_ctrl->read_bytes == mtd->writesize + mtd->oobsize) {
257 uint32_t lteccr = in_be32(&lbc->lteccr);
258 /*
259 * if command was a full page read and the ELBC
260 * has the LTECCR register, then bits 12-15 (ppc order) of
261 * LTECCR indicates which 512 byte sub-pages had fixed errors.
262 * bits 28-31 are uncorrectable errors, marked elsewhere.
263 * for small page nand only 1 bit is used.
264 * if the ELBC doesn't have the lteccr register it reads 0
265 */
266 if (lteccr & 0x000F000F)
267 out_be32(&lbc->lteccr, 0x000F000F); /* clear lteccr */
268 if (lteccr & 0x000F0000)
269 mtd->ecc_stats.corrected++;
270 }
271
272 return 0;
273 }
274
fsl_elbc_do_read(struct nand_chip * chip,int oob)275 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
276 {
277 struct fsl_elbc_mtd *priv = chip->priv;
278 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
279 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
280
281 if (priv->page_size) {
282 out_be32(&lbc->fir,
283 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
284 (FIR_OP_CA << FIR_OP1_SHIFT) |
285 (FIR_OP_PA << FIR_OP2_SHIFT) |
286 (FIR_OP_CM1 << FIR_OP3_SHIFT) |
287 (FIR_OP_RBW << FIR_OP4_SHIFT));
288
289 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
290 (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
291 } else {
292 out_be32(&lbc->fir,
293 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
294 (FIR_OP_CA << FIR_OP1_SHIFT) |
295 (FIR_OP_PA << FIR_OP2_SHIFT) |
296 (FIR_OP_RBW << FIR_OP3_SHIFT));
297
298 if (oob)
299 out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
300 else
301 out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
302 }
303 }
304
305 /* cmdfunc send commands to the FCM */
fsl_elbc_cmdfunc(struct mtd_info * mtd,unsigned int command,int column,int page_addr)306 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
307 int column, int page_addr)
308 {
309 struct nand_chip *chip = mtd->priv;
310 struct fsl_elbc_mtd *priv = chip->priv;
311 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
312 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
313 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
314
315 elbc_fcm_ctrl->use_mdr = 0;
316
317 /* clear the read buffer */
318 elbc_fcm_ctrl->read_bytes = 0;
319 if (command != NAND_CMD_PAGEPROG)
320 elbc_fcm_ctrl->index = 0;
321
322 switch (command) {
323 /* READ0 and READ1 read the entire buffer to use hardware ECC. */
324 case NAND_CMD_READ1:
325 column += 256;
326
327 /* fall-through */
328 case NAND_CMD_READ0:
329 dev_dbg(priv->dev,
330 "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
331 " 0x%x, column: 0x%x.\n", page_addr, column);
332
333
334 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
335 set_addr(mtd, 0, page_addr, 0);
336
337 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
338 elbc_fcm_ctrl->index += column;
339
340 fsl_elbc_do_read(chip, 0);
341 fsl_elbc_run_command(mtd);
342 return;
343
344 /* READOOB reads only the OOB because no ECC is performed. */
345 case NAND_CMD_READOOB:
346 dev_vdbg(priv->dev,
347 "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
348 " 0x%x, column: 0x%x.\n", page_addr, column);
349
350 out_be32(&lbc->fbcr, mtd->oobsize - column);
351 set_addr(mtd, column, page_addr, 1);
352
353 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
354
355 fsl_elbc_do_read(chip, 1);
356 fsl_elbc_run_command(mtd);
357 return;
358
359 case NAND_CMD_READID:
360 case NAND_CMD_PARAM:
361 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD %x\n", command);
362
363 out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |
364 (FIR_OP_UA << FIR_OP1_SHIFT) |
365 (FIR_OP_RBW << FIR_OP2_SHIFT));
366 out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);
367 /*
368 * although currently it's 8 bytes for READID, we always read
369 * the maximum 256 bytes(for PARAM)
370 */
371 out_be32(&lbc->fbcr, 256);
372 elbc_fcm_ctrl->read_bytes = 256;
373 elbc_fcm_ctrl->use_mdr = 1;
374 elbc_fcm_ctrl->mdr = column;
375 set_addr(mtd, 0, 0, 0);
376 fsl_elbc_run_command(mtd);
377 return;
378
379 /* ERASE1 stores the block and page address */
380 case NAND_CMD_ERASE1:
381 dev_vdbg(priv->dev,
382 "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
383 "page_addr: 0x%x.\n", page_addr);
384 set_addr(mtd, 0, page_addr, 0);
385 return;
386
387 /* ERASE2 uses the block and page address from ERASE1 */
388 case NAND_CMD_ERASE2:
389 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
390
391 out_be32(&lbc->fir,
392 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
393 (FIR_OP_PA << FIR_OP1_SHIFT) |
394 (FIR_OP_CM2 << FIR_OP2_SHIFT) |
395 (FIR_OP_CW1 << FIR_OP3_SHIFT) |
396 (FIR_OP_RS << FIR_OP4_SHIFT));
397
398 out_be32(&lbc->fcr,
399 (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
400 (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
401 (NAND_CMD_ERASE2 << FCR_CMD2_SHIFT));
402
403 out_be32(&lbc->fbcr, 0);
404 elbc_fcm_ctrl->read_bytes = 0;
405 elbc_fcm_ctrl->use_mdr = 1;
406
407 fsl_elbc_run_command(mtd);
408 return;
409
410 /* SEQIN sets up the addr buffer and all registers except the length */
411 case NAND_CMD_SEQIN: {
412 __be32 fcr;
413 dev_vdbg(priv->dev,
414 "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
415 "page_addr: 0x%x, column: 0x%x.\n",
416 page_addr, column);
417
418 elbc_fcm_ctrl->column = column;
419 elbc_fcm_ctrl->use_mdr = 1;
420
421 if (column >= mtd->writesize) {
422 /* OOB area */
423 column -= mtd->writesize;
424 elbc_fcm_ctrl->oob = 1;
425 } else {
426 WARN_ON(column != 0);
427 elbc_fcm_ctrl->oob = 0;
428 }
429
430 fcr = (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
431 (NAND_CMD_SEQIN << FCR_CMD2_SHIFT) |
432 (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT);
433
434 if (priv->page_size) {
435 out_be32(&lbc->fir,
436 (FIR_OP_CM2 << FIR_OP0_SHIFT) |
437 (FIR_OP_CA << FIR_OP1_SHIFT) |
438 (FIR_OP_PA << FIR_OP2_SHIFT) |
439 (FIR_OP_WB << FIR_OP3_SHIFT) |
440 (FIR_OP_CM3 << FIR_OP4_SHIFT) |
441 (FIR_OP_CW1 << FIR_OP5_SHIFT) |
442 (FIR_OP_RS << FIR_OP6_SHIFT));
443 } else {
444 out_be32(&lbc->fir,
445 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
446 (FIR_OP_CM2 << FIR_OP1_SHIFT) |
447 (FIR_OP_CA << FIR_OP2_SHIFT) |
448 (FIR_OP_PA << FIR_OP3_SHIFT) |
449 (FIR_OP_WB << FIR_OP4_SHIFT) |
450 (FIR_OP_CM3 << FIR_OP5_SHIFT) |
451 (FIR_OP_CW1 << FIR_OP6_SHIFT) |
452 (FIR_OP_RS << FIR_OP7_SHIFT));
453
454 if (elbc_fcm_ctrl->oob)
455 /* OOB area --> READOOB */
456 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
457 else
458 /* First 256 bytes --> READ0 */
459 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
460 }
461
462 out_be32(&lbc->fcr, fcr);
463 set_addr(mtd, column, page_addr, elbc_fcm_ctrl->oob);
464 return;
465 }
466
467 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
468 case NAND_CMD_PAGEPROG: {
469 dev_vdbg(priv->dev,
470 "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
471 "writing %d bytes.\n", elbc_fcm_ctrl->index);
472
473 /* if the write did not start at 0 or is not a full page
474 * then set the exact length, otherwise use a full page
475 * write so the HW generates the ECC.
476 */
477 if (elbc_fcm_ctrl->oob || elbc_fcm_ctrl->column != 0 ||
478 elbc_fcm_ctrl->index != mtd->writesize + mtd->oobsize)
479 out_be32(&lbc->fbcr,
480 elbc_fcm_ctrl->index - elbc_fcm_ctrl->column);
481 else
482 out_be32(&lbc->fbcr, 0);
483
484 fsl_elbc_run_command(mtd);
485 return;
486 }
487
488 /* CMD_STATUS must read the status byte while CEB is active */
489 /* Note - it does not wait for the ready line */
490 case NAND_CMD_STATUS:
491 out_be32(&lbc->fir,
492 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
493 (FIR_OP_RBW << FIR_OP1_SHIFT));
494 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
495 out_be32(&lbc->fbcr, 1);
496 set_addr(mtd, 0, 0, 0);
497 elbc_fcm_ctrl->read_bytes = 1;
498
499 fsl_elbc_run_command(mtd);
500
501 /* The chip always seems to report that it is
502 * write-protected, even when it is not.
503 */
504 setbits8(elbc_fcm_ctrl->addr, NAND_STATUS_WP);
505 return;
506
507 /* RESET without waiting for the ready line */
508 case NAND_CMD_RESET:
509 dev_dbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
510 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
511 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
512 fsl_elbc_run_command(mtd);
513 return;
514
515 default:
516 dev_err(priv->dev,
517 "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
518 command);
519 }
520 }
521
fsl_elbc_select_chip(struct mtd_info * mtd,int chip)522 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
523 {
524 /* The hardware does not seem to support multiple
525 * chips per bank.
526 */
527 }
528
529 /*
530 * Write buf to the FCM Controller Data Buffer
531 */
fsl_elbc_write_buf(struct mtd_info * mtd,const u8 * buf,int len)532 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
533 {
534 struct nand_chip *chip = mtd->priv;
535 struct fsl_elbc_mtd *priv = chip->priv;
536 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
537 unsigned int bufsize = mtd->writesize + mtd->oobsize;
538
539 if (len <= 0) {
540 dev_err(priv->dev, "write_buf of %d bytes", len);
541 elbc_fcm_ctrl->status = 0;
542 return;
543 }
544
545 if ((unsigned int)len > bufsize - elbc_fcm_ctrl->index) {
546 dev_err(priv->dev,
547 "write_buf beyond end of buffer "
548 "(%d requested, %u available)\n",
549 len, bufsize - elbc_fcm_ctrl->index);
550 len = bufsize - elbc_fcm_ctrl->index;
551 }
552
553 memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], buf, len);
554 /*
555 * This is workaround for the weird elbc hangs during nand write,
556 * Scott Wood says: "...perhaps difference in how long it takes a
557 * write to make it through the localbus compared to a write to IMMR
558 * is causing problems, and sync isn't helping for some reason."
559 * Reading back the last byte helps though.
560 */
561 in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index] + len - 1);
562
563 elbc_fcm_ctrl->index += len;
564 }
565
566 /*
567 * read a byte from either the FCM hardware buffer if it has any data left
568 * otherwise issue a command to read a single byte.
569 */
fsl_elbc_read_byte(struct mtd_info * mtd)570 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
571 {
572 struct nand_chip *chip = mtd->priv;
573 struct fsl_elbc_mtd *priv = chip->priv;
574 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
575
576 /* If there are still bytes in the FCM, then use the next byte. */
577 if (elbc_fcm_ctrl->index < elbc_fcm_ctrl->read_bytes)
578 return in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index++]);
579
580 dev_err(priv->dev, "read_byte beyond end of buffer\n");
581 return ERR_BYTE;
582 }
583
584 /*
585 * Read from the FCM Controller Data Buffer
586 */
fsl_elbc_read_buf(struct mtd_info * mtd,u8 * buf,int len)587 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
588 {
589 struct nand_chip *chip = mtd->priv;
590 struct fsl_elbc_mtd *priv = chip->priv;
591 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
592 int avail;
593
594 if (len < 0)
595 return;
596
597 avail = min((unsigned int)len,
598 elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
599 memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], avail);
600 elbc_fcm_ctrl->index += avail;
601
602 if (len > avail)
603 dev_err(priv->dev,
604 "read_buf beyond end of buffer "
605 "(%d requested, %d available)\n",
606 len, avail);
607 }
608
609 /*
610 * Verify buffer against the FCM Controller Data Buffer
611 */
fsl_elbc_verify_buf(struct mtd_info * mtd,const u_char * buf,int len)612 static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
613 {
614 struct nand_chip *chip = mtd->priv;
615 struct fsl_elbc_mtd *priv = chip->priv;
616 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
617 int i;
618
619 if (len < 0) {
620 dev_err(priv->dev, "write_buf of %d bytes", len);
621 return -EINVAL;
622 }
623
624 if ((unsigned int)len >
625 elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index) {
626 dev_err(priv->dev,
627 "verify_buf beyond end of buffer "
628 "(%d requested, %u available)\n",
629 len, elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
630
631 elbc_fcm_ctrl->index = elbc_fcm_ctrl->read_bytes;
632 return -EINVAL;
633 }
634
635 for (i = 0; i < len; i++)
636 if (in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index + i])
637 != buf[i])
638 break;
639
640 elbc_fcm_ctrl->index += len;
641 return i == len && elbc_fcm_ctrl->status == LTESR_CC ? 0 : -EIO;
642 }
643
644 /* This function is called after Program and Erase Operations to
645 * check for success or failure.
646 */
fsl_elbc_wait(struct mtd_info * mtd,struct nand_chip * chip)647 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
648 {
649 struct fsl_elbc_mtd *priv = chip->priv;
650 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
651
652 if (elbc_fcm_ctrl->status != LTESR_CC)
653 return NAND_STATUS_FAIL;
654
655 /* The chip always seems to report that it is
656 * write-protected, even when it is not.
657 */
658 return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP;
659 }
660
fsl_elbc_chip_init_tail(struct mtd_info * mtd)661 static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
662 {
663 struct nand_chip *chip = mtd->priv;
664 struct fsl_elbc_mtd *priv = chip->priv;
665 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
666 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
667 unsigned int al;
668
669 /* calculate FMR Address Length field */
670 al = 0;
671 if (chip->pagemask & 0xffff0000)
672 al++;
673 if (chip->pagemask & 0xff000000)
674 al++;
675
676 priv->fmr |= al << FMR_AL_SHIFT;
677
678 dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n",
679 chip->numchips);
680 dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n",
681 chip->chipsize);
682 dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
683 chip->pagemask);
684 dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
685 chip->chip_delay);
686 dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
687 chip->badblockpos);
688 dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
689 chip->chip_shift);
690 dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n",
691 chip->page_shift);
692 dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
693 chip->phys_erase_shift);
694 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecclayout = %p\n",
695 chip->ecclayout);
696 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
697 chip->ecc.mode);
698 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
699 chip->ecc.steps);
700 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
701 chip->ecc.bytes);
702 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
703 chip->ecc.total);
704 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
705 chip->ecc.layout);
706 dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
707 dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size);
708 dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
709 mtd->erasesize);
710 dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n",
711 mtd->writesize);
712 dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
713 mtd->oobsize);
714
715 /* adjust Option Register and ECC to match Flash page size */
716 if (mtd->writesize == 512) {
717 priv->page_size = 0;
718 clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
719 } else if (mtd->writesize == 2048) {
720 priv->page_size = 1;
721 setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
722 /* adjust ecc setup if needed */
723 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
724 BR_DECC_CHK_GEN) {
725 chip->ecc.size = 512;
726 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
727 &fsl_elbc_oob_lp_eccm1 :
728 &fsl_elbc_oob_lp_eccm0;
729 chip->badblock_pattern = &largepage_memorybased;
730 }
731 } else {
732 dev_err(priv->dev,
733 "fsl_elbc_init: page size %d is not supported\n",
734 mtd->writesize);
735 return -1;
736 }
737
738 return 0;
739 }
740
fsl_elbc_read_page(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int page)741 static int fsl_elbc_read_page(struct mtd_info *mtd,
742 struct nand_chip *chip,
743 uint8_t *buf,
744 int page)
745 {
746 fsl_elbc_read_buf(mtd, buf, mtd->writesize);
747 fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
748
749 if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
750 mtd->ecc_stats.failed++;
751
752 return 0;
753 }
754
755 /* ECC will be calculated automatically, and errors will be detected in
756 * waitfunc.
757 */
fsl_elbc_write_page(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf)758 static void fsl_elbc_write_page(struct mtd_info *mtd,
759 struct nand_chip *chip,
760 const uint8_t *buf)
761 {
762 fsl_elbc_write_buf(mtd, buf, mtd->writesize);
763 fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
764 }
765
fsl_elbc_chip_init(struct fsl_elbc_mtd * priv)766 static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
767 {
768 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
769 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
770 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
771 struct nand_chip *chip = &priv->chip;
772
773 dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
774
775 /* Fill in fsl_elbc_mtd structure */
776 priv->mtd.priv = chip;
777 priv->mtd.owner = THIS_MODULE;
778
779 /* set timeout to maximum */
780 priv->fmr = 15 << FMR_CWTO_SHIFT;
781 if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS)
782 priv->fmr |= FMR_ECCM;
783
784 /* fill in nand_chip structure */
785 /* set up function call table */
786 chip->read_byte = fsl_elbc_read_byte;
787 chip->write_buf = fsl_elbc_write_buf;
788 chip->read_buf = fsl_elbc_read_buf;
789 chip->verify_buf = fsl_elbc_verify_buf;
790 chip->select_chip = fsl_elbc_select_chip;
791 chip->cmdfunc = fsl_elbc_cmdfunc;
792 chip->waitfunc = fsl_elbc_wait;
793
794 chip->bbt_td = &bbt_main_descr;
795 chip->bbt_md = &bbt_mirror_descr;
796
797 /* set up nand options */
798 chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR;
799 chip->bbt_options = NAND_BBT_USE_FLASH;
800
801 chip->controller = &elbc_fcm_ctrl->controller;
802 chip->priv = priv;
803
804 chip->ecc.read_page = fsl_elbc_read_page;
805 chip->ecc.write_page = fsl_elbc_write_page;
806
807 /* If CS Base Register selects full hardware ECC then use it */
808 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
809 BR_DECC_CHK_GEN) {
810 chip->ecc.mode = NAND_ECC_HW;
811 /* put in small page settings and adjust later if needed */
812 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
813 &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0;
814 chip->ecc.size = 512;
815 chip->ecc.bytes = 3;
816 } else {
817 /* otherwise fall back to default software ECC */
818 chip->ecc.mode = NAND_ECC_SOFT;
819 }
820
821 return 0;
822 }
823
fsl_elbc_chip_remove(struct fsl_elbc_mtd * priv)824 static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
825 {
826 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
827 nand_release(&priv->mtd);
828
829 kfree(priv->mtd.name);
830
831 if (priv->vbase)
832 iounmap(priv->vbase);
833
834 elbc_fcm_ctrl->chips[priv->bank] = NULL;
835 kfree(priv);
836 return 0;
837 }
838
839 static DEFINE_MUTEX(fsl_elbc_nand_mutex);
840
fsl_elbc_nand_probe(struct platform_device * pdev)841 static int __devinit fsl_elbc_nand_probe(struct platform_device *pdev)
842 {
843 struct fsl_lbc_regs __iomem *lbc;
844 struct fsl_elbc_mtd *priv;
845 struct resource res;
846 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl;
847 static const char *part_probe_types[]
848 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
849 int ret;
850 int bank;
851 struct device *dev;
852 struct device_node *node = pdev->dev.of_node;
853 struct mtd_part_parser_data ppdata;
854
855 ppdata.of_node = pdev->dev.of_node;
856 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
857 return -ENODEV;
858 lbc = fsl_lbc_ctrl_dev->regs;
859 dev = fsl_lbc_ctrl_dev->dev;
860
861 /* get, allocate and map the memory resource */
862 ret = of_address_to_resource(node, 0, &res);
863 if (ret) {
864 dev_err(dev, "failed to get resource\n");
865 return ret;
866 }
867
868 /* find which chip select it is connected to */
869 for (bank = 0; bank < MAX_BANKS; bank++)
870 if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
871 (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
872 (in_be32(&lbc->bank[bank].br) &
873 in_be32(&lbc->bank[bank].or) & BR_BA)
874 == fsl_lbc_addr(res.start))
875 break;
876
877 if (bank >= MAX_BANKS) {
878 dev_err(dev, "address did not match any chip selects\n");
879 return -ENODEV;
880 }
881
882 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
883 if (!priv)
884 return -ENOMEM;
885
886 mutex_lock(&fsl_elbc_nand_mutex);
887 if (!fsl_lbc_ctrl_dev->nand) {
888 elbc_fcm_ctrl = kzalloc(sizeof(*elbc_fcm_ctrl), GFP_KERNEL);
889 if (!elbc_fcm_ctrl) {
890 dev_err(dev, "failed to allocate memory\n");
891 mutex_unlock(&fsl_elbc_nand_mutex);
892 ret = -ENOMEM;
893 goto err;
894 }
895 elbc_fcm_ctrl->counter++;
896
897 spin_lock_init(&elbc_fcm_ctrl->controller.lock);
898 init_waitqueue_head(&elbc_fcm_ctrl->controller.wq);
899 fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl;
900 } else {
901 elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
902 }
903 mutex_unlock(&fsl_elbc_nand_mutex);
904
905 elbc_fcm_ctrl->chips[bank] = priv;
906 priv->bank = bank;
907 priv->ctrl = fsl_lbc_ctrl_dev;
908 priv->dev = dev;
909
910 priv->vbase = ioremap(res.start, resource_size(&res));
911 if (!priv->vbase) {
912 dev_err(dev, "failed to map chip region\n");
913 ret = -ENOMEM;
914 goto err;
915 }
916
917 priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start);
918 if (!priv->mtd.name) {
919 ret = -ENOMEM;
920 goto err;
921 }
922
923 ret = fsl_elbc_chip_init(priv);
924 if (ret)
925 goto err;
926
927 ret = nand_scan_ident(&priv->mtd, 1, NULL);
928 if (ret)
929 goto err;
930
931 ret = fsl_elbc_chip_init_tail(&priv->mtd);
932 if (ret)
933 goto err;
934
935 ret = nand_scan_tail(&priv->mtd);
936 if (ret)
937 goto err;
938
939 /* First look for RedBoot table or partitions on the command
940 * line, these take precedence over device tree information */
941 mtd_device_parse_register(&priv->mtd, part_probe_types, &ppdata,
942 NULL, 0);
943
944 printk(KERN_INFO "eLBC NAND device at 0x%llx, bank %d\n",
945 (unsigned long long)res.start, priv->bank);
946 return 0;
947
948 err:
949 fsl_elbc_chip_remove(priv);
950 return ret;
951 }
952
fsl_elbc_nand_remove(struct platform_device * pdev)953 static int fsl_elbc_nand_remove(struct platform_device *pdev)
954 {
955 int i;
956 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
957 for (i = 0; i < MAX_BANKS; i++)
958 if (elbc_fcm_ctrl->chips[i])
959 fsl_elbc_chip_remove(elbc_fcm_ctrl->chips[i]);
960
961 mutex_lock(&fsl_elbc_nand_mutex);
962 elbc_fcm_ctrl->counter--;
963 if (!elbc_fcm_ctrl->counter) {
964 fsl_lbc_ctrl_dev->nand = NULL;
965 kfree(elbc_fcm_ctrl);
966 }
967 mutex_unlock(&fsl_elbc_nand_mutex);
968
969 return 0;
970
971 }
972
973 static const struct of_device_id fsl_elbc_nand_match[] = {
974 { .compatible = "fsl,elbc-fcm-nand", },
975 {}
976 };
977
978 static struct platform_driver fsl_elbc_nand_driver = {
979 .driver = {
980 .name = "fsl,elbc-fcm-nand",
981 .owner = THIS_MODULE,
982 .of_match_table = fsl_elbc_nand_match,
983 },
984 .probe = fsl_elbc_nand_probe,
985 .remove = fsl_elbc_nand_remove,
986 };
987
988 module_platform_driver(fsl_elbc_nand_driver);
989
990 MODULE_LICENSE("GPL");
991 MODULE_AUTHOR("Freescale");
992 MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");
993