1 /*
2 * Copyright (c) 2018, Impinj, Inc.
3 *
4 * i.MX7 SoC definitions
5 *
6 * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
7 *
8 * Based on hw/arm/fsl-imx6.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "hw/arm/fsl-imx7.h"
24 #include "hw/misc/unimp.h"
25 #include "hw/boards.h"
26 #include "system/system.h"
27 #include "qemu/error-report.h"
28 #include "qemu/module.h"
29 #include "target/arm/cpu-qom.h"
30
31 #define NAME_SIZE 20
32
fsl_imx7_init(Object * obj)33 static void fsl_imx7_init(Object *obj)
34 {
35 MachineState *ms = MACHINE(qdev_get_machine());
36 FslIMX7State *s = FSL_IMX7(obj);
37 char name[NAME_SIZE];
38 int i;
39
40 /*
41 * CPUs
42 */
43 for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
44 snprintf(name, NAME_SIZE, "cpu%d", i);
45 object_initialize_child(obj, name, &s->cpu[i],
46 ARM_CPU_TYPE_NAME("cortex-a7"));
47 }
48
49 /*
50 * A7MPCORE
51 */
52 object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
53 TYPE_A15MPCORE_PRIV);
54
55 /*
56 * GPIOs
57 */
58 for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
59 snprintf(name, NAME_SIZE, "gpio%d", i);
60 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
61 }
62
63 /*
64 * GPTs
65 */
66 for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
67 snprintf(name, NAME_SIZE, "gpt%d", i);
68 object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT);
69 }
70
71 /*
72 * CCM
73 */
74 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX7_CCM);
75
76 /*
77 * Analog
78 */
79 object_initialize_child(obj, "analog", &s->analog, TYPE_IMX7_ANALOG);
80
81 /*
82 * GPCv2
83 */
84 object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
85
86 /*
87 * SRC
88 */
89 object_initialize_child(obj, "src", &s->src, TYPE_IMX7_SRC);
90
91 /*
92 * ECSPIs
93 */
94 for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
95 snprintf(name, NAME_SIZE, "spi%d", i + 1);
96 object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
97 }
98
99 /*
100 * I2Cs
101 */
102 for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
103 snprintf(name, NAME_SIZE, "i2c%d", i + 1);
104 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
105 }
106
107 /*
108 * UARTs
109 */
110 for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
111 snprintf(name, NAME_SIZE, "uart%d", i);
112 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
113 }
114
115 /*
116 * Ethernets
117 */
118 for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
119 snprintf(name, NAME_SIZE, "eth%d", i);
120 object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
121 }
122
123 /*
124 * SDHCIs
125 */
126 for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
127 snprintf(name, NAME_SIZE, "usdhc%d", i);
128 object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
129 }
130
131 /*
132 * SNVS
133 */
134 object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
135
136 /*
137 * Watchdogs
138 */
139 for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
140 snprintf(name, NAME_SIZE, "wdt%d", i);
141 object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
142 }
143
144 /*
145 * GPR
146 */
147 object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
148
149 /*
150 * PCIE
151 */
152 object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
153 object_initialize_child(obj, "pcie4-msi-irq", &s->pcie4_msi_irq,
154 TYPE_OR_IRQ);
155
156 /*
157 * USBs
158 */
159 for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
160 snprintf(name, NAME_SIZE, "usb%d", i);
161 object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
162 }
163 }
164
fsl_imx7_realize(DeviceState * dev,Error ** errp)165 static void fsl_imx7_realize(DeviceState *dev, Error **errp)
166 {
167 MachineState *ms = MACHINE(qdev_get_machine());
168 FslIMX7State *s = FSL_IMX7(dev);
169 DeviceState *mpcore = DEVICE(&s->a7mpcore);
170 DeviceState *gic;
171 int i;
172 qemu_irq irq;
173 char name[NAME_SIZE];
174 unsigned int smp_cpus = ms->smp.cpus;
175
176 if (smp_cpus > FSL_IMX7_NUM_CPUS) {
177 error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
178 TYPE_FSL_IMX7, FSL_IMX7_NUM_CPUS, smp_cpus);
179 return;
180 }
181
182 /*
183 * CPUs
184 */
185 for (i = 0; i < smp_cpus; i++) {
186 Object *o = OBJECT(&s->cpu[i]);
187
188 /* On uniprocessor, the CBAR is set to 0 */
189 if (smp_cpus > 1) {
190 object_property_set_int(o, "reset-cbar", FSL_IMX7_A7MPCORE_ADDR,
191 &error_abort);
192 }
193
194 if (i) {
195 /*
196 * Secondary CPUs start in powered-down state (and can be
197 * powered up via the SRC system reset controller)
198 */
199 object_property_set_bool(o, "start-powered-off", true,
200 &error_abort);
201 }
202
203 qdev_realize(DEVICE(o), NULL, &error_abort);
204 }
205
206 /*
207 * A7MPCORE
208 */
209 object_property_set_int(OBJECT(mpcore), "num-cpu", smp_cpus, &error_abort);
210 object_property_set_int(OBJECT(mpcore), "num-irq",
211 FSL_IMX7_MAX_IRQ + GIC_INTERNAL, &error_abort);
212 sysbus_realize(SYS_BUS_DEVICE(mpcore), &error_abort);
213 sysbus_mmio_map(SYS_BUS_DEVICE(mpcore), 0, FSL_IMX7_A7MPCORE_ADDR);
214
215 gic = mpcore;
216 for (i = 0; i < smp_cpus; i++) {
217 SysBusDevice *sbd = SYS_BUS_DEVICE(gic);
218 DeviceState *d = DEVICE(qemu_get_cpu(i));
219
220 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
221 sysbus_connect_irq(sbd, i, irq);
222 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
223 sysbus_connect_irq(sbd, i + smp_cpus, irq);
224 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
225 sysbus_connect_irq(sbd, i + 2 * smp_cpus, irq);
226 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
227 sysbus_connect_irq(sbd, i + 3 * smp_cpus, irq);
228 }
229
230 /*
231 * A7MPCORE DAP
232 */
233 create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR,
234 FSL_IMX7_A7MPCORE_DAP_SIZE);
235
236 /*
237 * GPTs
238 */
239 for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
240 static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
241 FSL_IMX7_GPT1_ADDR,
242 FSL_IMX7_GPT2_ADDR,
243 FSL_IMX7_GPT3_ADDR,
244 FSL_IMX7_GPT4_ADDR,
245 };
246
247 static const int FSL_IMX7_GPTn_IRQ[FSL_IMX7_NUM_GPTS] = {
248 FSL_IMX7_GPT1_IRQ,
249 FSL_IMX7_GPT2_IRQ,
250 FSL_IMX7_GPT3_IRQ,
251 FSL_IMX7_GPT4_IRQ,
252 };
253
254 s->gpt[i].ccm = IMX_CCM(&s->ccm);
255 sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort);
256 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]);
257 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
258 qdev_get_gpio_in(gic, FSL_IMX7_GPTn_IRQ[i]));
259 }
260
261 /*
262 * GPIOs
263 */
264 for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
265 static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
266 FSL_IMX7_GPIO1_ADDR,
267 FSL_IMX7_GPIO2_ADDR,
268 FSL_IMX7_GPIO3_ADDR,
269 FSL_IMX7_GPIO4_ADDR,
270 FSL_IMX7_GPIO5_ADDR,
271 FSL_IMX7_GPIO6_ADDR,
272 FSL_IMX7_GPIO7_ADDR,
273 };
274
275 static const int FSL_IMX7_GPIOn_LOW_IRQ[FSL_IMX7_NUM_GPIOS] = {
276 FSL_IMX7_GPIO1_LOW_IRQ,
277 FSL_IMX7_GPIO2_LOW_IRQ,
278 FSL_IMX7_GPIO3_LOW_IRQ,
279 FSL_IMX7_GPIO4_LOW_IRQ,
280 FSL_IMX7_GPIO5_LOW_IRQ,
281 FSL_IMX7_GPIO6_LOW_IRQ,
282 FSL_IMX7_GPIO7_LOW_IRQ,
283 };
284
285 static const int FSL_IMX7_GPIOn_HIGH_IRQ[FSL_IMX7_NUM_GPIOS] = {
286 FSL_IMX7_GPIO1_HIGH_IRQ,
287 FSL_IMX7_GPIO2_HIGH_IRQ,
288 FSL_IMX7_GPIO3_HIGH_IRQ,
289 FSL_IMX7_GPIO4_HIGH_IRQ,
290 FSL_IMX7_GPIO5_HIGH_IRQ,
291 FSL_IMX7_GPIO6_HIGH_IRQ,
292 FSL_IMX7_GPIO7_HIGH_IRQ,
293 };
294
295 sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort);
296 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
297 FSL_IMX7_GPIOn_ADDR[i]);
298
299 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
300 qdev_get_gpio_in(gic, FSL_IMX7_GPIOn_LOW_IRQ[i]));
301
302 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
303 qdev_get_gpio_in(gic, FSL_IMX7_GPIOn_HIGH_IRQ[i]));
304 }
305
306 /*
307 * IOMUXC and IOMUXC_LPSR
308 */
309 create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR,
310 FSL_IMX7_IOMUXC_SIZE);
311 create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR,
312 FSL_IMX7_IOMUXC_LPSR_SIZE);
313
314 /*
315 * CCM
316 */
317 sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_abort);
318 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX7_CCM_ADDR);
319
320 /*
321 * Analog
322 */
323 sysbus_realize(SYS_BUS_DEVICE(&s->analog), &error_abort);
324 sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0, FSL_IMX7_ANALOG_ADDR);
325
326 /*
327 * GPCv2
328 */
329 sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
330 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
331
332 /*
333 * ECSPIs
334 */
335 for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
336 static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
337 FSL_IMX7_ECSPI1_ADDR,
338 FSL_IMX7_ECSPI2_ADDR,
339 FSL_IMX7_ECSPI3_ADDR,
340 FSL_IMX7_ECSPI4_ADDR,
341 };
342
343 static const int FSL_IMX7_SPIn_IRQ[FSL_IMX7_NUM_ECSPIS] = {
344 FSL_IMX7_ECSPI1_IRQ,
345 FSL_IMX7_ECSPI2_IRQ,
346 FSL_IMX7_ECSPI3_IRQ,
347 FSL_IMX7_ECSPI4_IRQ,
348 };
349
350 /* Initialize the SPI */
351 sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &error_abort);
352 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
353 FSL_IMX7_SPIn_ADDR[i]);
354 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
355 qdev_get_gpio_in(gic, FSL_IMX7_SPIn_IRQ[i]));
356 }
357
358 /*
359 * I2Cs
360 */
361 for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
362 static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = {
363 FSL_IMX7_I2C1_ADDR,
364 FSL_IMX7_I2C2_ADDR,
365 FSL_IMX7_I2C3_ADDR,
366 FSL_IMX7_I2C4_ADDR,
367 };
368
369 static const int FSL_IMX7_I2Cn_IRQ[FSL_IMX7_NUM_I2CS] = {
370 FSL_IMX7_I2C1_IRQ,
371 FSL_IMX7_I2C2_IRQ,
372 FSL_IMX7_I2C3_IRQ,
373 FSL_IMX7_I2C4_IRQ,
374 };
375
376 sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_abort);
377 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]);
378
379 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
380 qdev_get_gpio_in(gic, FSL_IMX7_I2Cn_IRQ[i]));
381 }
382
383 /*
384 * UARTs
385 */
386 for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
387 static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = {
388 FSL_IMX7_UART1_ADDR,
389 FSL_IMX7_UART2_ADDR,
390 FSL_IMX7_UART3_ADDR,
391 FSL_IMX7_UART4_ADDR,
392 FSL_IMX7_UART5_ADDR,
393 FSL_IMX7_UART6_ADDR,
394 FSL_IMX7_UART7_ADDR,
395 };
396
397 static const int FSL_IMX7_UARTn_IRQ[FSL_IMX7_NUM_UARTS] = {
398 FSL_IMX7_UART1_IRQ,
399 FSL_IMX7_UART2_IRQ,
400 FSL_IMX7_UART3_IRQ,
401 FSL_IMX7_UART4_IRQ,
402 FSL_IMX7_UART5_IRQ,
403 FSL_IMX7_UART6_IRQ,
404 FSL_IMX7_UART7_IRQ,
405 };
406
407
408 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
409
410 sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &error_abort);
411
412 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]);
413
414 irq = qdev_get_gpio_in(gic, FSL_IMX7_UARTn_IRQ[i]);
415 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, irq);
416 }
417
418 /*
419 * Ethernets
420 *
421 * We must use two loops since phy_connected affects the other interface
422 * and we have to set all properties before calling sysbus_realize().
423 */
424 for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
425 object_property_set_bool(OBJECT(&s->eth[i]), "phy-connected",
426 s->phy_connected[i], &error_abort);
427 /*
428 * If the MDIO bus on this controller is not connected, assume the
429 * other controller provides support for it.
430 */
431 if (!s->phy_connected[i]) {
432 object_property_set_link(OBJECT(&s->eth[1 - i]), "phy-consumer",
433 OBJECT(&s->eth[i]), &error_abort);
434 }
435 }
436
437 for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
438 static const hwaddr FSL_IMX7_ENETn_ADDR[FSL_IMX7_NUM_ETHS] = {
439 FSL_IMX7_ENET1_ADDR,
440 FSL_IMX7_ENET2_ADDR,
441 };
442
443 object_property_set_uint(OBJECT(&s->eth[i]), "phy-num",
444 s->phy_num[i], &error_abort);
445 object_property_set_uint(OBJECT(&s->eth[i]), "tx-ring-num",
446 FSL_IMX7_ETH_NUM_TX_RINGS, &error_abort);
447 qemu_configure_nic_device(DEVICE(&s->eth[i]), true, NULL);
448 sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort);
449
450 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]);
451
452 irq = qdev_get_gpio_in(gic, FSL_IMX7_ENET_IRQ(i, 0));
453 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, irq);
454 irq = qdev_get_gpio_in(gic, FSL_IMX7_ENET_IRQ(i, 3));
455 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, irq);
456 }
457
458 /*
459 * USDHCs
460 */
461 for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
462 static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = {
463 FSL_IMX7_USDHC1_ADDR,
464 FSL_IMX7_USDHC2_ADDR,
465 FSL_IMX7_USDHC3_ADDR,
466 };
467
468 static const int FSL_IMX7_USDHCn_IRQ[FSL_IMX7_NUM_USDHCS] = {
469 FSL_IMX7_USDHC1_IRQ,
470 FSL_IMX7_USDHC2_IRQ,
471 FSL_IMX7_USDHC3_IRQ,
472 };
473
474 sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort);
475
476 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
477 FSL_IMX7_USDHCn_ADDR[i]);
478
479 irq = qdev_get_gpio_in(gic, FSL_IMX7_USDHCn_IRQ[i]);
480 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, irq);
481 }
482
483 /*
484 * SNVS
485 */
486 sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
487 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR);
488
489 /*
490 * SRC
491 */
492 sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort);
493 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX7_SRC_ADDR);
494
495 /*
496 * Watchdogs
497 */
498 for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
499 static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = {
500 FSL_IMX7_WDOG1_ADDR,
501 FSL_IMX7_WDOG2_ADDR,
502 FSL_IMX7_WDOG3_ADDR,
503 FSL_IMX7_WDOG4_ADDR,
504 };
505 static const int FSL_IMX7_WDOGn_IRQ[FSL_IMX7_NUM_WDTS] = {
506 FSL_IMX7_WDOG1_IRQ,
507 FSL_IMX7_WDOG2_IRQ,
508 FSL_IMX7_WDOG3_IRQ,
509 FSL_IMX7_WDOG4_IRQ,
510 };
511
512 object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support",
513 true, &error_abort);
514 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);
515
516 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]);
517 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
518 qdev_get_gpio_in(gic, FSL_IMX7_WDOGn_IRQ[i]));
519 }
520
521 /*
522 * SDMA
523 */
524 create_unimplemented_device("sdma", FSL_IMX7_SDMA_ADDR, FSL_IMX7_SDMA_SIZE);
525
526 /*
527 * CAAM
528 */
529 create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
530
531 /*
532 * PWMs
533 */
534 for (i = 0; i < FSL_IMX7_NUM_PWMS; i++) {
535 static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] = {
536 FSL_IMX7_PWM1_ADDR,
537 FSL_IMX7_PWM2_ADDR,
538 FSL_IMX7_PWM3_ADDR,
539 FSL_IMX7_PWM4_ADDR,
540 };
541
542 snprintf(name, NAME_SIZE, "pwm%d", i);
543 create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i],
544 FSL_IMX7_PWMn_SIZE);
545 }
546
547 /*
548 * CANs
549 */
550 for (i = 0; i < FSL_IMX7_NUM_CANS; i++) {
551 static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] = {
552 FSL_IMX7_CAN1_ADDR,
553 FSL_IMX7_CAN2_ADDR,
554 };
555
556 snprintf(name, NAME_SIZE, "can%d", i);
557 create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i],
558 FSL_IMX7_CANn_SIZE);
559 }
560
561 /*
562 * SAIs (Audio SSI (Synchronous Serial Interface))
563 */
564 for (i = 0; i < FSL_IMX7_NUM_SAIS; i++) {
565 static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] = {
566 FSL_IMX7_SAI1_ADDR,
567 FSL_IMX7_SAI2_ADDR,
568 FSL_IMX7_SAI3_ADDR,
569 };
570
571 snprintf(name, NAME_SIZE, "sai%d", i);
572 create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i],
573 FSL_IMX7_SAIn_SIZE);
574 }
575
576 /*
577 * OCOTP
578 */
579 create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
580 FSL_IMX7_OCOTP_SIZE);
581
582 /*
583 * GPR
584 */
585 sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
586 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR);
587
588 /*
589 * PCIE
590 */
591 sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
592 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
593
594 object_property_set_int(OBJECT(&s->pcie4_msi_irq), "num-lines", 2,
595 &error_abort);
596 qdev_realize(DEVICE(&s->pcie4_msi_irq), NULL, &error_abort);
597
598 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_MSI_IRQ);
599 qdev_connect_gpio_out(DEVICE(&s->pcie4_msi_irq), 0, irq);
600
601 irq = qdev_get_gpio_in(gic, FSL_IMX7_PCI_INTA_IRQ);
602 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq);
603 irq = qdev_get_gpio_in(gic, FSL_IMX7_PCI_INTB_IRQ);
604 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq);
605 irq = qdev_get_gpio_in(gic, FSL_IMX7_PCI_INTC_IRQ);
606 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq);
607 irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 0);
608 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
609 irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 1);
610 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4, irq);
611
612 /*
613 * USBs
614 */
615 for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
616 static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = {
617 FSL_IMX7_USBMISC1_ADDR,
618 FSL_IMX7_USBMISC2_ADDR,
619 FSL_IMX7_USBMISC3_ADDR,
620 };
621
622 static const hwaddr FSL_IMX7_USBn_ADDR[FSL_IMX7_NUM_USBS] = {
623 FSL_IMX7_USB1_ADDR,
624 FSL_IMX7_USB2_ADDR,
625 FSL_IMX7_USB3_ADDR,
626 };
627
628 static const int FSL_IMX7_USBn_IRQ[FSL_IMX7_NUM_USBS] = {
629 FSL_IMX7_USB1_IRQ,
630 FSL_IMX7_USB2_IRQ,
631 FSL_IMX7_USB3_IRQ,
632 };
633
634 sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
635 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
636 FSL_IMX7_USBn_ADDR[i]);
637
638 irq = qdev_get_gpio_in(gic, FSL_IMX7_USBn_IRQ[i]);
639 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, irq);
640
641 snprintf(name, NAME_SIZE, "usbmisc%d", i);
642 create_unimplemented_device(name, FSL_IMX7_USBMISCn_ADDR[i],
643 FSL_IMX7_USBMISCn_SIZE);
644 }
645
646 /*
647 * ADCs
648 */
649 for (i = 0; i < FSL_IMX7_NUM_ADCS; i++) {
650 static const hwaddr FSL_IMX7_ADCn_ADDR[FSL_IMX7_NUM_ADCS] = {
651 FSL_IMX7_ADC1_ADDR,
652 FSL_IMX7_ADC2_ADDR,
653 };
654
655 snprintf(name, NAME_SIZE, "adc%d", i);
656 create_unimplemented_device(name, FSL_IMX7_ADCn_ADDR[i],
657 FSL_IMX7_ADCn_SIZE);
658 }
659
660 /*
661 * LCD
662 */
663 create_unimplemented_device("lcdif", FSL_IMX7_LCDIF_ADDR,
664 FSL_IMX7_LCDIF_SIZE);
665
666 /*
667 * DMA APBH
668 */
669 create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR,
670 FSL_IMX7_DMA_APBH_SIZE);
671 /*
672 * PCIe PHY
673 */
674 create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
675 FSL_IMX7_PCIE_PHY_SIZE);
676
677 /*
678 * CSU
679 */
680 create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR,
681 FSL_IMX7_CSU_SIZE);
682
683 /*
684 * TZASC
685 */
686 create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR,
687 FSL_IMX7_TZASC_SIZE);
688
689 /*
690 * OCRAM memory
691 */
692 memory_region_init_ram(&s->ocram, NULL, "imx7.ocram",
693 FSL_IMX7_OCRAM_MEM_SIZE,
694 &error_abort);
695 memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_ADDR,
696 &s->ocram);
697
698 /*
699 * OCRAM EPDC memory
700 */
701 memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc",
702 FSL_IMX7_OCRAM_EPDC_SIZE,
703 &error_abort);
704 memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_ADDR,
705 &s->ocram_epdc);
706
707 /*
708 * OCRAM PXP memory
709 */
710 memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp",
711 FSL_IMX7_OCRAM_PXP_SIZE,
712 &error_abort);
713 memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_ADDR,
714 &s->ocram_pxp);
715
716 /*
717 * OCRAM_S memory
718 */
719 memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s",
720 FSL_IMX7_OCRAM_S_SIZE,
721 &error_abort);
722 memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR,
723 &s->ocram_s);
724
725 /*
726 * ROM memory
727 */
728 memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom",
729 FSL_IMX7_ROM_SIZE, &error_abort);
730 memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR,
731 &s->rom);
732
733 /*
734 * CAAM memory
735 */
736 memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam",
737 FSL_IMX7_CAAM_MEM_SIZE, &error_abort);
738 memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADDR,
739 &s->caam);
740 }
741
742 static const Property fsl_imx7_properties[] = {
743 DEFINE_PROP_UINT32("fec1-phy-num", FslIMX7State, phy_num[0], 0),
744 DEFINE_PROP_UINT32("fec2-phy-num", FslIMX7State, phy_num[1], 1),
745 DEFINE_PROP_BOOL("fec1-phy-connected", FslIMX7State, phy_connected[0],
746 true),
747 DEFINE_PROP_BOOL("fec2-phy-connected", FslIMX7State, phy_connected[1],
748 true),
749 };
750
fsl_imx7_class_init(ObjectClass * oc,const void * data)751 static void fsl_imx7_class_init(ObjectClass *oc, const void *data)
752 {
753 DeviceClass *dc = DEVICE_CLASS(oc);
754
755 device_class_set_props(dc, fsl_imx7_properties);
756 dc->realize = fsl_imx7_realize;
757
758 /* Reason: Uses serial_hds and nd_table in realize() directly */
759 dc->user_creatable = false;
760 dc->desc = "i.MX7 SOC";
761 }
762
763 static const TypeInfo fsl_imx7_type_info = {
764 .name = TYPE_FSL_IMX7,
765 .parent = TYPE_DEVICE,
766 .instance_size = sizeof(FslIMX7State),
767 .instance_init = fsl_imx7_init,
768 .class_init = fsl_imx7_class_init,
769 };
770
fsl_imx7_register_types(void)771 static void fsl_imx7_register_types(void)
772 {
773 type_register_static(&fsl_imx7_type_info);
774 }
775 type_init(fsl_imx7_register_types)
776