1 /*
2 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
3 *
4 * i.MX6 SOC emulation.
5 *
6 * Based on hw/arm/fsl-imx31.c
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "hw/arm/fsl-imx6.h"
25 #include "hw/misc/unimp.h"
26 #include "hw/usb/imx-usb-phy.h"
27 #include "hw/boards.h"
28 #include "hw/qdev-properties.h"
29 #include "system/system.h"
30 #include "chardev/char.h"
31 #include "qemu/error-report.h"
32 #include "qemu/module.h"
33 #include "target/arm/cpu-qom.h"
34
35 #define IMX6_ESDHC_CAPABILITIES 0x057834b4
36
37 #define NAME_SIZE 20
38
fsl_imx6_init(Object * obj)39 static void fsl_imx6_init(Object *obj)
40 {
41 MachineState *ms = MACHINE(qdev_get_machine());
42 FslIMX6State *s = FSL_IMX6(obj);
43 char name[NAME_SIZE];
44 int i;
45
46 for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) {
47 snprintf(name, NAME_SIZE, "cpu%d", i);
48 object_initialize_child(obj, name, &s->cpu[i],
49 ARM_CPU_TYPE_NAME("cortex-a9"));
50 }
51
52 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
53
54 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6_CCM);
55
56 object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC);
57
58 object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
59
60 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
61 snprintf(name, NAME_SIZE, "uart%d", i + 1);
62 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
63 }
64
65 object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX6_GPT);
66
67 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
68 snprintf(name, NAME_SIZE, "epit%d", i + 1);
69 object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT);
70 }
71
72 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
73 snprintf(name, NAME_SIZE, "i2c%d", i + 1);
74 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
75 }
76
77 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
78 snprintf(name, NAME_SIZE, "gpio%d", i + 1);
79 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
80 }
81
82 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
83 snprintf(name, NAME_SIZE, "sdhc%d", i + 1);
84 object_initialize_child(obj, name, &s->esdhc[i], TYPE_IMX_USDHC);
85 }
86
87 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
88 snprintf(name, NAME_SIZE, "usbphy%d", i);
89 object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
90 }
91 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
92 snprintf(name, NAME_SIZE, "usb%d", i);
93 object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
94 }
95
96 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
97 snprintf(name, NAME_SIZE, "spi%d", i + 1);
98 object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
99 }
100 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) {
101 snprintf(name, NAME_SIZE, "wdt%d", i);
102 object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
103 }
104
105
106 object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET);
107
108 object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
109 object_initialize_child(obj, "pcie4-msi-irq", &s->pcie4_msi_irq,
110 TYPE_OR_IRQ);
111 }
112
fsl_imx6_realize(DeviceState * dev,Error ** errp)113 static void fsl_imx6_realize(DeviceState *dev, Error **errp)
114 {
115 MachineState *ms = MACHINE(qdev_get_machine());
116 FslIMX6State *s = FSL_IMX6(dev);
117 uint16_t i;
118 qemu_irq irq;
119 unsigned int smp_cpus = ms->smp.cpus;
120 DeviceState *mpcore = DEVICE(&s->a9mpcore);
121 DeviceState *gic;
122
123 if (smp_cpus > FSL_IMX6_NUM_CPUS) {
124 error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
125 TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus);
126 return;
127 }
128
129 for (i = 0; i < smp_cpus; i++) {
130
131 /* On uniprocessor, the CBAR is set to 0 */
132 if (smp_cpus > 1) {
133 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
134 FSL_IMX6_A9MPCORE_ADDR, &error_abort);
135 }
136
137 /* All CPU but CPU 0 start in power off mode */
138 if (i) {
139 object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-off",
140 true, &error_abort);
141 }
142
143 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
144 return;
145 }
146 }
147
148 object_property_set_int(OBJECT(mpcore), "num-cpu", smp_cpus, &error_abort);
149
150 object_property_set_int(OBJECT(mpcore), "num-irq",
151 FSL_IMX6_MAX_IRQ + GIC_INTERNAL, &error_abort);
152
153 if (!sysbus_realize(SYS_BUS_DEVICE(mpcore), errp)) {
154 return;
155 }
156 sysbus_mmio_map(SYS_BUS_DEVICE(mpcore), 0, FSL_IMX6_A9MPCORE_ADDR);
157
158 gic = mpcore;
159 for (i = 0; i < smp_cpus; i++) {
160 sysbus_connect_irq(SYS_BUS_DEVICE(gic), i,
161 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
162 sysbus_connect_irq(SYS_BUS_DEVICE(gic), i + smp_cpus,
163 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
164 }
165
166 /* L2 cache controller */
167 sysbus_create_simple("l2x0", FSL_IMX6_PL310_ADDR, NULL);
168
169 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) {
170 return;
171 }
172 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR);
173
174 if (!sysbus_realize(SYS_BUS_DEVICE(&s->src), errp)) {
175 return;
176 }
177 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR);
178
179 /* Initialize all UARTs */
180 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
181 static const struct {
182 hwaddr addr;
183 unsigned int irq;
184 } serial_table[FSL_IMX6_NUM_UARTS] = {
185 { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ },
186 { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ },
187 { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ },
188 { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ },
189 { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ },
190 };
191
192 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
193
194 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) {
195 return;
196 }
197
198 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
199 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
200 qdev_get_gpio_in(gic, serial_table[i].irq));
201 }
202
203 s->gpt.ccm = IMX_CCM(&s->ccm);
204
205 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), errp)) {
206 return;
207 }
208
209 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR);
210 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
211 qdev_get_gpio_in(gic, FSL_IMX6_GPT_IRQ));
212
213 /* Initialize all EPIT timers */
214 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
215 static const struct {
216 hwaddr addr;
217 unsigned int irq;
218 } epit_table[FSL_IMX6_NUM_EPITS] = {
219 { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ },
220 { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ },
221 };
222
223 s->epit[i].ccm = IMX_CCM(&s->ccm);
224
225 if (!sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), errp)) {
226 return;
227 }
228
229 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
230 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
231 qdev_get_gpio_in(gic, epit_table[i].irq));
232 }
233
234 /* Initialize all I2C */
235 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
236 static const struct {
237 hwaddr addr;
238 unsigned int irq;
239 } i2c_table[FSL_IMX6_NUM_I2CS] = {
240 { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ },
241 { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ },
242 { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ }
243 };
244
245 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) {
246 return;
247 }
248
249 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
250 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
251 qdev_get_gpio_in(gic, i2c_table[i].irq));
252 }
253
254 /* Initialize all GPIOs */
255 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
256 static const struct {
257 hwaddr addr;
258 unsigned int irq_low;
259 unsigned int irq_high;
260 } gpio_table[FSL_IMX6_NUM_GPIOS] = {
261 {
262 FSL_IMX6_GPIO1_ADDR,
263 FSL_IMX6_GPIO1_LOW_IRQ,
264 FSL_IMX6_GPIO1_HIGH_IRQ
265 },
266 {
267 FSL_IMX6_GPIO2_ADDR,
268 FSL_IMX6_GPIO2_LOW_IRQ,
269 FSL_IMX6_GPIO2_HIGH_IRQ
270 },
271 {
272 FSL_IMX6_GPIO3_ADDR,
273 FSL_IMX6_GPIO3_LOW_IRQ,
274 FSL_IMX6_GPIO3_HIGH_IRQ
275 },
276 {
277 FSL_IMX6_GPIO4_ADDR,
278 FSL_IMX6_GPIO4_LOW_IRQ,
279 FSL_IMX6_GPIO4_HIGH_IRQ
280 },
281 {
282 FSL_IMX6_GPIO5_ADDR,
283 FSL_IMX6_GPIO5_LOW_IRQ,
284 FSL_IMX6_GPIO5_HIGH_IRQ
285 },
286 {
287 FSL_IMX6_GPIO6_ADDR,
288 FSL_IMX6_GPIO6_LOW_IRQ,
289 FSL_IMX6_GPIO6_HIGH_IRQ
290 },
291 {
292 FSL_IMX6_GPIO7_ADDR,
293 FSL_IMX6_GPIO7_LOW_IRQ,
294 FSL_IMX6_GPIO7_HIGH_IRQ
295 },
296 };
297
298 object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true,
299 &error_abort);
300 object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq",
301 true, &error_abort);
302 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) {
303 return;
304 }
305
306 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
307 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
308 qdev_get_gpio_in(gic, gpio_table[i].irq_low));
309 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
310 qdev_get_gpio_in(gic, gpio_table[i].irq_high));
311 }
312
313 /* Initialize all SDHC */
314 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
315 static const struct {
316 hwaddr addr;
317 unsigned int irq;
318 } esdhc_table[FSL_IMX6_NUM_ESDHCS] = {
319 { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ },
320 { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ },
321 { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ },
322 { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ },
323 };
324
325 /* UHS-I SDIO3.0 SDR104 1.8V ADMA */
326 object_property_set_uint(OBJECT(&s->esdhc[i]), "sd-spec-version", 3,
327 &error_abort);
328 object_property_set_uint(OBJECT(&s->esdhc[i]), "capareg",
329 IMX6_ESDHC_CAPABILITIES, &error_abort);
330 if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), errp)) {
331 return;
332 }
333 sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
334 sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
335 qdev_get_gpio_in(gic, esdhc_table[i].irq));
336 }
337
338 /* USB */
339 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
340 sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
341 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
342 FSL_IMX6_USBPHY1_ADDR + i * 0x1000);
343 }
344 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
345 static const int FSL_IMX6_USBn_IRQ[] = {
346 FSL_IMX6_USB_OTG_IRQ,
347 FSL_IMX6_USB_HOST1_IRQ,
348 FSL_IMX6_USB_HOST2_IRQ,
349 FSL_IMX6_USB_HOST3_IRQ,
350 };
351
352 sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
353 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
354 FSL_IMX6_USBOH3_USB_ADDR + i * 0x200);
355 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
356 qdev_get_gpio_in(gic, FSL_IMX6_USBn_IRQ[i]));
357 }
358
359 /* Initialize all ECSPI */
360 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
361 static const struct {
362 hwaddr addr;
363 unsigned int irq;
364 } spi_table[FSL_IMX6_NUM_ECSPIS] = {
365 { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ },
366 { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ },
367 { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ },
368 { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ },
369 { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ },
370 };
371
372 /* Initialize the SPI */
373 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
374 return;
375 }
376
377 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
378 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
379 qdev_get_gpio_in(gic, spi_table[i].irq));
380 }
381
382 object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num,
383 &error_abort);
384 qemu_configure_nic_device(DEVICE(&s->eth), true, NULL);
385 if (!sysbus_realize(SYS_BUS_DEVICE(&s->eth), errp)) {
386 return;
387 }
388 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR);
389 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0,
390 qdev_get_gpio_in(gic, FSL_IMX6_ENET_MAC_IRQ));
391 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1,
392 qdev_get_gpio_in(gic, FSL_IMX6_ENET_MAC_1588_IRQ));
393
394 /*
395 * SNVS
396 */
397 sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
398 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6_SNVSHP_ADDR);
399
400 /*
401 * Watchdog
402 */
403 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) {
404 static const hwaddr FSL_IMX6_WDOGn_ADDR[FSL_IMX6_NUM_WDTS] = {
405 FSL_IMX6_WDOG1_ADDR,
406 FSL_IMX6_WDOG2_ADDR,
407 };
408 static const int FSL_IMX6_WDOGn_IRQ[FSL_IMX6_NUM_WDTS] = {
409 FSL_IMX6_WDOG1_IRQ,
410 FSL_IMX6_WDOG2_IRQ,
411 };
412
413 object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support",
414 true, &error_abort);
415 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);
416
417 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]);
418 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
419 qdev_get_gpio_in(gic, FSL_IMX6_WDOGn_IRQ[i]));
420 }
421
422 /*
423 * PCIe
424 */
425 sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
426 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX6_PCIe_REG_ADDR);
427
428 object_property_set_int(OBJECT(&s->pcie4_msi_irq), "num-lines", 2,
429 &error_abort);
430 qdev_realize(DEVICE(&s->pcie4_msi_irq), NULL, &error_abort);
431
432 irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE4_MSI_IRQ);
433 qdev_connect_gpio_out(DEVICE(&s->pcie4_msi_irq), 0, irq);
434
435 irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE1_IRQ);
436 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq);
437 irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE2_IRQ);
438 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq);
439 irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE3_IRQ);
440 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq);
441 irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 0);
442 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
443 irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 1);
444 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4, irq);
445
446 /*
447 * PCIe PHY
448 */
449 create_unimplemented_device("pcie-phy", FSL_IMX6_PCIe_ADDR,
450 FSL_IMX6_PCIe_SIZE);
451
452 /* ROM memory */
453 if (!memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom",
454 FSL_IMX6_ROM_SIZE, errp)) {
455 return;
456 }
457 memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR,
458 &s->rom);
459
460 /* CAAM memory */
461 if (!memory_region_init_rom(&s->caam, OBJECT(dev), "imx6.caam",
462 FSL_IMX6_CAAM_MEM_SIZE, errp)) {
463 return;
464 }
465 memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR,
466 &s->caam);
467
468 /* OCRAM memory */
469 if (!memory_region_init_ram(&s->ocram, NULL, "imx6.ocram",
470 FSL_IMX6_OCRAM_SIZE, errp)) {
471 return;
472 }
473 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR,
474 &s->ocram);
475
476 /* internal OCRAM (256 KB) is aliased over 1 MB */
477 memory_region_init_alias(&s->ocram_alias, OBJECT(dev), "imx6.ocram_alias",
478 &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE);
479 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR,
480 &s->ocram_alias);
481 }
482
483 static const Property fsl_imx6_properties[] = {
484 DEFINE_PROP_UINT32("fec-phy-num", FslIMX6State, phy_num, 0),
485 };
486
fsl_imx6_class_init(ObjectClass * oc,const void * data)487 static void fsl_imx6_class_init(ObjectClass *oc, const void *data)
488 {
489 DeviceClass *dc = DEVICE_CLASS(oc);
490
491 device_class_set_props(dc, fsl_imx6_properties);
492 dc->realize = fsl_imx6_realize;
493 dc->desc = "i.MX6 SOC";
494 /* Reason: Uses serial_hd() in the realize() function */
495 dc->user_creatable = false;
496 }
497
498 static const TypeInfo fsl_imx6_type_info = {
499 .name = TYPE_FSL_IMX6,
500 .parent = TYPE_DEVICE,
501 .instance_size = sizeof(FslIMX6State),
502 .instance_init = fsl_imx6_init,
503 .class_init = fsl_imx6_class_init,
504 };
505
fsl_imx6_register_types(void)506 static void fsl_imx6_register_types(void)
507 {
508 type_register_static(&fsl_imx6_type_info);
509 }
510
511 type_init(fsl_imx6_register_types)
512