1 /*
2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
3 *
4 * i.MX25 SOC emulation.
5 *
6 * Based on hw/arm/xlnx-zynqmp.c
7 *
8 * Copyright (C) 2015 Xilinx Inc
9 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
27 #include "hw/arm/fsl-imx25.h"
28 #include "system/system.h"
29 #include "hw/qdev-properties.h"
30 #include "chardev/char.h"
31 #include "target/arm/cpu-qom.h"
32
33 #define IMX25_ESDHC_CAPABILITIES 0x07e20000
34
fsl_imx25_init(Object * obj)35 static void fsl_imx25_init(Object *obj)
36 {
37 FslIMX25State *s = FSL_IMX25(obj);
38 int i;
39
40 object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm926"));
41
42 object_initialize_child(obj, "avic", &s->avic, TYPE_IMX_AVIC);
43
44 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX25_CCM);
45
46 for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
47 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_IMX_SERIAL);
48 }
49
50 for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
51 object_initialize_child(obj, "gpt[*]", &s->gpt[i], TYPE_IMX25_GPT);
52 }
53
54 for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
55 object_initialize_child(obj, "epit[*]", &s->epit[i], TYPE_IMX_EPIT);
56 }
57
58 object_initialize_child(obj, "fec", &s->fec, TYPE_IMX_FEC);
59
60 object_initialize_child(obj, "rngc", &s->rngc, TYPE_IMX_RNGC);
61
62 for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
63 object_initialize_child(obj, "i2c[*]", &s->i2c[i], TYPE_IMX_I2C);
64 }
65
66 for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
67 object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_IMX_GPIO);
68 }
69
70 for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
71 object_initialize_child(obj, "sdhc[*]", &s->esdhc[i], TYPE_IMX_USDHC);
72 }
73
74 for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
75 object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_CHIPIDEA);
76 }
77
78 object_initialize_child(obj, "wdt", &s->wdt, TYPE_IMX2_WDT);
79 }
80
fsl_imx25_realize(DeviceState * dev,Error ** errp)81 static void fsl_imx25_realize(DeviceState *dev, Error **errp)
82 {
83 FslIMX25State *s = FSL_IMX25(dev);
84 uint8_t i;
85
86 if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
87 return;
88 }
89
90 if (!sysbus_realize(SYS_BUS_DEVICE(&s->avic), errp)) {
91 return;
92 }
93 sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR);
94 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
95 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
96 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
97 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
98
99 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) {
100 return;
101 }
102 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR);
103
104 /* Initialize all UARTs */
105 for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
106 static const struct {
107 hwaddr addr;
108 unsigned int irq;
109 } serial_table[FSL_IMX25_NUM_UARTS] = {
110 { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ },
111 { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ },
112 { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ },
113 { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ },
114 { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ }
115 };
116
117 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
118
119 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) {
120 return;
121 }
122 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
123 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
124 qdev_get_gpio_in(DEVICE(&s->avic),
125 serial_table[i].irq));
126 }
127
128 /* Initialize all GPT timers */
129 for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
130 static const struct {
131 hwaddr addr;
132 unsigned int irq;
133 } gpt_table[FSL_IMX25_NUM_GPTS] = {
134 { FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ },
135 { FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ },
136 { FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ },
137 { FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ }
138 };
139
140 s->gpt[i].ccm = IMX_CCM(&s->ccm);
141
142 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), errp)) {
143 return;
144 }
145 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr);
146 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
147 qdev_get_gpio_in(DEVICE(&s->avic),
148 gpt_table[i].irq));
149 }
150
151 /* Initialize all EPIT timers */
152 for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
153 static const struct {
154 hwaddr addr;
155 unsigned int irq;
156 } epit_table[FSL_IMX25_NUM_EPITS] = {
157 { FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ },
158 { FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ }
159 };
160
161 s->epit[i].ccm = IMX_CCM(&s->ccm);
162
163 if (!sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), errp)) {
164 return;
165 }
166 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
167 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
168 qdev_get_gpio_in(DEVICE(&s->avic),
169 epit_table[i].irq));
170 }
171
172 object_property_set_uint(OBJECT(&s->fec), "phy-num", s->phy_num,
173 &error_abort);
174 qemu_configure_nic_device(DEVICE(&s->fec), true, NULL);
175
176 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fec), errp)) {
177 return;
178 }
179 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR);
180 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
181 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));
182
183 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rngc), errp)) {
184 return;
185 }
186 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rngc), 0, FSL_IMX25_RNGC_ADDR);
187 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rngc), 0,
188 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_RNGC_IRQ));
189
190 /* Initialize all I2C */
191 for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
192 static const struct {
193 hwaddr addr;
194 unsigned int irq;
195 } i2c_table[FSL_IMX25_NUM_I2CS] = {
196 { FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ },
197 { FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ },
198 { FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ }
199 };
200
201 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) {
202 return;
203 }
204 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
205 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
206 qdev_get_gpio_in(DEVICE(&s->avic),
207 i2c_table[i].irq));
208 }
209
210 /* Initialize all GPIOs */
211 for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
212 static const struct {
213 hwaddr addr;
214 unsigned int irq;
215 } gpio_table[FSL_IMX25_NUM_GPIOS] = {
216 { FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ },
217 { FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ },
218 { FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ },
219 { FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ }
220 };
221
222 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) {
223 return;
224 }
225 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
226 /* Connect GPIO IRQ to PIC */
227 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
228 qdev_get_gpio_in(DEVICE(&s->avic),
229 gpio_table[i].irq));
230 }
231
232 /* Initialize all SDHC */
233 for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
234 static const struct {
235 hwaddr addr;
236 unsigned int irq;
237 } esdhc_table[FSL_IMX25_NUM_ESDHCS] = {
238 { FSL_IMX25_ESDHC1_ADDR, FSL_IMX25_ESDHC1_IRQ },
239 { FSL_IMX25_ESDHC2_ADDR, FSL_IMX25_ESDHC2_IRQ },
240 };
241
242 object_property_set_uint(OBJECT(&s->esdhc[i]), "sd-spec-version", 2,
243 &error_abort);
244 object_property_set_uint(OBJECT(&s->esdhc[i]), "capareg",
245 IMX25_ESDHC_CAPABILITIES, &error_abort);
246 if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), errp)) {
247 return;
248 }
249 sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
250 sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
251 qdev_get_gpio_in(DEVICE(&s->avic),
252 esdhc_table[i].irq));
253 }
254
255 /* USB */
256 for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
257 static const struct {
258 hwaddr addr;
259 unsigned int irq;
260 } usb_table[FSL_IMX25_NUM_USBS] = {
261 { FSL_IMX25_USB1_ADDR, FSL_IMX25_USB1_IRQ },
262 { FSL_IMX25_USB2_ADDR, FSL_IMX25_USB2_IRQ },
263 };
264
265 sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
266 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr);
267 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
268 qdev_get_gpio_in(DEVICE(&s->avic),
269 usb_table[i].irq));
270 }
271
272 /* Watchdog */
273 object_property_set_bool(OBJECT(&s->wdt), "pretimeout-support", true,
274 &error_abort);
275 sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_abort);
276 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX25_WDT_ADDR);
277 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt), 0,
278 qdev_get_gpio_in(DEVICE(&s->avic),
279 FSL_IMX25_WDT_IRQ));
280
281 /* initialize 2 x 16 KB ROM */
282 if (!memory_region_init_rom(&s->rom[0], OBJECT(dev), "imx25.rom0",
283 FSL_IMX25_ROM0_SIZE, errp)) {
284 return;
285 }
286 memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR,
287 &s->rom[0]);
288 if (!memory_region_init_rom(&s->rom[1], OBJECT(dev), "imx25.rom1",
289 FSL_IMX25_ROM1_SIZE, errp)) {
290 return;
291 }
292 memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR,
293 &s->rom[1]);
294
295 /* initialize internal RAM (128 KB) */
296 if (!memory_region_init_ram(&s->iram, NULL, "imx25.iram",
297 FSL_IMX25_IRAM_SIZE, errp)) {
298 return;
299 }
300 memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR,
301 &s->iram);
302
303 /* internal RAM (128 KB) is aliased over 128 MB - 128 KB */
304 memory_region_init_alias(&s->iram_alias, OBJECT(dev), "imx25.iram_alias",
305 &s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE);
306 memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR,
307 &s->iram_alias);
308 }
309
310 static const Property fsl_imx25_properties[] = {
311 DEFINE_PROP_UINT32("fec-phy-num", FslIMX25State, phy_num, 0),
312 };
313
fsl_imx25_class_init(ObjectClass * oc,const void * data)314 static void fsl_imx25_class_init(ObjectClass *oc, const void *data)
315 {
316 DeviceClass *dc = DEVICE_CLASS(oc);
317
318 device_class_set_props(dc, fsl_imx25_properties);
319 dc->realize = fsl_imx25_realize;
320 dc->desc = "i.MX25 SOC";
321 /*
322 * Reason: uses serial_hds in realize and the imx25 board does not
323 * support multiple CPUs
324 */
325 dc->user_creatable = false;
326 }
327
328 static const TypeInfo fsl_imx25_type_info = {
329 .name = TYPE_FSL_IMX25,
330 .parent = TYPE_DEVICE,
331 .instance_size = sizeof(FslIMX25State),
332 .instance_init = fsl_imx25_init,
333 .class_init = fsl_imx25_class_init,
334 };
335
fsl_imx25_register_types(void)336 static void fsl_imx25_register_types(void)
337 {
338 type_register_static(&fsl_imx25_type_info);
339 }
340
341 type_init(fsl_imx25_register_types)
342