1// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 2/* 3* Copyright 2023 Mobileye Vision Technologies Ltd. 4*/ 5 6#include <dt-bindings/interrupt-controller/mips-gic.h> 7 8#include <dt-bindings/clock/mobileye,eyeq5-clk.h> 9 10/ { 11 #address-cells = <2>; 12 #size-cells = <2>; 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 cpu@0 { 17 device_type = "cpu"; 18 compatible = "img,i6500"; 19 reg = <0>; 20 clocks = <&olb EQ5C_CPU_CORE0>; 21 }; 22 }; 23 24 reserved-memory { 25 #address-cells = <2>; 26 #size-cells = <2>; 27 ranges; 28 29 /* These reserved memory regions are also defined in bootmanager 30 * for configuring inbound translation for BARS, don't change 31 * these without syncing with bootmanager 32 */ 33 shmem0_reserved: shmem@804000000 { 34 reg = <0x8 0x04000000 0x0 0x1000000>; 35 }; 36 shmem1_reserved: shmem@805000000 { 37 reg = <0x8 0x05000000 0x0 0x1000000>; 38 }; 39 pci0_msi_reserved: pci0-msi@806000000 { 40 reg = <0x8 0x06000000 0x0 0x100000>; 41 }; 42 pci1_msi_reserved: pci1-msi@806100000 { 43 reg = <0x8 0x06100000 0x0 0x100000>; 44 }; 45 46 mini_coredump0_reserved: mini-coredump0@806200000 { 47 reg = <0x8 0x06200000 0x0 0x100000>; 48 }; 49 mhm_reserved_0: the-mhm-reserved-0@0 { 50 reg = <0x8 0x00000000 0x0 0x0000800>; 51 }; 52 53 nvram@461fe00 { 54 compatible = "mobileye,eyeq5-bootloader-config", "nvmem-rmem"; 55 reg = <0x0 0x0461fe00 0x0 0x200>; 56 #address-cells = <1>; 57 #size-cells = <1>; 58 no-map; 59 60 nvmem-layout { 61 compatible = "fixed-layout"; 62 #address-cells = <1>; 63 #size-cells = <1>; 64 65 eth0_mac: mac@7c { 66 reg = <0x7c 0x6>; 67 }; 68 69 eth1_mac: mac@82 { 70 reg = <0x82 0x6>; 71 }; 72 }; 73 }; 74 }; 75 76 aliases { 77 serial0 = &uart0; 78 serial1 = &uart1; 79 serial2 = &uart2; 80 }; 81 82 cpu_intc: interrupt-controller { 83 compatible = "mti,cpu-interrupt-controller"; 84 interrupt-controller; 85 #address-cells = <0>; 86 #interrupt-cells = <1>; 87 }; 88 89 xtal: xtal { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <30000000>; 93 }; 94 95 pclk: pclk { 96 compatible = "fixed-clock"; 97 #clock-cells = <0>; 98 clock-frequency = <250000000>; /* 250MHz */ 99 }; 100 101 tsu_clk: tsu-clk { 102 compatible = "fixed-clock"; 103 #clock-cells = <0>; 104 clock-frequency = <125000000>; /* 125MHz */ 105 }; 106 107 soc: soc { 108 #address-cells = <2>; 109 #size-cells = <2>; 110 ranges; 111 compatible = "simple-bus"; 112 113 i2c0: i2c@300000 { 114 compatible = "mobileye,eyeq5-i2c", "arm,primecell"; 115 reg = <0 0x300000 0x0 0x1000>; 116 interrupt-parent = <&gic>; 117 interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>; 118 clock-frequency = <400000>; /* Fast mode */ 119 #address-cells = <1>; 120 #size-cells = <0>; 121 clocks = <&olb 35>, <&olb EQ5C_PER_I2C>; 122 clock-names = "i2cclk", "apb_pclk"; 123 resets = <&olb 0 13>; 124 i2c-transfer-timeout-us = <10000>; 125 mobileye,olb = <&olb 0>; 126 }; 127 128 i2c1: i2c@400000 { 129 compatible = "mobileye,eyeq5-i2c", "arm,primecell"; 130 reg = <0 0x400000 0x0 0x1000>; 131 interrupt-parent = <&gic>; 132 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; 133 clock-frequency = <400000>; /* Fast mode */ 134 #address-cells = <1>; 135 #size-cells = <0>; 136 clocks = <&olb 35>, <&olb EQ5C_PER_I2C>; 137 clock-names = "i2cclk", "apb_pclk"; 138 resets = <&olb 0 14>; 139 i2c-transfer-timeout-us = <10000>; 140 mobileye,olb = <&olb 1>; 141 }; 142 143 i2c2: i2c@500000 { 144 compatible = "mobileye,eyeq5-i2c", "arm,primecell"; 145 reg = <0 0x500000 0x0 0x1000>; 146 interrupt-parent = <&gic>; 147 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; 148 clock-frequency = <400000>; /* Fast mode */ 149 #address-cells = <1>; 150 #size-cells = <0>; 151 clocks = <&olb 35>, <&olb EQ5C_PER_I2C>; 152 clock-names = "i2cclk", "apb_pclk"; 153 resets = <&olb 0 15>; 154 i2c-transfer-timeout-us = <10000>; 155 mobileye,olb = <&olb 2>; 156 }; 157 158 i2c3: i2c@600000 { 159 compatible = "mobileye,eyeq5-i2c", "arm,primecell"; 160 reg = <0 0x600000 0x0 0x1000>; 161 interrupt-parent = <&gic>; 162 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; 163 clock-frequency = <400000>; /* Fast mode */ 164 #address-cells = <1>; 165 #size-cells = <0>; 166 clocks = <&olb 35>, <&olb EQ5C_PER_I2C>; 167 clock-names = "i2cclk", "apb_pclk"; 168 resets = <&olb 0 16>; 169 i2c-transfer-timeout-us = <10000>; 170 mobileye,olb = <&olb 3>; 171 }; 172 173 i2c4: i2c@700000 { 174 compatible = "mobileye,eyeq5-i2c", "arm,primecell"; 175 reg = <0 0x700000 0x0 0x1000>; 176 interrupt-parent = <&gic>; 177 interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>; 178 clock-frequency = <400000>; /* Fast mode */ 179 #address-cells = <1>; 180 #size-cells = <0>; 181 clocks = <&olb 35>, <&olb EQ5C_PER_I2C>; 182 clock-names = "i2cclk", "apb_pclk"; 183 resets = <&olb 0 17>; 184 i2c-transfer-timeout-us = <10000>; 185 mobileye,olb = <&olb 4>; 186 }; 187 188 uart0: serial@800000 { 189 compatible = "arm,pl011", "arm,primecell"; 190 reg = <0 0x800000 0x0 0x1000>; 191 reg-io-width = <4>; 192 interrupt-parent = <&gic>; 193 interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; 194 clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; 195 clock-names = "uartclk", "apb_pclk"; 196 resets = <&olb 0 10>; 197 pinctrl-names = "default"; 198 pinctrl-0 = <&uart0_pins>; 199 }; 200 201 uart1: serial@900000 { 202 compatible = "arm,pl011", "arm,primecell"; 203 reg = <0 0x900000 0x0 0x1000>; 204 reg-io-width = <4>; 205 interrupt-parent = <&gic>; 206 interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; 208 clock-names = "uartclk", "apb_pclk"; 209 resets = <&olb 0 11>; 210 pinctrl-names = "default"; 211 pinctrl-0 = <&uart1_pins>; 212 }; 213 214 uart2: serial@a00000 { 215 compatible = "arm,pl011", "arm,primecell"; 216 reg = <0 0xa00000 0x0 0x1000>; 217 reg-io-width = <4>; 218 interrupt-parent = <&gic>; 219 interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; 221 clock-names = "uartclk", "apb_pclk"; 222 resets = <&olb 0 12>; 223 pinctrl-names = "default"; 224 pinctrl-0 = <&uart2_pins>; 225 }; 226 227 olb: system-controller@e00000 { 228 compatible = "mobileye,eyeq5-olb", "syscon"; 229 reg = <0 0xe00000 0x0 0x400>; 230 #reset-cells = <2>; 231 #clock-cells = <1>; 232 clocks = <&xtal>; 233 clock-names = "ref"; 234 }; 235 236 gic: interrupt-controller@140000 { 237 compatible = "mti,gic"; 238 reg = <0x0 0x140000 0x0 0x20000>; 239 interrupt-controller; 240 #interrupt-cells = <3>; 241 242 /* 243 * Declare the interrupt-parent even though the mti,gic 244 * binding doesn't require it, such that the kernel can 245 * figure out that cpu_intc is the root interrupt 246 * controller & should be probed first. 247 */ 248 interrupt-parent = <&cpu_intc>; 249 250 timer { 251 compatible = "mti,gic-timer"; 252 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; 253 clocks = <&olb EQ5C_CPU_CORE0>; 254 }; 255 }; 256 257 emmc: mmc@2200000 { 258 compatible = "mobileye,eyeq-sd4hc", "cdns,sd4hc"; 259 reg = <0 0x2200000 0x0 0x1000>; 260 interrupt-parent = <&gic>; 261 interrupts = <GIC_SHARED 10 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&olb EQ5C_PER_EMMC>; 263 bus-width = <8>; 264 max-frequency = <200000000>; 265 mmc-ddr-1_8v; 266 sd-uhs-ddr50; 267 mmc-hs200-1_8v; 268 mmc-hs400-1_8v; 269 mmc-hs400-enhanced-strobe; 270 271 cdns,phy-input-delay-legacy = <4>; 272 cdns,phy-input-delay-mmc-highspeed = <2>; 273 cdns,phy-input-delay-mmc-ddr = <3>; 274 cdns,phy-dll-delay-sdclk = <32>; 275 cdns,phy-dll-delay-sdclk-hsmmc = <32>; 276 cdns,phy-dll-delay-strobe = <32>; 277 }; 278 279 gpio0: gpio@1400000 { 280 compatible = "mobileye,eyeq5-gpio"; 281 reg = <0x0 0x1400000 0x0 0x1000>; 282 gpio-bank = <0>; 283 ngpios = <29>; 284 interrupt-parent = <&gic>; 285 interrupts = <GIC_SHARED 14 IRQ_TYPE_LEVEL_HIGH>; 286 gpio-controller; 287 #gpio-cells = <2>; 288 gpio-ranges = <&olb 0 0 29>; 289 interrupt-controller; 290 #interrupt-cells = <2>; 291 resets = <&olb 0 26>; 292 }; 293 294 gpio1: gpio@1500000 { 295 compatible = "mobileye,eyeq5-gpio"; 296 reg = <0x0 0x1500000 0x0 0x1000>; 297 gpio-bank = <1>; 298 ngpios = <23>; 299 interrupt-parent = <&gic>; 300 interrupts = <GIC_SHARED 14 IRQ_TYPE_LEVEL_HIGH>; 301 gpio-controller; 302 #gpio-cells = <2>; 303 gpio-ranges = <&olb 0 29 23>; 304 interrupt-controller; 305 #interrupt-cells = <2>; 306 resets = <&olb 0 26>; 307 }; 308 }; 309}; 310 311#include "eyeq5-pins.dtsi" 312