1 /**
2 * dwc3-omap.c - OMAP Specific Glue layer
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #include <linux/module.h>
40 #include <linux/kernel.h>
41 #include <linux/slab.h>
42 #include <linux/interrupt.h>
43 #include <linux/spinlock.h>
44 #include <linux/platform_device.h>
45 #include <linux/platform_data/dwc3-omap.h>
46 #include <linux/dma-mapping.h>
47 #include <linux/ioport.h>
48 #include <linux/io.h>
49 #include <linux/module.h>
50
51 #include "core.h"
52 #include "io.h"
53
54 /*
55 * All these registers belong to OMAP's Wrapper around the
56 * DesignWare USB3 Core.
57 */
58
59 #define USBOTGSS_REVISION 0x0000
60 #define USBOTGSS_SYSCONFIG 0x0010
61 #define USBOTGSS_IRQ_EOI 0x0020
62 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024
63 #define USBOTGSS_IRQSTATUS_0 0x0028
64 #define USBOTGSS_IRQENABLE_SET_0 0x002c
65 #define USBOTGSS_IRQENABLE_CLR_0 0x0030
66 #define USBOTGSS_IRQSTATUS_RAW_1 0x0034
67 #define USBOTGSS_IRQSTATUS_1 0x0038
68 #define USBOTGSS_IRQENABLE_SET_1 0x003c
69 #define USBOTGSS_IRQENABLE_CLR_1 0x0040
70 #define USBOTGSS_UTMI_OTG_CTRL 0x0080
71 #define USBOTGSS_UTMI_OTG_STATUS 0x0084
72 #define USBOTGSS_MMRAM_OFFSET 0x0100
73 #define USBOTGSS_FLADJ 0x0104
74 #define USBOTGSS_DEBUG_CFG 0x0108
75 #define USBOTGSS_DEBUG_DATA 0x010c
76
77 /* SYSCONFIG REGISTER */
78 #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
79 #define USBOTGSS_SYSCONFIG_STANDBYMODE(x) ((x) << 4)
80
81 #define USBOTGSS_STANDBYMODE_FORCE_STANDBY 0
82 #define USBOTGSS_STANDBYMODE_NO_STANDBY 1
83 #define USBOTGSS_STANDBYMODE_SMART_STANDBY 2
84 #define USBOTGSS_STANDBYMODE_SMART_WAKEUP 3
85
86 #define USBOTGSS_STANDBYMODE_MASK (0x03 << 4)
87
88 #define USBOTGSS_SYSCONFIG_IDLEMODE(x) ((x) << 2)
89
90 #define USBOTGSS_IDLEMODE_FORCE_IDLE 0
91 #define USBOTGSS_IDLEMODE_NO_IDLE 1
92 #define USBOTGSS_IDLEMODE_SMART_IDLE 2
93 #define USBOTGSS_IDLEMODE_SMART_WAKEUP 3
94
95 #define USBOTGSS_IDLEMODE_MASK (0x03 << 2)
96
97 /* IRQ_EOI REGISTER */
98 #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
99
100 /* IRQS0 BITS */
101 #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
102
103 /* IRQ1 BITS */
104 #define USBOTGSS_IRQ1_DMADISABLECLR (1 << 17)
105 #define USBOTGSS_IRQ1_OEVT (1 << 16)
106 #define USBOTGSS_IRQ1_DRVVBUS_RISE (1 << 13)
107 #define USBOTGSS_IRQ1_CHRGVBUS_RISE (1 << 12)
108 #define USBOTGSS_IRQ1_DISCHRGVBUS_RISE (1 << 11)
109 #define USBOTGSS_IRQ1_IDPULLUP_RISE (1 << 8)
110 #define USBOTGSS_IRQ1_DRVVBUS_FALL (1 << 5)
111 #define USBOTGSS_IRQ1_CHRGVBUS_FALL (1 << 4)
112 #define USBOTGSS_IRQ1_DISCHRGVBUS_FALL (1 << 3)
113 #define USBOTGSS_IRQ1_IDPULLUP_FALL (1 << 0)
114
115 /* UTMI_OTG_CTRL REGISTER */
116 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
117 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4)
118 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3)
119 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0)
120
121 /* UTMI_OTG_STATUS REGISTER */
122 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31)
123 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9)
124 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
125 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4)
126 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3)
127 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2)
128 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
129
130 struct dwc3_omap {
131 /* device lock */
132 spinlock_t lock;
133
134 struct platform_device *dwc3;
135 struct device *dev;
136
137 int irq;
138 void __iomem *base;
139
140 void *context;
141 u32 resource_size;
142
143 u32 dma_status:1;
144 };
145
dwc3_omap_interrupt(int irq,void * _omap)146 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
147 {
148 struct dwc3_omap *omap = _omap;
149 u32 reg;
150
151 spin_lock(&omap->lock);
152
153 reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_1);
154
155 if (reg & USBOTGSS_IRQ1_DMADISABLECLR) {
156 dev_dbg(omap->dev, "DMA Disable was Cleared\n");
157 omap->dma_status = false;
158 }
159
160 if (reg & USBOTGSS_IRQ1_OEVT)
161 dev_dbg(omap->dev, "OTG Event\n");
162
163 if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE)
164 dev_dbg(omap->dev, "DRVVBUS Rise\n");
165
166 if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE)
167 dev_dbg(omap->dev, "CHRGVBUS Rise\n");
168
169 if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE)
170 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
171
172 if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE)
173 dev_dbg(omap->dev, "IDPULLUP Rise\n");
174
175 if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL)
176 dev_dbg(omap->dev, "DRVVBUS Fall\n");
177
178 if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL)
179 dev_dbg(omap->dev, "CHRGVBUS Fall\n");
180
181 if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL)
182 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
183
184 if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL)
185 dev_dbg(omap->dev, "IDPULLUP Fall\n");
186
187 dwc3_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg);
188
189 reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_0);
190 dwc3_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg);
191
192 spin_unlock(&omap->lock);
193
194 return IRQ_HANDLED;
195 }
196
dwc3_omap_probe(struct platform_device * pdev)197 static int __devinit dwc3_omap_probe(struct platform_device *pdev)
198 {
199 struct dwc3_omap_data *pdata = pdev->dev.platform_data;
200 struct platform_device *dwc3;
201 struct dwc3_omap *omap;
202 struct resource *res;
203
204 int devid;
205 int ret = -ENOMEM;
206 int irq;
207
208 u32 reg;
209
210 void __iomem *base;
211 void *context;
212
213 omap = kzalloc(sizeof(*omap), GFP_KERNEL);
214 if (!omap) {
215 dev_err(&pdev->dev, "not enough memory\n");
216 goto err0;
217 }
218
219 platform_set_drvdata(pdev, omap);
220
221 irq = platform_get_irq(pdev, 1);
222 if (irq < 0) {
223 dev_err(&pdev->dev, "missing IRQ resource\n");
224 ret = -EINVAL;
225 goto err1;
226 }
227
228 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
229 if (!res) {
230 dev_err(&pdev->dev, "missing memory base resource\n");
231 ret = -EINVAL;
232 goto err1;
233 }
234
235 base = ioremap_nocache(res->start, resource_size(res));
236 if (!base) {
237 dev_err(&pdev->dev, "ioremap failed\n");
238 goto err1;
239 }
240
241 devid = dwc3_get_device_id();
242 if (devid < 0)
243 goto err2;
244
245 dwc3 = platform_device_alloc("dwc3", devid);
246 if (!dwc3) {
247 dev_err(&pdev->dev, "couldn't allocate dwc3 device\n");
248 goto err3;
249 }
250
251 context = kzalloc(resource_size(res), GFP_KERNEL);
252 if (!context) {
253 dev_err(&pdev->dev, "couldn't allocate dwc3 context memory\n");
254 goto err4;
255 }
256
257 spin_lock_init(&omap->lock);
258 dma_set_coherent_mask(&dwc3->dev, pdev->dev.coherent_dma_mask);
259
260 dwc3->dev.parent = &pdev->dev;
261 dwc3->dev.dma_mask = pdev->dev.dma_mask;
262 dwc3->dev.dma_parms = pdev->dev.dma_parms;
263 omap->resource_size = resource_size(res);
264 omap->context = context;
265 omap->dev = &pdev->dev;
266 omap->irq = irq;
267 omap->base = base;
268 omap->dwc3 = dwc3;
269
270 reg = dwc3_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
271
272 if (!pdata) {
273 dev_dbg(&pdev->dev, "missing platform data\n");
274 } else {
275 switch (pdata->utmi_mode) {
276 case DWC3_OMAP_UTMI_MODE_SW:
277 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
278 break;
279 case DWC3_OMAP_UTMI_MODE_HW:
280 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
281 break;
282 default:
283 dev_dbg(&pdev->dev, "UNKNOWN utmi mode %d\n",
284 pdata->utmi_mode);
285 }
286 }
287
288 dwc3_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg);
289
290 /* check the DMA Status */
291 reg = dwc3_readl(omap->base, USBOTGSS_SYSCONFIG);
292 omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
293
294 /* Set No-Idle and No-Standby */
295 reg &= ~(USBOTGSS_STANDBYMODE_MASK
296 | USBOTGSS_IDLEMODE_MASK);
297
298 reg |= (USBOTGSS_SYSCONFIG_STANDBYMODE(USBOTGSS_STANDBYMODE_NO_STANDBY)
299 | USBOTGSS_SYSCONFIG_IDLEMODE(USBOTGSS_IDLEMODE_NO_IDLE));
300
301 dwc3_writel(omap->base, USBOTGSS_SYSCONFIG, reg);
302
303 ret = request_irq(omap->irq, dwc3_omap_interrupt, 0,
304 "dwc3-omap", omap);
305 if (ret) {
306 dev_err(&pdev->dev, "failed to request IRQ #%d --> %d\n",
307 omap->irq, ret);
308 goto err5;
309 }
310
311 /* enable all IRQs */
312 reg = USBOTGSS_IRQO_COREIRQ_ST;
313 dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg);
314
315 reg = (USBOTGSS_IRQ1_OEVT |
316 USBOTGSS_IRQ1_DRVVBUS_RISE |
317 USBOTGSS_IRQ1_CHRGVBUS_RISE |
318 USBOTGSS_IRQ1_DISCHRGVBUS_RISE |
319 USBOTGSS_IRQ1_IDPULLUP_RISE |
320 USBOTGSS_IRQ1_DRVVBUS_FALL |
321 USBOTGSS_IRQ1_CHRGVBUS_FALL |
322 USBOTGSS_IRQ1_DISCHRGVBUS_FALL |
323 USBOTGSS_IRQ1_IDPULLUP_FALL);
324
325 dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg);
326
327 ret = platform_device_add_resources(dwc3, pdev->resource,
328 pdev->num_resources);
329 if (ret) {
330 dev_err(&pdev->dev, "couldn't add resources to dwc3 device\n");
331 goto err6;
332 }
333
334 ret = platform_device_add(dwc3);
335 if (ret) {
336 dev_err(&pdev->dev, "failed to register dwc3 device\n");
337 goto err6;
338 }
339
340 return 0;
341
342 err6:
343 free_irq(omap->irq, omap);
344
345 err5:
346 kfree(omap->context);
347
348 err4:
349 platform_device_put(dwc3);
350
351 err3:
352 dwc3_put_device_id(devid);
353
354 err2:
355 iounmap(base);
356
357 err1:
358 kfree(omap);
359
360 err0:
361 return ret;
362 }
363
dwc3_omap_remove(struct platform_device * pdev)364 static int __devexit dwc3_omap_remove(struct platform_device *pdev)
365 {
366 struct dwc3_omap *omap = platform_get_drvdata(pdev);
367
368 platform_device_unregister(omap->dwc3);
369
370 dwc3_put_device_id(omap->dwc3->id);
371 free_irq(omap->irq, omap);
372 iounmap(omap->base);
373
374 kfree(omap->context);
375 kfree(omap);
376
377 return 0;
378 }
379
380 static const struct of_device_id of_dwc3_matach[] = {
381 {
382 "ti,dwc3",
383 },
384 { },
385 };
386 MODULE_DEVICE_TABLE(of, of_dwc3_matach);
387
388 static struct platform_driver dwc3_omap_driver = {
389 .probe = dwc3_omap_probe,
390 .remove = __devexit_p(dwc3_omap_remove),
391 .driver = {
392 .name = "omap-dwc3",
393 .of_match_table = of_dwc3_matach,
394 },
395 };
396
397 module_platform_driver(dwc3_omap_driver);
398
399 MODULE_ALIAS("platform:omap-dwc3");
400 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
401 MODULE_LICENSE("Dual BSD/GPL");
402 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");
403