1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2024 AIROHA Inc
4 * Author: Lorenzo Bianconi <lorenzo@kernel.org>
5 * Author: Ray Liu <ray.liu@airoha.com>
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/errno.h>
14 #include <linux/limits.h>
15 #include <linux/math.h>
16 #include <linux/minmax.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/platform_device.h>
20 #include <linux/property.h>
21 #include <linux/regmap.h>
22 #include <linux/sizes.h>
23 #include <linux/spi/spi.h>
24 #include <linux/spi/spi-mem.h>
25 #include <linux/types.h>
26 #include <linux/unaligned.h>
27
28 /* SPI */
29 #define REG_SPI_CTRL_BASE 0x1FA10000
30
31 #define REG_SPI_CTRL_READ_MODE 0x0000
32 #define REG_SPI_CTRL_READ_IDLE_EN 0x0004
33 #define REG_SPI_CTRL_SIDLY 0x0008
34 #define REG_SPI_CTRL_CSHEXT 0x000c
35 #define REG_SPI_CTRL_CSLEXT 0x0010
36
37 #define REG_SPI_CTRL_MTX_MODE_TOG 0x0014
38 #define SPI_CTRL_MTX_MODE_TOG GENMASK(3, 0)
39
40 #define REG_SPI_CTRL_RDCTL_FSM 0x0018
41 #define SPI_CTRL_RDCTL_FSM GENMASK(3, 0)
42
43 #define REG_SPI_CTRL_MACMUX_SEL 0x001c
44
45 #define REG_SPI_CTRL_MANUAL_EN 0x0020
46 #define SPI_CTRL_MANUAL_EN BIT(0)
47
48 #define REG_SPI_CTRL_OPFIFO_EMPTY 0x0024
49 #define SPI_CTRL_OPFIFO_EMPTY BIT(0)
50
51 #define REG_SPI_CTRL_OPFIFO_WDATA 0x0028
52 #define SPI_CTRL_OPFIFO_LEN GENMASK(8, 0)
53 #define SPI_CTRL_OPFIFO_OP GENMASK(13, 9)
54
55 #define REG_SPI_CTRL_OPFIFO_FULL 0x002c
56 #define SPI_CTRL_OPFIFO_FULL BIT(0)
57
58 #define REG_SPI_CTRL_OPFIFO_WR 0x0030
59 #define SPI_CTRL_OPFIFO_WR BIT(0)
60
61 #define REG_SPI_CTRL_DFIFO_FULL 0x0034
62 #define SPI_CTRL_DFIFO_FULL BIT(0)
63
64 #define REG_SPI_CTRL_DFIFO_WDATA 0x0038
65 #define SPI_CTRL_DFIFO_WDATA GENMASK(7, 0)
66
67 #define REG_SPI_CTRL_DFIFO_EMPTY 0x003c
68 #define SPI_CTRL_DFIFO_EMPTY BIT(0)
69
70 #define REG_SPI_CTRL_DFIFO_RD 0x0040
71 #define SPI_CTRL_DFIFO_RD BIT(0)
72
73 #define REG_SPI_CTRL_DFIFO_RDATA 0x0044
74 #define SPI_CTRL_DFIFO_RDATA GENMASK(7, 0)
75
76 #define REG_SPI_CTRL_DUMMY 0x0080
77 #define SPI_CTRL_CTRL_DUMMY GENMASK(3, 0)
78
79 #define REG_SPI_CTRL_PROBE_SEL 0x0088
80 #define REG_SPI_CTRL_INTERRUPT 0x0090
81 #define REG_SPI_CTRL_INTERRUPT_EN 0x0094
82 #define REG_SPI_CTRL_SI_CK_SEL 0x009c
83 #define REG_SPI_CTRL_SW_CFGNANDADDR_VAL 0x010c
84 #define REG_SPI_CTRL_SW_CFGNANDADDR_EN 0x0110
85 #define REG_SPI_CTRL_SFC_STRAP 0x0114
86
87 #define REG_SPI_CTRL_NFI2SPI_EN 0x0130
88 #define SPI_CTRL_NFI2SPI_EN BIT(0)
89
90 /* NFI2SPI */
91 #define REG_SPI_NFI_CNFG 0x0000
92 #define SPI_NFI_DMA_MODE BIT(0)
93 #define SPI_NFI_READ_MODE BIT(1)
94 #define SPI_NFI_DMA_BURST_EN BIT(2)
95 #define SPI_NFI_HW_ECC_EN BIT(8)
96 #define SPI_NFI_AUTO_FDM_EN BIT(9)
97 #define SPI_NFI_OPMODE GENMASK(14, 12)
98
99 #define REG_SPI_NFI_PAGEFMT 0x0004
100 #define SPI_NFI_PAGE_SIZE GENMASK(1, 0)
101 #define SPI_NFI_SPARE_SIZE GENMASK(5, 4)
102
103 #define REG_SPI_NFI_CON 0x0008
104 #define SPI_NFI_FIFO_FLUSH BIT(0)
105 #define SPI_NFI_RST BIT(1)
106 #define SPI_NFI_RD_TRIG BIT(8)
107 #define SPI_NFI_WR_TRIG BIT(9)
108 #define SPI_NFI_SEC_NUM GENMASK(15, 12)
109
110 #define REG_SPI_NFI_INTR_EN 0x0010
111 #define SPI_NFI_RD_DONE_EN BIT(0)
112 #define SPI_NFI_WR_DONE_EN BIT(1)
113 #define SPI_NFI_RST_DONE_EN BIT(2)
114 #define SPI_NFI_ERASE_DONE_EN BIT(3)
115 #define SPI_NFI_BUSY_RETURN_EN BIT(4)
116 #define SPI_NFI_ACCESS_LOCK_EN BIT(5)
117 #define SPI_NFI_AHB_DONE_EN BIT(6)
118 #define SPI_NFI_ALL_IRQ_EN \
119 (SPI_NFI_RD_DONE_EN | SPI_NFI_WR_DONE_EN | \
120 SPI_NFI_RST_DONE_EN | SPI_NFI_ERASE_DONE_EN | \
121 SPI_NFI_BUSY_RETURN_EN | SPI_NFI_ACCESS_LOCK_EN | \
122 SPI_NFI_AHB_DONE_EN)
123
124 #define REG_SPI_NFI_INTR 0x0014
125 #define SPI_NFI_AHB_DONE BIT(6)
126
127 #define REG_SPI_NFI_CMD 0x0020
128
129 #define REG_SPI_NFI_ADDR_NOB 0x0030
130 #define SPI_NFI_ROW_ADDR_NOB GENMASK(6, 4)
131
132 #define REG_SPI_NFI_STA 0x0060
133 #define REG_SPI_NFI_FIFOSTA 0x0064
134 #define REG_SPI_NFI_STRADDR 0x0080
135 #define REG_SPI_NFI_FDM0L 0x00a0
136 #define REG_SPI_NFI_FDM0M 0x00a4
137 #define REG_SPI_NFI_FDM7L 0x00d8
138 #define REG_SPI_NFI_FDM7M 0x00dc
139 #define REG_SPI_NFI_FIFODATA0 0x0190
140 #define REG_SPI_NFI_FIFODATA1 0x0194
141 #define REG_SPI_NFI_FIFODATA2 0x0198
142 #define REG_SPI_NFI_FIFODATA3 0x019c
143 #define REG_SPI_NFI_MASTERSTA 0x0224
144
145 #define REG_SPI_NFI_SECCUS_SIZE 0x022c
146 #define SPI_NFI_CUS_SEC_SIZE GENMASK(12, 0)
147 #define SPI_NFI_CUS_SEC_SIZE_EN BIT(16)
148
149 #define REG_SPI_NFI_RD_CTL2 0x0510
150 #define REG_SPI_NFI_RD_CTL3 0x0514
151
152 #define REG_SPI_NFI_PG_CTL1 0x0524
153 #define SPI_NFI_PG_LOAD_CMD GENMASK(15, 8)
154
155 #define REG_SPI_NFI_PG_CTL2 0x0528
156 #define REG_SPI_NFI_NOR_PROG_ADDR 0x052c
157 #define REG_SPI_NFI_NOR_RD_ADDR 0x0534
158
159 #define REG_SPI_NFI_SNF_MISC_CTL 0x0538
160 #define SPI_NFI_DATA_READ_WR_MODE GENMASK(18, 16)
161
162 #define REG_SPI_NFI_SNF_MISC_CTL2 0x053c
163 #define SPI_NFI_READ_DATA_BYTE_NUM GENMASK(12, 0)
164 #define SPI_NFI_PROG_LOAD_BYTE_NUM GENMASK(28, 16)
165
166 #define REG_SPI_NFI_SNF_STA_CTL1 0x0550
167 #define SPI_NFI_READ_FROM_CACHE_DONE BIT(25)
168 #define SPI_NFI_LOAD_TO_CACHE_DONE BIT(26)
169
170 #define REG_SPI_NFI_SNF_STA_CTL2 0x0554
171
172 #define REG_SPI_NFI_SNF_NFI_CNFG 0x055c
173 #define SPI_NFI_SPI_MODE BIT(0)
174
175 /* SPI NAND Protocol OP */
176 #define SPI_NAND_OP_GET_FEATURE 0x0f
177 #define SPI_NAND_OP_SET_FEATURE 0x1f
178 #define SPI_NAND_OP_PAGE_READ 0x13
179 #define SPI_NAND_OP_READ_FROM_CACHE_SINGLE 0x03
180 #define SPI_NAND_OP_READ_FROM_CACHE_SINGLE_FAST 0x0b
181 #define SPI_NAND_OP_READ_FROM_CACHE_DUAL 0x3b
182 #define SPI_NAND_OP_READ_FROM_CACHE_QUAD 0x6b
183 #define SPI_NAND_OP_WRITE_ENABLE 0x06
184 #define SPI_NAND_OP_WRITE_DISABLE 0x04
185 #define SPI_NAND_OP_PROGRAM_LOAD_SINGLE 0x02
186 #define SPI_NAND_OP_PROGRAM_LOAD_QUAD 0x32
187 #define SPI_NAND_OP_PROGRAM_LOAD_RAMDOM_SINGLE 0x84
188 #define SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD 0x34
189 #define SPI_NAND_OP_PROGRAM_EXECUTE 0x10
190 #define SPI_NAND_OP_READ_ID 0x9f
191 #define SPI_NAND_OP_BLOCK_ERASE 0xd8
192 #define SPI_NAND_OP_RESET 0xff
193 #define SPI_NAND_OP_DIE_SELECT 0xc2
194
195 /* SNAND FIFO commands */
196 #define SNAND_FIFO_TX_BUSWIDTH_SINGLE 0x08
197 #define SNAND_FIFO_TX_BUSWIDTH_DUAL 0x09
198 #define SNAND_FIFO_TX_BUSWIDTH_QUAD 0x0a
199 #define SNAND_FIFO_RX_BUSWIDTH_SINGLE 0x0c
200 #define SNAND_FIFO_RX_BUSWIDTH_DUAL 0x0e
201 #define SNAND_FIFO_RX_BUSWIDTH_QUAD 0x0f
202
203 #define SPI_NAND_CACHE_SIZE (SZ_4K + SZ_256)
204 #define SPI_MAX_TRANSFER_SIZE 511
205
206 enum airoha_snand_mode {
207 SPI_MODE_AUTO,
208 SPI_MODE_MANUAL,
209 SPI_MODE_DMA,
210 };
211
212 enum airoha_snand_cs {
213 SPI_CHIP_SEL_HIGH,
214 SPI_CHIP_SEL_LOW,
215 };
216
217 struct airoha_snand_ctrl {
218 struct device *dev;
219 struct regmap *regmap_ctrl;
220 struct regmap *regmap_nfi;
221 struct clk *spi_clk;
222
223 struct {
224 size_t page_size;
225 size_t sec_size;
226 u8 sec_num;
227 u8 spare_size;
228 } nfi_cfg;
229 };
230
airoha_snand_set_fifo_op(struct airoha_snand_ctrl * as_ctrl,u8 op_cmd,int op_len)231 static int airoha_snand_set_fifo_op(struct airoha_snand_ctrl *as_ctrl,
232 u8 op_cmd, int op_len)
233 {
234 int err;
235 u32 val;
236
237 err = regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WDATA,
238 FIELD_PREP(SPI_CTRL_OPFIFO_LEN, op_len) |
239 FIELD_PREP(SPI_CTRL_OPFIFO_OP, op_cmd));
240 if (err)
241 return err;
242
243 err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
244 REG_SPI_CTRL_OPFIFO_FULL,
245 val, !(val & SPI_CTRL_OPFIFO_FULL),
246 0, 250 * USEC_PER_MSEC);
247 if (err)
248 return err;
249
250 err = regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WR,
251 SPI_CTRL_OPFIFO_WR);
252 if (err)
253 return err;
254
255 return regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
256 REG_SPI_CTRL_OPFIFO_EMPTY,
257 val, (val & SPI_CTRL_OPFIFO_EMPTY),
258 0, 250 * USEC_PER_MSEC);
259 }
260
airoha_snand_set_cs(struct airoha_snand_ctrl * as_ctrl,u8 cs)261 static int airoha_snand_set_cs(struct airoha_snand_ctrl *as_ctrl, u8 cs)
262 {
263 return airoha_snand_set_fifo_op(as_ctrl, cs, sizeof(cs));
264 }
265
airoha_snand_write_data_to_fifo(struct airoha_snand_ctrl * as_ctrl,const u8 * data,int len)266 static int airoha_snand_write_data_to_fifo(struct airoha_snand_ctrl *as_ctrl,
267 const u8 *data, int len)
268 {
269 int i;
270
271 for (i = 0; i < len; i++) {
272 int err;
273 u32 val;
274
275 /* 1. Wait until dfifo is not full */
276 err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
277 REG_SPI_CTRL_DFIFO_FULL, val,
278 !(val & SPI_CTRL_DFIFO_FULL),
279 0, 250 * USEC_PER_MSEC);
280 if (err)
281 return err;
282
283 /* 2. Write data to register DFIFO_WDATA */
284 err = regmap_write(as_ctrl->regmap_ctrl,
285 REG_SPI_CTRL_DFIFO_WDATA,
286 FIELD_PREP(SPI_CTRL_DFIFO_WDATA, data[i]));
287 if (err)
288 return err;
289
290 /* 3. Wait until dfifo is not full */
291 err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
292 REG_SPI_CTRL_DFIFO_FULL, val,
293 !(val & SPI_CTRL_DFIFO_FULL),
294 0, 250 * USEC_PER_MSEC);
295 if (err)
296 return err;
297 }
298
299 return 0;
300 }
301
airoha_snand_read_data_from_fifo(struct airoha_snand_ctrl * as_ctrl,u8 * ptr,int len)302 static int airoha_snand_read_data_from_fifo(struct airoha_snand_ctrl *as_ctrl,
303 u8 *ptr, int len)
304 {
305 int i;
306
307 for (i = 0; i < len; i++) {
308 int err;
309 u32 val;
310
311 /* 1. wait until dfifo is not empty */
312 err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
313 REG_SPI_CTRL_DFIFO_EMPTY, val,
314 !(val & SPI_CTRL_DFIFO_EMPTY),
315 0, 250 * USEC_PER_MSEC);
316 if (err)
317 return err;
318
319 /* 2. read from dfifo to register DFIFO_RDATA */
320 err = regmap_read(as_ctrl->regmap_ctrl,
321 REG_SPI_CTRL_DFIFO_RDATA, &val);
322 if (err)
323 return err;
324
325 ptr[i] = FIELD_GET(SPI_CTRL_DFIFO_RDATA, val);
326 /* 3. enable register DFIFO_RD to read next byte */
327 err = regmap_write(as_ctrl->regmap_ctrl,
328 REG_SPI_CTRL_DFIFO_RD, SPI_CTRL_DFIFO_RD);
329 if (err)
330 return err;
331 }
332
333 return 0;
334 }
335
airoha_snand_set_mode(struct airoha_snand_ctrl * as_ctrl,enum airoha_snand_mode mode)336 static int airoha_snand_set_mode(struct airoha_snand_ctrl *as_ctrl,
337 enum airoha_snand_mode mode)
338 {
339 int err;
340
341 switch (mode) {
342 case SPI_MODE_MANUAL: {
343 u32 val;
344
345 err = regmap_write(as_ctrl->regmap_ctrl,
346 REG_SPI_CTRL_NFI2SPI_EN, 0);
347 if (err)
348 return err;
349
350 err = regmap_write(as_ctrl->regmap_ctrl,
351 REG_SPI_CTRL_READ_IDLE_EN, 0);
352 if (err)
353 return err;
354
355 err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
356 REG_SPI_CTRL_RDCTL_FSM, val,
357 !(val & SPI_CTRL_RDCTL_FSM),
358 0, 250 * USEC_PER_MSEC);
359 if (err)
360 return err;
361
362 err = regmap_write(as_ctrl->regmap_ctrl,
363 REG_SPI_CTRL_MTX_MODE_TOG, 9);
364 if (err)
365 return err;
366
367 err = regmap_write(as_ctrl->regmap_ctrl,
368 REG_SPI_CTRL_MANUAL_EN, SPI_CTRL_MANUAL_EN);
369 if (err)
370 return err;
371 break;
372 }
373 case SPI_MODE_DMA:
374 err = regmap_write(as_ctrl->regmap_ctrl,
375 REG_SPI_CTRL_NFI2SPI_EN,
376 SPI_CTRL_MANUAL_EN);
377 if (err < 0)
378 return err;
379
380 err = regmap_write(as_ctrl->regmap_ctrl,
381 REG_SPI_CTRL_MTX_MODE_TOG, 0x0);
382 if (err < 0)
383 return err;
384
385 err = regmap_write(as_ctrl->regmap_ctrl,
386 REG_SPI_CTRL_MANUAL_EN, 0x0);
387 if (err < 0)
388 return err;
389 break;
390 case SPI_MODE_AUTO:
391 default:
392 break;
393 }
394
395 return regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_DUMMY, 0);
396 }
397
airoha_snand_write_data(struct airoha_snand_ctrl * as_ctrl,const u8 * data,int len,int buswidth)398 static int airoha_snand_write_data(struct airoha_snand_ctrl *as_ctrl,
399 const u8 *data, int len, int buswidth)
400 {
401 int i, data_len;
402 u8 cmd;
403
404 switch (buswidth) {
405 case 0:
406 case 1:
407 cmd = SNAND_FIFO_TX_BUSWIDTH_SINGLE;
408 break;
409 case 2:
410 cmd = SNAND_FIFO_TX_BUSWIDTH_DUAL;
411 break;
412 case 4:
413 cmd = SNAND_FIFO_TX_BUSWIDTH_QUAD;
414 break;
415 default:
416 return -EINVAL;
417 }
418
419 for (i = 0; i < len; i += data_len) {
420 int err;
421
422 data_len = min(len - i, SPI_MAX_TRANSFER_SIZE);
423 err = airoha_snand_set_fifo_op(as_ctrl, cmd, data_len);
424 if (err)
425 return err;
426
427 err = airoha_snand_write_data_to_fifo(as_ctrl, &data[i],
428 data_len);
429 if (err < 0)
430 return err;
431 }
432
433 return 0;
434 }
435
airoha_snand_read_data(struct airoha_snand_ctrl * as_ctrl,u8 * data,int len,int buswidth)436 static int airoha_snand_read_data(struct airoha_snand_ctrl *as_ctrl,
437 u8 *data, int len, int buswidth)
438 {
439 int i, data_len;
440 u8 cmd;
441
442 switch (buswidth) {
443 case 0:
444 case 1:
445 cmd = SNAND_FIFO_RX_BUSWIDTH_SINGLE;
446 break;
447 case 2:
448 cmd = SNAND_FIFO_RX_BUSWIDTH_DUAL;
449 break;
450 case 4:
451 cmd = SNAND_FIFO_RX_BUSWIDTH_QUAD;
452 break;
453 default:
454 return -EINVAL;
455 }
456
457 for (i = 0; i < len; i += data_len) {
458 int err;
459
460 data_len = min(len - i, SPI_MAX_TRANSFER_SIZE);
461 err = airoha_snand_set_fifo_op(as_ctrl, cmd, data_len);
462 if (err)
463 return err;
464
465 err = airoha_snand_read_data_from_fifo(as_ctrl, &data[i],
466 data_len);
467 if (err < 0)
468 return err;
469 }
470
471 return 0;
472 }
473
airoha_snand_nfi_init(struct airoha_snand_ctrl * as_ctrl)474 static int airoha_snand_nfi_init(struct airoha_snand_ctrl *as_ctrl)
475 {
476 int err;
477
478 /* switch to SNFI mode */
479 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_NFI_CNFG,
480 SPI_NFI_SPI_MODE);
481 if (err)
482 return err;
483
484 /* Enable DMA */
485 return regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR_EN,
486 SPI_NFI_ALL_IRQ_EN, SPI_NFI_AHB_DONE_EN);
487 }
488
airoha_snand_nfi_config(struct airoha_snand_ctrl * as_ctrl)489 static int airoha_snand_nfi_config(struct airoha_snand_ctrl *as_ctrl)
490 {
491 int err;
492 u32 val;
493
494 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
495 SPI_NFI_FIFO_FLUSH | SPI_NFI_RST);
496 if (err)
497 return err;
498
499 /* auto FDM */
500 err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
501 SPI_NFI_AUTO_FDM_EN);
502 if (err)
503 return err;
504
505 /* HW ECC */
506 err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
507 SPI_NFI_HW_ECC_EN);
508 if (err)
509 return err;
510
511 /* DMA Burst */
512 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
513 SPI_NFI_DMA_BURST_EN);
514 if (err)
515 return err;
516
517 /* page format */
518 switch (as_ctrl->nfi_cfg.spare_size) {
519 case 26:
520 val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x1);
521 break;
522 case 27:
523 val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x2);
524 break;
525 case 28:
526 val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x3);
527 break;
528 default:
529 val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x0);
530 break;
531 }
532
533 err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_PAGEFMT,
534 SPI_NFI_SPARE_SIZE, val);
535 if (err)
536 return err;
537
538 switch (as_ctrl->nfi_cfg.page_size) {
539 case 2048:
540 val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x1);
541 break;
542 case 4096:
543 val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x2);
544 break;
545 default:
546 val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x0);
547 break;
548 }
549
550 err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_PAGEFMT,
551 SPI_NFI_PAGE_SIZE, val);
552 if (err)
553 return err;
554
555 /* sec num */
556 val = FIELD_PREP(SPI_NFI_SEC_NUM, as_ctrl->nfi_cfg.sec_num);
557 err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
558 SPI_NFI_SEC_NUM, val);
559 if (err)
560 return err;
561
562 /* enable cust sec size */
563 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
564 SPI_NFI_CUS_SEC_SIZE_EN);
565 if (err)
566 return err;
567
568 /* set cust sec size */
569 val = FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, as_ctrl->nfi_cfg.sec_size);
570 return regmap_update_bits(as_ctrl->regmap_nfi,
571 REG_SPI_NFI_SECCUS_SIZE,
572 SPI_NFI_CUS_SEC_SIZE, val);
573 }
574
airoha_snand_is_page_ops(const struct spi_mem_op * op)575 static bool airoha_snand_is_page_ops(const struct spi_mem_op *op)
576 {
577 if (op->addr.nbytes != 2)
578 return false;
579
580 if (op->addr.buswidth != 1 && op->addr.buswidth != 2 &&
581 op->addr.buswidth != 4)
582 return false;
583
584 switch (op->data.dir) {
585 case SPI_MEM_DATA_IN:
586 if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth > 0xf)
587 return false;
588
589 /* quad in / quad out */
590 if (op->addr.buswidth == 4)
591 return op->data.buswidth == 4;
592
593 if (op->addr.buswidth == 2)
594 return op->data.buswidth == 2;
595
596 /* standard spi */
597 return op->data.buswidth == 4 || op->data.buswidth == 2 ||
598 op->data.buswidth == 1;
599 case SPI_MEM_DATA_OUT:
600 return !op->dummy.nbytes && op->addr.buswidth == 1 &&
601 (op->data.buswidth == 4 || op->data.buswidth == 1);
602 default:
603 return false;
604 }
605 }
606
airoha_snand_adjust_op_size(struct spi_mem * mem,struct spi_mem_op * op)607 static int airoha_snand_adjust_op_size(struct spi_mem *mem,
608 struct spi_mem_op *op)
609 {
610 size_t max_len;
611
612 if (airoha_snand_is_page_ops(op)) {
613 struct airoha_snand_ctrl *as_ctrl;
614
615 as_ctrl = spi_controller_get_devdata(mem->spi->controller);
616 max_len = as_ctrl->nfi_cfg.sec_size;
617 max_len += as_ctrl->nfi_cfg.spare_size;
618 max_len *= as_ctrl->nfi_cfg.sec_num;
619
620 if (op->data.nbytes > max_len)
621 op->data.nbytes = max_len;
622 } else {
623 max_len = 1 + op->addr.nbytes + op->dummy.nbytes;
624 if (max_len >= 160)
625 return -EOPNOTSUPP;
626
627 if (op->data.nbytes > 160 - max_len)
628 op->data.nbytes = 160 - max_len;
629 }
630
631 return 0;
632 }
633
airoha_snand_supports_op(struct spi_mem * mem,const struct spi_mem_op * op)634 static bool airoha_snand_supports_op(struct spi_mem *mem,
635 const struct spi_mem_op *op)
636 {
637 if (!spi_mem_default_supports_op(mem, op))
638 return false;
639
640 if (op->cmd.buswidth != 1)
641 return false;
642
643 if (airoha_snand_is_page_ops(op))
644 return true;
645
646 return (!op->addr.nbytes || op->addr.buswidth == 1) &&
647 (!op->dummy.nbytes || op->dummy.buswidth == 1) &&
648 (!op->data.nbytes || op->data.buswidth == 1);
649 }
650
airoha_snand_dirmap_create(struct spi_mem_dirmap_desc * desc)651 static int airoha_snand_dirmap_create(struct spi_mem_dirmap_desc *desc)
652 {
653 u8 *txrx_buf = spi_get_ctldata(desc->mem->spi);
654
655 if (!txrx_buf)
656 return -EINVAL;
657
658 if (desc->info.offset + desc->info.length > U32_MAX)
659 return -EINVAL;
660
661 /* continuous reading is not supported */
662 if (desc->info.length > SPI_NAND_CACHE_SIZE)
663 return -E2BIG;
664
665 if (!airoha_snand_supports_op(desc->mem, &desc->info.op_tmpl))
666 return -EOPNOTSUPP;
667
668 return 0;
669 }
670
airoha_snand_dirmap_read(struct spi_mem_dirmap_desc * desc,u64 offs,size_t len,void * buf)671 static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
672 u64 offs, size_t len, void *buf)
673 {
674 struct spi_mem_op *op = &desc->info.op_tmpl;
675 struct spi_device *spi = desc->mem->spi;
676 struct airoha_snand_ctrl *as_ctrl;
677 u8 *txrx_buf = spi_get_ctldata(spi);
678 dma_addr_t dma_addr;
679 u32 val, rd_mode;
680 int err;
681
682 switch (op->cmd.opcode) {
683 case SPI_NAND_OP_READ_FROM_CACHE_DUAL:
684 rd_mode = 1;
685 break;
686 case SPI_NAND_OP_READ_FROM_CACHE_QUAD:
687 rd_mode = 2;
688 break;
689 default:
690 rd_mode = 0;
691 break;
692 }
693
694 as_ctrl = spi_controller_get_devdata(spi->controller);
695 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_DMA);
696 if (err < 0)
697 return err;
698
699 err = airoha_snand_nfi_config(as_ctrl);
700 if (err)
701 goto error_dma_mode_off;
702
703 dma_addr = dma_map_single(as_ctrl->dev, txrx_buf, SPI_NAND_CACHE_SIZE,
704 DMA_FROM_DEVICE);
705 err = dma_mapping_error(as_ctrl->dev, dma_addr);
706 if (err)
707 goto error_dma_mode_off;
708
709 /* set dma addr */
710 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR,
711 dma_addr);
712 if (err)
713 goto error_dma_unmap;
714
715 /* set cust sec size */
716 val = as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num;
717 val = FIELD_PREP(SPI_NFI_READ_DATA_BYTE_NUM, val);
718 err = regmap_update_bits(as_ctrl->regmap_nfi,
719 REG_SPI_NFI_SNF_MISC_CTL2,
720 SPI_NFI_READ_DATA_BYTE_NUM, val);
721 if (err)
722 goto error_dma_unmap;
723
724 /* set read command */
725 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL2,
726 op->cmd.opcode);
727 if (err)
728 goto error_dma_unmap;
729
730 /* set read mode */
731 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
732 FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, rd_mode));
733 if (err)
734 goto error_dma_unmap;
735
736 /* set read addr: zero page offset + descriptor read offset */
737 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL3,
738 desc->info.offset);
739 if (err)
740 goto error_dma_unmap;
741
742 /* set nfi read */
743 err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
744 SPI_NFI_OPMODE,
745 FIELD_PREP(SPI_NFI_OPMODE, 6));
746 if (err)
747 goto error_dma_unmap;
748
749 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
750 SPI_NFI_READ_MODE | SPI_NFI_DMA_MODE);
751 if (err)
752 goto error_dma_unmap;
753
754 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x0);
755 if (err)
756 goto error_dma_unmap;
757
758 /* trigger dma start read */
759 err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
760 SPI_NFI_RD_TRIG);
761 if (err)
762 goto error_dma_unmap;
763
764 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
765 SPI_NFI_RD_TRIG);
766 if (err)
767 goto error_dma_unmap;
768
769 err = regmap_read_poll_timeout(as_ctrl->regmap_nfi,
770 REG_SPI_NFI_SNF_STA_CTL1, val,
771 (val & SPI_NFI_READ_FROM_CACHE_DONE),
772 0, 1 * USEC_PER_SEC);
773 if (err)
774 goto error_dma_unmap;
775
776 /*
777 * SPI_NFI_READ_FROM_CACHE_DONE bit must be written at the end
778 * of dirmap_read operation even if it is already set.
779 */
780 err = regmap_write_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
781 SPI_NFI_READ_FROM_CACHE_DONE,
782 SPI_NFI_READ_FROM_CACHE_DONE);
783 if (err)
784 goto error_dma_unmap;
785
786 err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR,
787 val, (val & SPI_NFI_AHB_DONE), 0,
788 1 * USEC_PER_SEC);
789 if (err)
790 goto error_dma_unmap;
791
792 /* DMA read need delay for data ready from controller to DRAM */
793 udelay(1);
794
795 dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE,
796 DMA_FROM_DEVICE);
797 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
798 if (err < 0)
799 return err;
800
801 memcpy(buf, txrx_buf + offs, len);
802
803 return len;
804
805 error_dma_unmap:
806 dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE,
807 DMA_FROM_DEVICE);
808 error_dma_mode_off:
809 airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
810 return err;
811 }
812
airoha_snand_dirmap_write(struct spi_mem_dirmap_desc * desc,u64 offs,size_t len,const void * buf)813 static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
814 u64 offs, size_t len, const void *buf)
815 {
816 struct spi_mem_op *op = &desc->info.op_tmpl;
817 struct spi_device *spi = desc->mem->spi;
818 u8 *txrx_buf = spi_get_ctldata(spi);
819 struct airoha_snand_ctrl *as_ctrl;
820 dma_addr_t dma_addr;
821 u32 wr_mode, val;
822 int err;
823
824 as_ctrl = spi_controller_get_devdata(spi->controller);
825 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
826 if (err < 0)
827 return err;
828
829 memcpy(txrx_buf + offs, buf, len);
830 dma_addr = dma_map_single(as_ctrl->dev, txrx_buf, SPI_NAND_CACHE_SIZE,
831 DMA_TO_DEVICE);
832 err = dma_mapping_error(as_ctrl->dev, dma_addr);
833 if (err)
834 return err;
835
836 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_DMA);
837 if (err < 0)
838 goto error_dma_unmap;
839
840 err = airoha_snand_nfi_config(as_ctrl);
841 if (err)
842 goto error_dma_unmap;
843
844 if (op->cmd.opcode == SPI_NAND_OP_PROGRAM_LOAD_QUAD ||
845 op->cmd.opcode == SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD)
846 wr_mode = BIT(1);
847 else
848 wr_mode = 0;
849
850 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR,
851 dma_addr);
852 if (err)
853 goto error_dma_unmap;
854
855 val = FIELD_PREP(SPI_NFI_PROG_LOAD_BYTE_NUM,
856 as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num);
857 err = regmap_update_bits(as_ctrl->regmap_nfi,
858 REG_SPI_NFI_SNF_MISC_CTL2,
859 SPI_NFI_PROG_LOAD_BYTE_NUM, val);
860 if (err)
861 goto error_dma_unmap;
862
863 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL1,
864 FIELD_PREP(SPI_NFI_PG_LOAD_CMD,
865 op->cmd.opcode));
866 if (err)
867 goto error_dma_unmap;
868
869 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
870 FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, wr_mode));
871 if (err)
872 goto error_dma_unmap;
873
874 /* set write addr: zero page offset + descriptor write offset */
875 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL2,
876 desc->info.offset);
877 if (err)
878 goto error_dma_unmap;
879
880 err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
881 SPI_NFI_READ_MODE);
882 if (err)
883 goto error_dma_unmap;
884
885 err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
886 SPI_NFI_OPMODE,
887 FIELD_PREP(SPI_NFI_OPMODE, 3));
888 if (err)
889 goto error_dma_unmap;
890
891 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
892 SPI_NFI_DMA_MODE);
893 if (err)
894 goto error_dma_unmap;
895
896 err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x80);
897 if (err)
898 goto error_dma_unmap;
899
900 err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
901 SPI_NFI_WR_TRIG);
902 if (err)
903 goto error_dma_unmap;
904
905 err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
906 SPI_NFI_WR_TRIG);
907 if (err)
908 goto error_dma_unmap;
909
910 err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR,
911 val, (val & SPI_NFI_AHB_DONE), 0,
912 1 * USEC_PER_SEC);
913 if (err)
914 goto error_dma_unmap;
915
916 err = regmap_read_poll_timeout(as_ctrl->regmap_nfi,
917 REG_SPI_NFI_SNF_STA_CTL1, val,
918 (val & SPI_NFI_LOAD_TO_CACHE_DONE),
919 0, 1 * USEC_PER_SEC);
920 if (err)
921 goto error_dma_unmap;
922
923 /*
924 * SPI_NFI_LOAD_TO_CACHE_DONE bit must be written at the end
925 * of dirmap_write operation even if it is already set.
926 */
927 err = regmap_write_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
928 SPI_NFI_LOAD_TO_CACHE_DONE,
929 SPI_NFI_LOAD_TO_CACHE_DONE);
930 if (err)
931 goto error_dma_unmap;
932
933 dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE,
934 DMA_TO_DEVICE);
935 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
936 if (err < 0)
937 return err;
938
939 return len;
940
941 error_dma_unmap:
942 dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE,
943 DMA_TO_DEVICE);
944 airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
945 return err;
946 }
947
airoha_snand_exec_op(struct spi_mem * mem,const struct spi_mem_op * op)948 static int airoha_snand_exec_op(struct spi_mem *mem,
949 const struct spi_mem_op *op)
950 {
951 struct airoha_snand_ctrl *as_ctrl;
952 int op_len, addr_len, dummy_len;
953 u8 buf[20], *data;
954 int i, err;
955
956 as_ctrl = spi_controller_get_devdata(mem->spi->controller);
957
958 op_len = op->cmd.nbytes;
959 addr_len = op->addr.nbytes;
960 dummy_len = op->dummy.nbytes;
961
962 if (op_len + dummy_len + addr_len > sizeof(buf))
963 return -EIO;
964
965 data = buf;
966 for (i = 0; i < op_len; i++)
967 *data++ = op->cmd.opcode >> (8 * (op_len - i - 1));
968 for (i = 0; i < addr_len; i++)
969 *data++ = op->addr.val >> (8 * (addr_len - i - 1));
970 for (i = 0; i < dummy_len; i++)
971 *data++ = 0xff;
972
973 /* switch to manual mode */
974 err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
975 if (err < 0)
976 return err;
977
978 err = airoha_snand_set_cs(as_ctrl, SPI_CHIP_SEL_LOW);
979 if (err < 0)
980 return err;
981
982 /* opcode */
983 data = buf;
984 err = airoha_snand_write_data(as_ctrl, data, op_len,
985 op->cmd.buswidth);
986 if (err)
987 return err;
988
989 /* addr part */
990 data += op_len;
991 if (addr_len) {
992 err = airoha_snand_write_data(as_ctrl, data, addr_len,
993 op->addr.buswidth);
994 if (err)
995 return err;
996 }
997
998 /* dummy */
999 data += addr_len;
1000 if (dummy_len) {
1001 err = airoha_snand_write_data(as_ctrl, data, dummy_len,
1002 op->dummy.buswidth);
1003 if (err)
1004 return err;
1005 }
1006
1007 /* data */
1008 if (op->data.nbytes) {
1009 if (op->data.dir == SPI_MEM_DATA_IN)
1010 err = airoha_snand_read_data(as_ctrl, op->data.buf.in,
1011 op->data.nbytes,
1012 op->data.buswidth);
1013 else
1014 err = airoha_snand_write_data(as_ctrl, op->data.buf.out,
1015 op->data.nbytes,
1016 op->data.buswidth);
1017 if (err)
1018 return err;
1019 }
1020
1021 return airoha_snand_set_cs(as_ctrl, SPI_CHIP_SEL_HIGH);
1022 }
1023
1024 static const struct spi_controller_mem_ops airoha_snand_mem_ops = {
1025 .adjust_op_size = airoha_snand_adjust_op_size,
1026 .supports_op = airoha_snand_supports_op,
1027 .exec_op = airoha_snand_exec_op,
1028 .dirmap_create = airoha_snand_dirmap_create,
1029 .dirmap_read = airoha_snand_dirmap_read,
1030 .dirmap_write = airoha_snand_dirmap_write,
1031 };
1032
airoha_snand_setup(struct spi_device * spi)1033 static int airoha_snand_setup(struct spi_device *spi)
1034 {
1035 struct airoha_snand_ctrl *as_ctrl;
1036 u8 *txrx_buf;
1037
1038 /* prepare device buffer */
1039 as_ctrl = spi_controller_get_devdata(spi->controller);
1040 txrx_buf = devm_kzalloc(as_ctrl->dev, SPI_NAND_CACHE_SIZE,
1041 GFP_KERNEL);
1042 if (!txrx_buf)
1043 return -ENOMEM;
1044
1045 spi_set_ctldata(spi, txrx_buf);
1046
1047 return 0;
1048 }
1049
airoha_snand_nfi_setup(struct airoha_snand_ctrl * as_ctrl)1050 static int airoha_snand_nfi_setup(struct airoha_snand_ctrl *as_ctrl)
1051 {
1052 u32 val, sec_size, sec_num;
1053 int err;
1054
1055 err = regmap_read(as_ctrl->regmap_nfi, REG_SPI_NFI_CON, &val);
1056 if (err)
1057 return err;
1058
1059 sec_num = FIELD_GET(SPI_NFI_SEC_NUM, val);
1060
1061 err = regmap_read(as_ctrl->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE, &val);
1062 if (err)
1063 return err;
1064
1065 sec_size = FIELD_GET(SPI_NFI_CUS_SEC_SIZE, val);
1066
1067 /* init default value */
1068 as_ctrl->nfi_cfg.sec_size = sec_size;
1069 as_ctrl->nfi_cfg.sec_num = sec_num;
1070 as_ctrl->nfi_cfg.page_size = round_down(sec_size * sec_num, 1024);
1071 as_ctrl->nfi_cfg.spare_size = 16;
1072
1073 err = airoha_snand_nfi_init(as_ctrl);
1074 if (err)
1075 return err;
1076
1077 return airoha_snand_nfi_config(as_ctrl);
1078 }
1079
1080 static const struct regmap_config spi_ctrl_regmap_config = {
1081 .name = "ctrl",
1082 .reg_bits = 32,
1083 .val_bits = 32,
1084 .reg_stride = 4,
1085 .max_register = REG_SPI_CTRL_NFI2SPI_EN,
1086 };
1087
1088 static const struct regmap_config spi_nfi_regmap_config = {
1089 .name = "nfi",
1090 .reg_bits = 32,
1091 .val_bits = 32,
1092 .reg_stride = 4,
1093 .max_register = REG_SPI_NFI_SNF_NFI_CNFG,
1094 };
1095
1096 static const struct of_device_id airoha_snand_ids[] = {
1097 { .compatible = "airoha,en7581-snand" },
1098 { /* sentinel */ }
1099 };
1100 MODULE_DEVICE_TABLE(of, airoha_snand_ids);
1101
airoha_snand_probe(struct platform_device * pdev)1102 static int airoha_snand_probe(struct platform_device *pdev)
1103 {
1104 struct airoha_snand_ctrl *as_ctrl;
1105 struct device *dev = &pdev->dev;
1106 struct spi_controller *ctrl;
1107 void __iomem *base;
1108 int err;
1109
1110 ctrl = devm_spi_alloc_host(dev, sizeof(*as_ctrl));
1111 if (!ctrl)
1112 return -ENOMEM;
1113
1114 as_ctrl = spi_controller_get_devdata(ctrl);
1115 as_ctrl->dev = dev;
1116
1117 base = devm_platform_ioremap_resource(pdev, 0);
1118 if (IS_ERR(base))
1119 return PTR_ERR(base);
1120
1121 as_ctrl->regmap_ctrl = devm_regmap_init_mmio(dev, base,
1122 &spi_ctrl_regmap_config);
1123 if (IS_ERR(as_ctrl->regmap_ctrl))
1124 return dev_err_probe(dev, PTR_ERR(as_ctrl->regmap_ctrl),
1125 "failed to init spi ctrl regmap\n");
1126
1127 base = devm_platform_ioremap_resource(pdev, 1);
1128 if (IS_ERR(base))
1129 return PTR_ERR(base);
1130
1131 as_ctrl->regmap_nfi = devm_regmap_init_mmio(dev, base,
1132 &spi_nfi_regmap_config);
1133 if (IS_ERR(as_ctrl->regmap_nfi))
1134 return dev_err_probe(dev, PTR_ERR(as_ctrl->regmap_nfi),
1135 "failed to init spi nfi regmap\n");
1136
1137 as_ctrl->spi_clk = devm_clk_get_enabled(dev, "spi");
1138 if (IS_ERR(as_ctrl->spi_clk))
1139 return dev_err_probe(dev, PTR_ERR(as_ctrl->spi_clk),
1140 "unable to get spi clk\n");
1141
1142 err = dma_set_mask(as_ctrl->dev, DMA_BIT_MASK(32));
1143 if (err)
1144 return err;
1145
1146 ctrl->num_chipselect = 2;
1147 ctrl->mem_ops = &airoha_snand_mem_ops;
1148 ctrl->bits_per_word_mask = SPI_BPW_MASK(8);
1149 ctrl->mode_bits = SPI_RX_DUAL;
1150 ctrl->setup = airoha_snand_setup;
1151 device_set_node(&ctrl->dev, dev_fwnode(dev));
1152
1153 err = airoha_snand_nfi_setup(as_ctrl);
1154 if (err)
1155 return err;
1156
1157 return devm_spi_register_controller(dev, ctrl);
1158 }
1159
1160 static struct platform_driver airoha_snand_driver = {
1161 .driver = {
1162 .name = "airoha-spi",
1163 .of_match_table = airoha_snand_ids,
1164 },
1165 .probe = airoha_snand_probe,
1166 };
1167 module_platform_driver(airoha_snand_driver);
1168
1169 MODULE_DESCRIPTION("Airoha SPI-NAND Flash Controller Driver");
1170 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
1171 MODULE_AUTHOR("Ray Liu <ray.liu@airoha.com>");
1172 MODULE_LICENSE("GPL");
1173