1 // SPDX-License-Identifier: GPL-2.0+
2 #include <linux/bitfield.h>
3 #include <linux/bitmap.h>
4 #include <linux/mfd/syscon.h>
5 #include <linux/module.h>
6 #include <linux/nvmem-consumer.h>
7 #include <linux/pinctrl/consumer.h>
8 #include <linux/phy.h>
9 #include <linux/regmap.h>
10 
11 #include "../phylib.h"
12 #include "mtk.h"
13 
14 #define MTK_GPHY_ID_MT7981			0x03a29461
15 #define MTK_GPHY_ID_MT7988			0x03a29481
16 
17 #define MTK_EXT_PAGE_ACCESS			0x1f
18 #define MTK_PHY_PAGE_STANDARD			0x0000
19 #define MTK_PHY_PAGE_EXTENDED_3			0x0003
20 
21 #define MTK_PHY_LPI_REG_14			0x14
22 #define MTK_PHY_LPI_WAKE_TIMER_1000_MASK	GENMASK(8, 0)
23 
24 #define MTK_PHY_LPI_REG_1c			0x1c
25 #define MTK_PHY_SMI_DET_ON_THRESH_MASK		GENMASK(13, 8)
26 
27 #define MTK_PHY_PAGE_EXTENDED_2A30		0x2a30
28 
29 /* Registers on Token Ring debug nodes */
30 /* ch_addr = 0x0, node_addr = 0x7, data_addr = 0x15 */
31 /* NormMseLoThresh */
32 #define NORMAL_MSE_LO_THRESH_MASK		GENMASK(15, 8)
33 
34 /* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */
35 /* RemAckCntLimitCtrl */
36 #define REMOTE_ACK_COUNT_LIMIT_CTRL_MASK	GENMASK(2, 1)
37 
38 /* ch_addr = 0x1, node_addr = 0xd, data_addr = 0x20 */
39 /* VcoSlicerThreshBitsHigh */
40 #define VCO_SLICER_THRESH_HIGH_MASK		GENMASK(23, 0)
41 
42 /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x0 */
43 /* DfeTailEnableVgaThresh1000 */
44 #define DFE_TAIL_EANBLE_VGA_TRHESH_1000		GENMASK(5, 1)
45 
46 /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x1 */
47 /* MrvlTrFix100Kp */
48 #define MRVL_TR_FIX_100KP_MASK			GENMASK(22, 20)
49 /* MrvlTrFix100Kf */
50 #define MRVL_TR_FIX_100KF_MASK			GENMASK(19, 17)
51 /* MrvlTrFix1000Kp */
52 #define MRVL_TR_FIX_1000KP_MASK			GENMASK(16, 14)
53 /* MrvlTrFix1000Kf */
54 #define MRVL_TR_FIX_1000KF_MASK			GENMASK(13, 11)
55 
56 /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x12 */
57 /* VgaDecRate */
58 #define VGA_DECIMATION_RATE_MASK		GENMASK(8, 5)
59 
60 /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */
61 /* SlvDSPreadyTime */
62 #define SLAVE_DSP_READY_TIME_MASK		GENMASK(22, 15)
63 /* MasDSPreadyTime */
64 #define MASTER_DSP_READY_TIME_MASK		GENMASK(14, 7)
65 
66 /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x18 */
67 /* EnabRandUpdTrig */
68 #define ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER	BIT(8)
69 
70 /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x20 */
71 /* ResetSyncOffset */
72 #define RESET_SYNC_OFFSET_MASK			GENMASK(11, 8)
73 
74 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x0 */
75 /* FfeUpdGainForceVal */
76 #define FFE_UPDATE_GAIN_FORCE_VAL_MASK		GENMASK(9, 7)
77 /* FfeUpdGainForce */
78 #define FFE_UPDATE_GAIN_FORCE			BIT(6)
79 
80 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x3 */
81 /* TrFreeze */
82 #define TR_FREEZE_MASK				GENMASK(11, 0)
83 
84 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x6 */
85 /* SS: Steady-state, KP: Proportional Gain */
86 /* SSTrKp100 */
87 #define SS_TR_KP100_MASK			GENMASK(21, 19)
88 /* SSTrKf100 */
89 #define SS_TR_KF100_MASK			GENMASK(18, 16)
90 /* SSTrKp1000Mas */
91 #define SS_TR_KP1000_MASTER_MASK		GENMASK(15, 13)
92 /* SSTrKf1000Mas */
93 #define SS_TR_KF1000_MASTER_MASK		GENMASK(12, 10)
94 /* SSTrKp1000Slv */
95 #define SS_TR_KP1000_SLAVE_MASK			GENMASK(9, 7)
96 /* SSTrKf1000Slv */
97 #define SS_TR_KF1000_SLAVE_MASK			GENMASK(6, 4)
98 
99 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x8 */
100 /* clear this bit if wanna select from AFE */
101 /* Regsigdet_sel_1000 */
102 #define EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE	BIT(4)
103 
104 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xd */
105 /* RegEEE_st2TrKf1000 */
106 #define EEE1000_STAGE2_TR_KF_MASK		GENMASK(13, 11)
107 
108 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xf */
109 /* RegEEE_slv_waketr_timer_tar */
110 #define SLAVE_WAKETR_TIMER_MASK			GENMASK(20, 11)
111 /* RegEEE_slv_remtx_timer_tar */
112 #define SLAVE_REMTX_TIMER_MASK			GENMASK(10, 1)
113 
114 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x10 */
115 /* RegEEE_slv_wake_int_timer_tar */
116 #define SLAVE_WAKEINT_TIMER_MASK		GENMASK(10, 1)
117 
118 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x14 */
119 /* RegEEE_trfreeze_timer2 */
120 #define TR_FREEZE_TIMER2_MASK			GENMASK(9, 0)
121 
122 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x1c */
123 /* RegEEE100Stg1_tar */
124 #define EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK	GENMASK(8, 0)
125 
126 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x25 */
127 /* REGEEE_wake_slv_tr_wait_dfesigdet_en */
128 #define WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN	BIT(11)
129 
130 #define ANALOG_INTERNAL_OPERATION_MAX_US	20
131 #define TXRESERVE_MIN				0
132 #define TXRESERVE_MAX				7
133 
134 #define MTK_PHY_ANARG_RG			0x10
135 #define   MTK_PHY_TCLKOFFSET_MASK		GENMASK(12, 8)
136 
137 /* Registers on MDIO_MMD_VEND1 */
138 #define MTK_PHY_TXVLD_DA_RG			0x12
139 #define   MTK_PHY_DA_TX_I2MPB_A_GBE_MASK	GENMASK(15, 10)
140 #define   MTK_PHY_DA_TX_I2MPB_A_TBT_MASK	GENMASK(5, 0)
141 
142 #define MTK_PHY_TX_I2MPB_TEST_MODE_A2		0x16
143 #define   MTK_PHY_DA_TX_I2MPB_A_HBT_MASK	GENMASK(15, 10)
144 #define   MTK_PHY_DA_TX_I2MPB_A_TST_MASK	GENMASK(5, 0)
145 
146 #define MTK_PHY_TX_I2MPB_TEST_MODE_B1		0x17
147 #define   MTK_PHY_DA_TX_I2MPB_B_GBE_MASK	GENMASK(13, 8)
148 #define   MTK_PHY_DA_TX_I2MPB_B_TBT_MASK	GENMASK(5, 0)
149 
150 #define MTK_PHY_TX_I2MPB_TEST_MODE_B2		0x18
151 #define   MTK_PHY_DA_TX_I2MPB_B_HBT_MASK	GENMASK(13, 8)
152 #define   MTK_PHY_DA_TX_I2MPB_B_TST_MASK	GENMASK(5, 0)
153 
154 #define MTK_PHY_TX_I2MPB_TEST_MODE_C1		0x19
155 #define   MTK_PHY_DA_TX_I2MPB_C_GBE_MASK	GENMASK(13, 8)
156 #define   MTK_PHY_DA_TX_I2MPB_C_TBT_MASK	GENMASK(5, 0)
157 
158 #define MTK_PHY_TX_I2MPB_TEST_MODE_C2		0x20
159 #define   MTK_PHY_DA_TX_I2MPB_C_HBT_MASK	GENMASK(13, 8)
160 #define   MTK_PHY_DA_TX_I2MPB_C_TST_MASK	GENMASK(5, 0)
161 
162 #define MTK_PHY_TX_I2MPB_TEST_MODE_D1		0x21
163 #define   MTK_PHY_DA_TX_I2MPB_D_GBE_MASK	GENMASK(13, 8)
164 #define   MTK_PHY_DA_TX_I2MPB_D_TBT_MASK	GENMASK(5, 0)
165 
166 #define MTK_PHY_TX_I2MPB_TEST_MODE_D2		0x22
167 #define   MTK_PHY_DA_TX_I2MPB_D_HBT_MASK	GENMASK(13, 8)
168 #define   MTK_PHY_DA_TX_I2MPB_D_TST_MASK	GENMASK(5, 0)
169 
170 #define MTK_PHY_RXADC_CTRL_RG7			0xc6
171 #define   MTK_PHY_DA_AD_BUF_BIAS_LP_MASK	GENMASK(9, 8)
172 
173 #define MTK_PHY_RXADC_CTRL_RG9			0xc8
174 #define   MTK_PHY_DA_RX_PSBN_TBT_MASK		GENMASK(14, 12)
175 #define   MTK_PHY_DA_RX_PSBN_HBT_MASK		GENMASK(10, 8)
176 #define   MTK_PHY_DA_RX_PSBN_GBE_MASK		GENMASK(6, 4)
177 #define   MTK_PHY_DA_RX_PSBN_LP_MASK		GENMASK(2, 0)
178 
179 #define MTK_PHY_LDO_OUTPUT_V			0xd7
180 
181 #define MTK_PHY_RG_ANA_CAL_RG0			0xdb
182 #define   MTK_PHY_RG_CAL_CKINV			BIT(12)
183 #define   MTK_PHY_RG_ANA_CALEN			BIT(8)
184 #define   MTK_PHY_RG_ZCALEN_A			BIT(0)
185 
186 #define MTK_PHY_RG_ANA_CAL_RG1			0xdc
187 #define   MTK_PHY_RG_ZCALEN_B			BIT(12)
188 #define   MTK_PHY_RG_ZCALEN_C			BIT(8)
189 #define   MTK_PHY_RG_ZCALEN_D			BIT(4)
190 #define   MTK_PHY_RG_TXVOS_CALEN		BIT(0)
191 
192 #define MTK_PHY_RG_ANA_CAL_RG5			0xe0
193 #define   MTK_PHY_RG_REXT_TRIM_MASK		GENMASK(13, 8)
194 
195 #define MTK_PHY_RG_TX_FILTER			0xfe
196 
197 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120	0x120
198 #define   MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK	GENMASK(12, 8)
199 #define   MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK	GENMASK(4, 0)
200 
201 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122	0x122
202 #define   MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK	GENMASK(7, 0)
203 
204 #define MTK_PHY_RG_TESTMUX_ADC_CTRL		0x144
205 #define   MTK_PHY_RG_TXEN_DIG_MASK		GENMASK(5, 5)
206 
207 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B		0x172
208 #define   MTK_PHY_CR_TX_AMP_OFFSET_A_MASK	GENMASK(13, 8)
209 #define   MTK_PHY_CR_TX_AMP_OFFSET_B_MASK	GENMASK(6, 0)
210 
211 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D		0x173
212 #define   MTK_PHY_CR_TX_AMP_OFFSET_C_MASK	GENMASK(13, 8)
213 #define   MTK_PHY_CR_TX_AMP_OFFSET_D_MASK	GENMASK(6, 0)
214 
215 #define MTK_PHY_RG_AD_CAL_COMP			0x17a
216 #define   MTK_PHY_AD_CAL_COMP_OUT_MASK		GENMASK(8, 8)
217 
218 #define MTK_PHY_RG_AD_CAL_CLK			0x17b
219 #define   MTK_PHY_DA_CAL_CLK			BIT(0)
220 
221 #define MTK_PHY_RG_AD_CALIN			0x17c
222 #define   MTK_PHY_DA_CALIN_FLAG			BIT(0)
223 
224 #define MTK_PHY_RG_DASN_DAC_IN0_A		0x17d
225 #define   MTK_PHY_DASN_DAC_IN0_A_MASK		GENMASK(9, 0)
226 
227 #define MTK_PHY_RG_DASN_DAC_IN0_B		0x17e
228 #define   MTK_PHY_DASN_DAC_IN0_B_MASK		GENMASK(9, 0)
229 
230 #define MTK_PHY_RG_DASN_DAC_IN0_C		0x17f
231 #define   MTK_PHY_DASN_DAC_IN0_C_MASK		GENMASK(9, 0)
232 
233 #define MTK_PHY_RG_DASN_DAC_IN0_D		0x180
234 #define   MTK_PHY_DASN_DAC_IN0_D_MASK		GENMASK(9, 0)
235 
236 #define MTK_PHY_RG_DASN_DAC_IN1_A		0x181
237 #define   MTK_PHY_DASN_DAC_IN1_A_MASK		GENMASK(9, 0)
238 
239 #define MTK_PHY_RG_DASN_DAC_IN1_B		0x182
240 #define   MTK_PHY_DASN_DAC_IN1_B_MASK		GENMASK(9, 0)
241 
242 #define MTK_PHY_RG_DASN_DAC_IN1_C		0x183
243 #define   MTK_PHY_DASN_DAC_IN1_C_MASK		GENMASK(9, 0)
244 
245 #define MTK_PHY_RG_DASN_DAC_IN1_D		0x184
246 #define   MTK_PHY_DASN_DAC_IN1_D_MASK		GENMASK(9, 0)
247 
248 #define MTK_PHY_RG_DEV1E_REG19b			0x19b
249 #define   MTK_PHY_BYPASS_DSP_LPI_READY		BIT(8)
250 
251 #define MTK_PHY_RG_LP_IIR2_K1_L			0x22a
252 #define MTK_PHY_RG_LP_IIR2_K1_U			0x22b
253 #define MTK_PHY_RG_LP_IIR2_K2_L			0x22c
254 #define MTK_PHY_RG_LP_IIR2_K2_U			0x22d
255 #define MTK_PHY_RG_LP_IIR2_K3_L			0x22e
256 #define MTK_PHY_RG_LP_IIR2_K3_U			0x22f
257 #define MTK_PHY_RG_LP_IIR2_K4_L			0x230
258 #define MTK_PHY_RG_LP_IIR2_K4_U			0x231
259 #define MTK_PHY_RG_LP_IIR2_K5_L			0x232
260 #define MTK_PHY_RG_LP_IIR2_K5_U			0x233
261 
262 #define MTK_PHY_RG_DEV1E_REG234			0x234
263 #define   MTK_PHY_TR_OPEN_LOOP_EN_MASK		GENMASK(0, 0)
264 #define   MTK_PHY_LPF_X_AVERAGE_MASK		GENMASK(7, 4)
265 #define   MTK_PHY_TR_LP_IIR_EEE_EN		BIT(12)
266 
267 #define MTK_PHY_RG_LPF_CNT_VAL			0x235
268 
269 #define MTK_PHY_RG_DEV1E_REG238			0x238
270 #define   MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK	GENMASK(8, 0)
271 #define   MTK_PHY_LPI_SLV_SEND_TX_EN		BIT(12)
272 
273 #define MTK_PHY_RG_DEV1E_REG239			0x239
274 #define   MTK_PHY_LPI_SEND_LOC_TIMER_MASK	GENMASK(8, 0)
275 #define   MTK_PHY_LPI_TXPCS_LOC_RCV		BIT(12)
276 
277 #define MTK_PHY_RG_DEV1E_REG27C			0x27c
278 #define   MTK_PHY_VGASTATE_FFE_THR_ST1_MASK	GENMASK(12, 8)
279 #define MTK_PHY_RG_DEV1E_REG27D			0x27d
280 #define   MTK_PHY_VGASTATE_FFE_THR_ST2_MASK	GENMASK(4, 0)
281 
282 #define MTK_PHY_RG_DEV1E_REG2C7			0x2c7
283 #define   MTK_PHY_MAX_GAIN_MASK			GENMASK(4, 0)
284 #define   MTK_PHY_MIN_GAIN_MASK			GENMASK(12, 8)
285 
286 #define MTK_PHY_RG_DEV1E_REG2D1			0x2d1
287 #define   MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK	GENMASK(7, 0)
288 #define   MTK_PHY_LPI_SKIP_SD_SLV_TR		BIT(8)
289 #define   MTK_PHY_LPI_TR_READY			BIT(9)
290 #define   MTK_PHY_LPI_VCO_EEE_STG0_EN		BIT(10)
291 
292 #define MTK_PHY_RG_DEV1E_REG323			0x323
293 #define   MTK_PHY_EEE_WAKE_MAS_INT_DC		BIT(0)
294 #define   MTK_PHY_EEE_WAKE_SLV_INT_DC		BIT(4)
295 
296 #define MTK_PHY_RG_DEV1E_REG324			0x324
297 #define   MTK_PHY_SMI_DETCNT_MAX_MASK		GENMASK(5, 0)
298 #define   MTK_PHY_SMI_DET_MAX_EN		BIT(8)
299 
300 #define MTK_PHY_RG_DEV1E_REG326			0x326
301 #define   MTK_PHY_LPI_MODE_SD_ON		BIT(0)
302 #define   MTK_PHY_RESET_RANDUPD_CNT		BIT(1)
303 #define   MTK_PHY_TREC_UPDATE_ENAB_CLR		BIT(2)
304 #define   MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF	BIT(4)
305 #define   MTK_PHY_TR_READY_SKIP_AFE_WAKEUP	BIT(5)
306 
307 #define MTK_PHY_LDO_PUMP_EN_PAIRAB		0x502
308 #define MTK_PHY_LDO_PUMP_EN_PAIRCD		0x503
309 
310 #define MTK_PHY_DA_TX_R50_PAIR_A		0x53d
311 #define MTK_PHY_DA_TX_R50_PAIR_B		0x53e
312 #define MTK_PHY_DA_TX_R50_PAIR_C		0x53f
313 #define MTK_PHY_DA_TX_R50_PAIR_D		0x540
314 
315 /* Registers on MDIO_MMD_VEND2 */
316 #define MTK_PHY_LED1_DEFAULT_POLARITIES		BIT(1)
317 
318 #define MTK_PHY_RG_BG_RASEL			0x115
319 #define   MTK_PHY_RG_BG_RASEL_MASK		GENMASK(2, 0)
320 
321 /* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */
322 #define RG_GPIO_MISC_TPBANK0			0x6f0
323 #define   RG_GPIO_MISC_TPBANK0_BOOTMODE		GENMASK(11, 8)
324 
325 /* These macro privides efuse parsing for internal phy. */
326 #define EFS_DA_TX_I2MPB_A(x)			(((x) >> 0) & GENMASK(5, 0))
327 #define EFS_DA_TX_I2MPB_B(x)			(((x) >> 6) & GENMASK(5, 0))
328 #define EFS_DA_TX_I2MPB_C(x)			(((x) >> 12) & GENMASK(5, 0))
329 #define EFS_DA_TX_I2MPB_D(x)			(((x) >> 18) & GENMASK(5, 0))
330 #define EFS_DA_TX_AMP_OFFSET_A(x)		(((x) >> 24) & GENMASK(5, 0))
331 
332 #define EFS_DA_TX_AMP_OFFSET_B(x)		(((x) >> 0) & GENMASK(5, 0))
333 #define EFS_DA_TX_AMP_OFFSET_C(x)		(((x) >> 6) & GENMASK(5, 0))
334 #define EFS_DA_TX_AMP_OFFSET_D(x)		(((x) >> 12) & GENMASK(5, 0))
335 #define EFS_DA_TX_R50_A(x)			(((x) >> 18) & GENMASK(5, 0))
336 #define EFS_DA_TX_R50_B(x)			(((x) >> 24) & GENMASK(5, 0))
337 
338 #define EFS_DA_TX_R50_C(x)			(((x) >> 0) & GENMASK(5, 0))
339 #define EFS_DA_TX_R50_D(x)			(((x) >> 6) & GENMASK(5, 0))
340 
341 #define EFS_RG_BG_RASEL(x)			(((x) >> 4) & GENMASK(2, 0))
342 #define EFS_RG_REXT_TRIM(x)			(((x) >> 7) & GENMASK(5, 0))
343 
344 enum {
345 	NO_PAIR,
346 	PAIR_A,
347 	PAIR_B,
348 	PAIR_C,
349 	PAIR_D,
350 };
351 
352 enum calibration_mode {
353 	EFUSE_K,
354 	SW_K
355 };
356 
357 enum CAL_ITEM {
358 	REXT,
359 	TX_OFFSET,
360 	TX_AMP,
361 	TX_R50,
362 	TX_VCM
363 };
364 
365 enum CAL_MODE {
366 	EFUSE_M,
367 	SW_M
368 };
369 
370 struct mtk_socphy_shared {
371 	u32			boottrap;
372 	struct mtk_socphy_priv	priv[4];
373 };
374 
375 /* One calibration cycle consists of:
376  * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
377  *   until AD_CAL_COMP is ready to output calibration result.
378  * 2.Wait until DA_CAL_CLK is available.
379  * 3.Fetch AD_CAL_COMP_OUT.
380  */
cal_cycle(struct phy_device * phydev,int devad,u32 regnum,u16 mask,u16 cal_val)381 static int cal_cycle(struct phy_device *phydev, int devad,
382 		     u32 regnum, u16 mask, u16 cal_val)
383 {
384 	int reg_val;
385 	int ret;
386 
387 	phy_modify_mmd(phydev, devad, regnum,
388 		       mask, cal_val);
389 	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
390 			 MTK_PHY_DA_CALIN_FLAG);
391 
392 	ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
393 					MTK_PHY_RG_AD_CAL_CLK, reg_val,
394 					reg_val & MTK_PHY_DA_CAL_CLK, 500,
395 					ANALOG_INTERNAL_OPERATION_MAX_US,
396 					false);
397 	if (ret) {
398 		phydev_err(phydev, "Calibration cycle timeout\n");
399 		return ret;
400 	}
401 
402 	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
403 			   MTK_PHY_DA_CALIN_FLAG);
404 	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP);
405 	if (ret < 0)
406 		return ret;
407 	ret = FIELD_GET(MTK_PHY_AD_CAL_COMP_OUT_MASK, ret);
408 	phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
409 
410 	return ret;
411 }
412 
rext_fill_result(struct phy_device * phydev,u16 * buf)413 static int rext_fill_result(struct phy_device *phydev, u16 *buf)
414 {
415 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
416 		       MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8);
417 	phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL,
418 		       MTK_PHY_RG_BG_RASEL_MASK, buf[1]);
419 
420 	return 0;
421 }
422 
rext_cal_efuse(struct phy_device * phydev,u32 * buf)423 static int rext_cal_efuse(struct phy_device *phydev, u32 *buf)
424 {
425 	u16 rext_cal_val[2];
426 
427 	rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]);
428 	rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]);
429 	rext_fill_result(phydev, rext_cal_val);
430 
431 	return 0;
432 }
433 
tx_offset_fill_result(struct phy_device * phydev,u16 * buf)434 static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf)
435 {
436 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
437 		       MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8);
438 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
439 		       MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]);
440 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
441 		       MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8);
442 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
443 		       MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]);
444 
445 	return 0;
446 }
447 
tx_offset_cal_efuse(struct phy_device * phydev,u32 * buf)448 static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf)
449 {
450 	u16 tx_offset_cal_val[4];
451 
452 	tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]);
453 	tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]);
454 	tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]);
455 	tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]);
456 
457 	tx_offset_fill_result(phydev, tx_offset_cal_val);
458 
459 	return 0;
460 }
461 
tx_amp_fill_result(struct phy_device * phydev,u16 * buf)462 static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
463 {
464 	const int vals_9481[16] = { 10, 6, 6, 10,
465 				    10, 6, 6, 10,
466 				    10, 6, 6, 10,
467 				    10, 6, 6, 10 };
468 	const int vals_9461[16] = { 7, 1, 4, 7,
469 				    7, 1, 4, 7,
470 				    7, 1, 4, 7,
471 				    7, 1, 4, 7 };
472 	int bias[16] = {};
473 	int i;
474 
475 	switch (phydev->drv->phy_id) {
476 	case MTK_GPHY_ID_MT7981:
477 		/* We add some calibration to efuse values
478 		 * due to board level influence.
479 		 * GBE: +7, TBT: +1, HBT: +4, TST: +7
480 		 */
481 		memcpy(bias, (const void *)vals_9461, sizeof(bias));
482 		break;
483 	case MTK_GPHY_ID_MT7988:
484 		memcpy(bias, (const void *)vals_9481, sizeof(bias));
485 		break;
486 	}
487 
488 	/* Prevent overflow */
489 	for (i = 0; i < 12; i++) {
490 		if (buf[i >> 2] + bias[i] > 63) {
491 			buf[i >> 2] = 63;
492 			bias[i] = 0;
493 		}
494 	}
495 
496 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
497 		       MTK_PHY_DA_TX_I2MPB_A_GBE_MASK,
498 		       FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_GBE_MASK,
499 				  buf[0] + bias[0]));
500 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
501 		       MTK_PHY_DA_TX_I2MPB_A_TBT_MASK,
502 		       FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TBT_MASK,
503 				  buf[0] + bias[1]));
504 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
505 		       MTK_PHY_DA_TX_I2MPB_A_HBT_MASK,
506 		       FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_HBT_MASK,
507 				  buf[0] + bias[2]));
508 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
509 		       MTK_PHY_DA_TX_I2MPB_A_TST_MASK,
510 		       FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TST_MASK,
511 				  buf[0] + bias[3]));
512 
513 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
514 		       MTK_PHY_DA_TX_I2MPB_B_GBE_MASK,
515 		       FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_GBE_MASK,
516 				  buf[1] + bias[4]));
517 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
518 		       MTK_PHY_DA_TX_I2MPB_B_TBT_MASK,
519 		       FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TBT_MASK,
520 				  buf[1] + bias[5]));
521 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
522 		       MTK_PHY_DA_TX_I2MPB_B_HBT_MASK,
523 		       FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_HBT_MASK,
524 				  buf[1] + bias[6]));
525 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
526 		       MTK_PHY_DA_TX_I2MPB_B_TST_MASK,
527 		       FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TST_MASK,
528 				  buf[1] + bias[7]));
529 
530 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
531 		       MTK_PHY_DA_TX_I2MPB_C_GBE_MASK,
532 		       FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_GBE_MASK,
533 				  buf[2] + bias[8]));
534 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
535 		       MTK_PHY_DA_TX_I2MPB_C_TBT_MASK,
536 		       FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TBT_MASK,
537 				  buf[2] + bias[9]));
538 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
539 		       MTK_PHY_DA_TX_I2MPB_C_HBT_MASK,
540 		       FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_HBT_MASK,
541 				  buf[2] + bias[10]));
542 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
543 		       MTK_PHY_DA_TX_I2MPB_C_TST_MASK,
544 		       FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TST_MASK,
545 				  buf[2] + bias[11]));
546 
547 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
548 		       MTK_PHY_DA_TX_I2MPB_D_GBE_MASK,
549 		       FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_GBE_MASK,
550 				  buf[3] + bias[12]));
551 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
552 		       MTK_PHY_DA_TX_I2MPB_D_TBT_MASK,
553 		       FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TBT_MASK,
554 				  buf[3] + bias[13]));
555 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
556 		       MTK_PHY_DA_TX_I2MPB_D_HBT_MASK,
557 		       FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_HBT_MASK,
558 				  buf[3] + bias[14]));
559 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
560 		       MTK_PHY_DA_TX_I2MPB_D_TST_MASK,
561 		       FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TST_MASK,
562 				  buf[3] + bias[15]));
563 
564 	return 0;
565 }
566 
tx_amp_cal_efuse(struct phy_device * phydev,u32 * buf)567 static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf)
568 {
569 	u16 tx_amp_cal_val[4];
570 
571 	tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]);
572 	tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]);
573 	tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]);
574 	tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]);
575 	tx_amp_fill_result(phydev, tx_amp_cal_val);
576 
577 	return 0;
578 }
579 
tx_r50_fill_result(struct phy_device * phydev,u16 tx_r50_cal_val,u8 txg_calen_x)580 static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val,
581 			      u8 txg_calen_x)
582 {
583 	int bias = 0;
584 	u16 reg, val;
585 
586 	if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
587 		bias = -1;
588 
589 	val = clamp_val(bias + tx_r50_cal_val, 0, 63);
590 
591 	switch (txg_calen_x) {
592 	case PAIR_A:
593 		reg = MTK_PHY_DA_TX_R50_PAIR_A;
594 		break;
595 	case PAIR_B:
596 		reg = MTK_PHY_DA_TX_R50_PAIR_B;
597 		break;
598 	case PAIR_C:
599 		reg = MTK_PHY_DA_TX_R50_PAIR_C;
600 		break;
601 	case PAIR_D:
602 		reg = MTK_PHY_DA_TX_R50_PAIR_D;
603 		break;
604 	default:
605 		return -EINVAL;
606 	}
607 
608 	phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8);
609 
610 	return 0;
611 }
612 
tx_r50_cal_efuse(struct phy_device * phydev,u32 * buf,u8 txg_calen_x)613 static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf,
614 			    u8 txg_calen_x)
615 {
616 	u16 tx_r50_cal_val;
617 
618 	switch (txg_calen_x) {
619 	case PAIR_A:
620 		tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]);
621 		break;
622 	case PAIR_B:
623 		tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]);
624 		break;
625 	case PAIR_C:
626 		tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]);
627 		break;
628 	case PAIR_D:
629 		tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]);
630 		break;
631 	default:
632 		return -EINVAL;
633 	}
634 	tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
635 
636 	return 0;
637 }
638 
tx_vcm_cal_sw(struct phy_device * phydev,u8 rg_txreserve_x)639 static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
640 {
641 	u8 lower_idx, upper_idx, txreserve_val;
642 	u8 lower_ret, upper_ret;
643 	int ret;
644 
645 	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
646 			 MTK_PHY_RG_ANA_CALEN);
647 	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
648 			   MTK_PHY_RG_CAL_CKINV);
649 	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
650 			 MTK_PHY_RG_TXVOS_CALEN);
651 
652 	switch (rg_txreserve_x) {
653 	case PAIR_A:
654 		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
655 				   MTK_PHY_RG_DASN_DAC_IN0_A,
656 				   MTK_PHY_DASN_DAC_IN0_A_MASK);
657 		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
658 				   MTK_PHY_RG_DASN_DAC_IN1_A,
659 				   MTK_PHY_DASN_DAC_IN1_A_MASK);
660 		phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
661 				 MTK_PHY_RG_ANA_CAL_RG0,
662 				 MTK_PHY_RG_ZCALEN_A);
663 		break;
664 	case PAIR_B:
665 		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
666 				   MTK_PHY_RG_DASN_DAC_IN0_B,
667 				   MTK_PHY_DASN_DAC_IN0_B_MASK);
668 		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
669 				   MTK_PHY_RG_DASN_DAC_IN1_B,
670 				   MTK_PHY_DASN_DAC_IN1_B_MASK);
671 		phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
672 				 MTK_PHY_RG_ANA_CAL_RG1,
673 				 MTK_PHY_RG_ZCALEN_B);
674 		break;
675 	case PAIR_C:
676 		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
677 				   MTK_PHY_RG_DASN_DAC_IN0_C,
678 				   MTK_PHY_DASN_DAC_IN0_C_MASK);
679 		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
680 				   MTK_PHY_RG_DASN_DAC_IN1_C,
681 				   MTK_PHY_DASN_DAC_IN1_C_MASK);
682 		phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
683 				 MTK_PHY_RG_ANA_CAL_RG1,
684 				 MTK_PHY_RG_ZCALEN_C);
685 		break;
686 	case PAIR_D:
687 		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
688 				   MTK_PHY_RG_DASN_DAC_IN0_D,
689 				   MTK_PHY_DASN_DAC_IN0_D_MASK);
690 		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
691 				   MTK_PHY_RG_DASN_DAC_IN1_D,
692 				   MTK_PHY_DASN_DAC_IN1_D_MASK);
693 		phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
694 				 MTK_PHY_RG_ANA_CAL_RG1,
695 				 MTK_PHY_RG_ZCALEN_D);
696 		break;
697 	default:
698 		ret = -EINVAL;
699 		goto restore;
700 	}
701 
702 	lower_idx = TXRESERVE_MIN;
703 	upper_idx = TXRESERVE_MAX;
704 
705 	phydev_dbg(phydev, "Start TX-VCM SW cal.\n");
706 	while ((upper_idx - lower_idx) > 1) {
707 		txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2);
708 		ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
709 				MTK_PHY_DA_RX_PSBN_TBT_MASK |
710 				MTK_PHY_DA_RX_PSBN_HBT_MASK |
711 				MTK_PHY_DA_RX_PSBN_GBE_MASK |
712 				MTK_PHY_DA_RX_PSBN_LP_MASK,
713 				txreserve_val << 12 | txreserve_val << 8 |
714 				txreserve_val << 4 | txreserve_val);
715 		if (ret == 1) {
716 			upper_idx = txreserve_val;
717 			upper_ret = ret;
718 		} else if (ret == 0) {
719 			lower_idx = txreserve_val;
720 			lower_ret = ret;
721 		} else {
722 			goto restore;
723 		}
724 	}
725 
726 	if (lower_idx == TXRESERVE_MIN) {
727 		lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
728 				      MTK_PHY_RXADC_CTRL_RG9,
729 				      MTK_PHY_DA_RX_PSBN_TBT_MASK |
730 				      MTK_PHY_DA_RX_PSBN_HBT_MASK |
731 				      MTK_PHY_DA_RX_PSBN_GBE_MASK |
732 				      MTK_PHY_DA_RX_PSBN_LP_MASK,
733 				      lower_idx << 12 | lower_idx << 8 |
734 				      lower_idx << 4 | lower_idx);
735 		ret = lower_ret;
736 	} else if (upper_idx == TXRESERVE_MAX) {
737 		upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
738 				      MTK_PHY_RXADC_CTRL_RG9,
739 				      MTK_PHY_DA_RX_PSBN_TBT_MASK |
740 				      MTK_PHY_DA_RX_PSBN_HBT_MASK |
741 				      MTK_PHY_DA_RX_PSBN_GBE_MASK |
742 				      MTK_PHY_DA_RX_PSBN_LP_MASK,
743 				      upper_idx << 12 | upper_idx << 8 |
744 				      upper_idx << 4 | upper_idx);
745 		ret = upper_ret;
746 	}
747 	if (ret < 0)
748 		goto restore;
749 
750 	/* We calibrate TX-VCM in different logic. Check upper index and then
751 	 * lower index. If this calibration is valid, apply lower index's
752 	 * result.
753 	 */
754 	ret = upper_ret - lower_ret;
755 	if (ret == 1) {
756 		ret = 0;
757 		/* Make sure we use upper_idx in our calibration system */
758 		cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
759 			  MTK_PHY_DA_RX_PSBN_TBT_MASK |
760 			  MTK_PHY_DA_RX_PSBN_HBT_MASK |
761 			  MTK_PHY_DA_RX_PSBN_GBE_MASK |
762 			  MTK_PHY_DA_RX_PSBN_LP_MASK,
763 			  upper_idx << 12 | upper_idx << 8 |
764 			  upper_idx << 4 | upper_idx);
765 		phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx);
766 	} else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 &&
767 		   lower_ret == 1) {
768 		ret = 0;
769 		cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
770 			  MTK_PHY_DA_RX_PSBN_TBT_MASK |
771 			  MTK_PHY_DA_RX_PSBN_HBT_MASK |
772 			  MTK_PHY_DA_RX_PSBN_GBE_MASK |
773 			  MTK_PHY_DA_RX_PSBN_LP_MASK,
774 			  lower_idx << 12 | lower_idx << 8 |
775 			  lower_idx << 4 | lower_idx);
776 		phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n",
777 			    lower_idx);
778 	} else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
779 		   lower_ret == 0) {
780 		ret = 0;
781 		phydev_warn(phydev,
782 			    "TX-VCM SW cal result at high margin 0x%x\n",
783 			    upper_idx);
784 	} else {
785 		ret = -EINVAL;
786 	}
787 
788 restore:
789 	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
790 			   MTK_PHY_RG_ANA_CALEN);
791 	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
792 			   MTK_PHY_RG_TXVOS_CALEN);
793 	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
794 			   MTK_PHY_RG_ZCALEN_A);
795 	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
796 			   MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C |
797 			   MTK_PHY_RG_ZCALEN_D);
798 
799 	return ret;
800 }
801 
mt798x_phy_common_finetune(struct phy_device * phydev)802 static void mt798x_phy_common_finetune(struct phy_device *phydev)
803 {
804 	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
805 	__mtk_tr_modify(phydev, 0x1, 0xf, 0x17,
806 			SLAVE_DSP_READY_TIME_MASK | MASTER_DSP_READY_TIME_MASK,
807 			FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x18) |
808 			FIELD_PREP(MASTER_DSP_READY_TIME_MASK, 0x18));
809 
810 	__mtk_tr_set_bits(phydev, 0x1, 0xf, 0x18,
811 			  ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER);
812 
813 	__mtk_tr_modify(phydev, 0x0, 0x7, 0x15,
814 			NORMAL_MSE_LO_THRESH_MASK,
815 			FIELD_PREP(NORMAL_MSE_LO_THRESH_MASK, 0x55));
816 
817 	__mtk_tr_modify(phydev, 0x2, 0xd, 0x0,
818 			FFE_UPDATE_GAIN_FORCE_VAL_MASK,
819 			FIELD_PREP(FFE_UPDATE_GAIN_FORCE_VAL_MASK, 0x4) |
820 				   FFE_UPDATE_GAIN_FORCE);
821 
822 	__mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x3, TR_FREEZE_MASK);
823 
824 	__mtk_tr_modify(phydev, 0x2, 0xd, 0x6,
825 			SS_TR_KP100_MASK | SS_TR_KF100_MASK |
826 			SS_TR_KP1000_MASTER_MASK | SS_TR_KF1000_MASTER_MASK |
827 			SS_TR_KP1000_SLAVE_MASK | SS_TR_KF1000_SLAVE_MASK,
828 			FIELD_PREP(SS_TR_KP100_MASK, 0x5) |
829 			FIELD_PREP(SS_TR_KF100_MASK, 0x6) |
830 			FIELD_PREP(SS_TR_KP1000_MASTER_MASK, 0x5) |
831 			FIELD_PREP(SS_TR_KF1000_MASTER_MASK, 0x6) |
832 			FIELD_PREP(SS_TR_KP1000_SLAVE_MASK, 0x5) |
833 			FIELD_PREP(SS_TR_KF1000_SLAVE_MASK, 0x6));
834 
835 	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
836 }
837 
mt7981_phy_finetune(struct phy_device * phydev)838 static void mt7981_phy_finetune(struct phy_device *phydev)
839 {
840 	u16 val[8] = { 0x01ce, 0x01c1,
841 		       0x020f, 0x0202,
842 		       0x03d0, 0x03c0,
843 		       0x0013, 0x0005 };
844 	int i, k;
845 
846 	/* 100M eye finetune:
847 	 * Keep middle level of TX MLT3 shapper as default.
848 	 * Only change TX MLT3 overshoot level here.
849 	 */
850 	for (k = 0, i = 1; i < 12; i++) {
851 		if (i % 3 == 0)
852 			continue;
853 		phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
854 	}
855 
856 	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
857 	__mtk_tr_modify(phydev, 0x1, 0xf, 0x20,
858 			RESET_SYNC_OFFSET_MASK,
859 			FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x6));
860 
861 	__mtk_tr_modify(phydev, 0x1, 0xf, 0x12,
862 			VGA_DECIMATION_RATE_MASK,
863 			FIELD_PREP(VGA_DECIMATION_RATE_MASK, 0x1));
864 
865 	/* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
866 	 * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
867 	 */
868 	__mtk_tr_modify(phydev, 0x1, 0xf, 0x1,
869 			MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK |
870 			MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK,
871 			FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x3) |
872 			FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x2) |
873 			FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x3) |
874 			FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x2));
875 
876 	/* VcoSlicerThreshBitsHigh */
877 	__mtk_tr_modify(phydev, 0x1, 0xd, 0x20,
878 			VCO_SLICER_THRESH_HIGH_MASK,
879 			FIELD_PREP(VCO_SLICER_THRESH_HIGH_MASK, 0x555555));
880 	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
881 
882 	/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
883 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
884 		       MTK_PHY_TR_OPEN_LOOP_EN_MASK |
885 		       MTK_PHY_LPF_X_AVERAGE_MASK,
886 		       BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
887 
888 	/* rg_tr_lpf_cnt_val = 512 */
889 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
890 
891 	/* IIR2 related */
892 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
893 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
894 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
895 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
896 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
897 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
898 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
899 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
900 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
901 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
902 
903 	/* FFE peaking */
904 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
905 		       MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8);
906 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
907 		       MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e);
908 
909 	/* Disable LDO pump */
910 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
911 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
912 	/* Adjust LDO output voltage */
913 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
914 }
915 
mt7988_phy_finetune(struct phy_device * phydev)916 static void mt7988_phy_finetune(struct phy_device *phydev)
917 {
918 	u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
919 			0x020d, 0x0206, 0x0384, 0x03d0,
920 			0x03c6, 0x030a, 0x0011, 0x0005 };
921 	int i;
922 
923 	/* Set default MLT3 shaper first */
924 	for (i = 0; i < 12; i++)
925 		phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
926 
927 	/* TCT finetune */
928 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
929 
930 	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
931 	__mtk_tr_modify(phydev, 0x1, 0xf, 0x20,
932 			RESET_SYNC_OFFSET_MASK,
933 			FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x5));
934 
935 	/* VgaDecRate is 1 at default on mt7988 */
936 
937 	__mtk_tr_modify(phydev, 0x1, 0xf, 0x1,
938 			MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK |
939 			MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK,
940 			FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x6) |
941 			FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x7) |
942 			FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x6) |
943 			FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x7));
944 
945 	__mtk_tr_modify(phydev, 0x0, 0xf, 0x3c,
946 			REMOTE_ACK_COUNT_LIMIT_CTRL_MASK,
947 			FIELD_PREP(REMOTE_ACK_COUNT_LIMIT_CTRL_MASK, 0x1));
948 	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
949 
950 	/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
951 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
952 		       MTK_PHY_TR_OPEN_LOOP_EN_MASK |
953 		       MTK_PHY_LPF_X_AVERAGE_MASK,
954 		       BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
955 
956 	/* rg_tr_lpf_cnt_val = 1023 */
957 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff);
958 }
959 
mt798x_phy_eee(struct phy_device * phydev)960 static void mt798x_phy_eee(struct phy_device *phydev)
961 {
962 	phy_modify_mmd(phydev, MDIO_MMD_VEND1,
963 		       MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120,
964 		       MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK |
965 		       MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK,
966 		       FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) |
967 		       FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14));
968 
969 	phy_modify_mmd(phydev, MDIO_MMD_VEND1,
970 		       MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
971 		       MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
972 		       FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
973 				  0xff));
974 
975 	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
976 			   MTK_PHY_RG_TESTMUX_ADC_CTRL,
977 			   MTK_PHY_RG_TXEN_DIG_MASK);
978 
979 	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
980 			 MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY);
981 
982 	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
983 			   MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN);
984 
985 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238,
986 		       MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK |
987 		       MTK_PHY_LPI_SLV_SEND_TX_EN,
988 		       FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
989 
990 	/* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */
991 	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
992 			   MTK_PHY_LPI_TXPCS_LOC_RCV);
993 
994 	/* This also fixes some IoT issues, such as CH340 */
995 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
996 		       MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
997 		       FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
998 		       FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13));
999 
1000 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1,
1001 		       MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
1002 		       FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
1003 				  0x33) |
1004 		       MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY |
1005 		       MTK_PHY_LPI_VCO_EEE_STG0_EN);
1006 
1007 	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323,
1008 			 MTK_PHY_EEE_WAKE_MAS_INT_DC |
1009 			 MTK_PHY_EEE_WAKE_SLV_INT_DC);
1010 
1011 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324,
1012 		       MTK_PHY_SMI_DETCNT_MAX_MASK,
1013 		       FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) |
1014 		       MTK_PHY_SMI_DET_MAX_EN);
1015 
1016 	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326,
1017 			 MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT |
1018 			 MTK_PHY_TREC_UPDATE_ENAB_CLR |
1019 			 MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF |
1020 			 MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
1021 
1022 	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
1023 	__mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x8,
1024 			  EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE);
1025 
1026 	__mtk_tr_modify(phydev, 0x2, 0xd, 0xd,
1027 			EEE1000_STAGE2_TR_KF_MASK,
1028 			FIELD_PREP(EEE1000_STAGE2_TR_KF_MASK, 0x2));
1029 
1030 	__mtk_tr_modify(phydev, 0x2, 0xd, 0xf,
1031 			SLAVE_WAKETR_TIMER_MASK | SLAVE_REMTX_TIMER_MASK,
1032 			FIELD_PREP(SLAVE_WAKETR_TIMER_MASK, 0x6) |
1033 			FIELD_PREP(SLAVE_REMTX_TIMER_MASK, 0x14));
1034 
1035 	__mtk_tr_modify(phydev, 0x2, 0xd, 0x10,
1036 			SLAVE_WAKEINT_TIMER_MASK,
1037 			FIELD_PREP(SLAVE_WAKEINT_TIMER_MASK, 0x8));
1038 
1039 	__mtk_tr_modify(phydev, 0x2, 0xd, 0x14,
1040 			TR_FREEZE_TIMER2_MASK,
1041 			FIELD_PREP(TR_FREEZE_TIMER2_MASK, 0x24a));
1042 
1043 	__mtk_tr_modify(phydev, 0x2, 0xd, 0x1c,
1044 			EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK,
1045 			FIELD_PREP(EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK,
1046 				   0x10));
1047 
1048 	__mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x25,
1049 			  WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN);
1050 
1051 	__mtk_tr_modify(phydev, 0x1, 0xf, 0x0,
1052 			DFE_TAIL_EANBLE_VGA_TRHESH_1000,
1053 			FIELD_PREP(DFE_TAIL_EANBLE_VGA_TRHESH_1000, 0x1b));
1054 	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
1055 
1056 	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
1057 	__phy_modify(phydev, MTK_PHY_LPI_REG_14,
1058 		     MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
1059 		     FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c));
1060 
1061 	__phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
1062 		     FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc));
1063 	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
1064 
1065 	phy_modify_mmd(phydev, MDIO_MMD_VEND1,
1066 		       MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
1067 		       MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
1068 		       FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
1069 				  0xff));
1070 }
1071 
cal_sw(struct phy_device * phydev,enum CAL_ITEM cal_item,u8 start_pair,u8 end_pair)1072 static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
1073 		  u8 start_pair, u8 end_pair)
1074 {
1075 	u8 pair_n;
1076 	int ret;
1077 
1078 	for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
1079 		/* TX_OFFSET & TX_AMP have no SW calibration. */
1080 		switch (cal_item) {
1081 		case TX_VCM:
1082 			ret = tx_vcm_cal_sw(phydev, pair_n);
1083 			break;
1084 		default:
1085 			return -EINVAL;
1086 		}
1087 		if (ret)
1088 			return ret;
1089 	}
1090 	return 0;
1091 }
1092 
cal_efuse(struct phy_device * phydev,enum CAL_ITEM cal_item,u8 start_pair,u8 end_pair,u32 * buf)1093 static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item,
1094 		     u8 start_pair, u8 end_pair, u32 *buf)
1095 {
1096 	u8 pair_n;
1097 	int ret;
1098 
1099 	for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
1100 		/* TX_VCM has no efuse calibration. */
1101 		switch (cal_item) {
1102 		case REXT:
1103 			ret = rext_cal_efuse(phydev, buf);
1104 			break;
1105 		case TX_OFFSET:
1106 			ret = tx_offset_cal_efuse(phydev, buf);
1107 			break;
1108 		case TX_AMP:
1109 			ret = tx_amp_cal_efuse(phydev, buf);
1110 			break;
1111 		case TX_R50:
1112 			ret = tx_r50_cal_efuse(phydev, buf, pair_n);
1113 			break;
1114 		default:
1115 			return -EINVAL;
1116 		}
1117 		if (ret)
1118 			return ret;
1119 	}
1120 
1121 	return 0;
1122 }
1123 
start_cal(struct phy_device * phydev,enum CAL_ITEM cal_item,enum CAL_MODE cal_mode,u8 start_pair,u8 end_pair,u32 * buf)1124 static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
1125 		     enum CAL_MODE cal_mode, u8 start_pair,
1126 		     u8 end_pair, u32 *buf)
1127 {
1128 	int ret;
1129 
1130 	switch (cal_mode) {
1131 	case EFUSE_M:
1132 		ret = cal_efuse(phydev, cal_item, start_pair,
1133 				end_pair, buf);
1134 		break;
1135 	case SW_M:
1136 		ret = cal_sw(phydev, cal_item, start_pair, end_pair);
1137 		break;
1138 	default:
1139 		return -EINVAL;
1140 	}
1141 
1142 	if (ret) {
1143 		phydev_err(phydev, "cal %d failed\n", cal_item);
1144 		return -EIO;
1145 	}
1146 
1147 	return 0;
1148 }
1149 
mt798x_phy_calibration(struct phy_device * phydev)1150 static int mt798x_phy_calibration(struct phy_device *phydev)
1151 {
1152 	struct nvmem_cell *cell;
1153 	int ret = 0;
1154 	size_t len;
1155 	u32 *buf;
1156 
1157 	cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
1158 	if (IS_ERR(cell)) {
1159 		if (PTR_ERR(cell) == -EPROBE_DEFER)
1160 			return PTR_ERR(cell);
1161 		return 0;
1162 	}
1163 
1164 	buf = (u32 *)nvmem_cell_read(cell, &len);
1165 	if (IS_ERR(buf))
1166 		return PTR_ERR(buf);
1167 	nvmem_cell_put(cell);
1168 
1169 	if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) {
1170 		phydev_err(phydev, "invalid efuse data\n");
1171 		ret = -EINVAL;
1172 		goto out;
1173 	}
1174 
1175 	ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf);
1176 	if (ret)
1177 		goto out;
1178 	ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf);
1179 	if (ret)
1180 		goto out;
1181 	ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf);
1182 	if (ret)
1183 		goto out;
1184 	ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf);
1185 	if (ret)
1186 		goto out;
1187 	ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf);
1188 	if (ret)
1189 		goto out;
1190 
1191 out:
1192 	kfree(buf);
1193 	return ret;
1194 }
1195 
mt798x_phy_config_init(struct phy_device * phydev)1196 static int mt798x_phy_config_init(struct phy_device *phydev)
1197 {
1198 	switch (phydev->drv->phy_id) {
1199 	case MTK_GPHY_ID_MT7981:
1200 		mt7981_phy_finetune(phydev);
1201 		break;
1202 	case MTK_GPHY_ID_MT7988:
1203 		mt7988_phy_finetune(phydev);
1204 		break;
1205 	}
1206 
1207 	mt798x_phy_common_finetune(phydev);
1208 	mt798x_phy_eee(phydev);
1209 
1210 	return mt798x_phy_calibration(phydev);
1211 }
1212 
mt798x_phy_led_blink_set(struct phy_device * phydev,u8 index,unsigned long * delay_on,unsigned long * delay_off)1213 static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index,
1214 				    unsigned long *delay_on,
1215 				    unsigned long *delay_off)
1216 {
1217 	bool blinking = false;
1218 	int err;
1219 
1220 	err = mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking);
1221 	if (err < 0)
1222 		return err;
1223 
1224 	err = mtk_phy_hw_led_blink_set(phydev, index, blinking);
1225 	if (err)
1226 		return err;
1227 
1228 	return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK,
1229 				     false);
1230 }
1231 
mt798x_phy_led_brightness_set(struct phy_device * phydev,u8 index,enum led_brightness value)1232 static int mt798x_phy_led_brightness_set(struct phy_device *phydev,
1233 					 u8 index, enum led_brightness value)
1234 {
1235 	int err;
1236 
1237 	err = mtk_phy_hw_led_blink_set(phydev, index, false);
1238 	if (err)
1239 		return err;
1240 
1241 	return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK,
1242 				     (value != LED_OFF));
1243 }
1244 
1245 static const unsigned long supported_triggers =
1246 	BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
1247 	BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
1248 	BIT(TRIGGER_NETDEV_LINK)        |
1249 	BIT(TRIGGER_NETDEV_LINK_10)     |
1250 	BIT(TRIGGER_NETDEV_LINK_100)    |
1251 	BIT(TRIGGER_NETDEV_LINK_1000)   |
1252 	BIT(TRIGGER_NETDEV_RX)          |
1253 	BIT(TRIGGER_NETDEV_TX);
1254 
mt798x_phy_led_hw_is_supported(struct phy_device * phydev,u8 index,unsigned long rules)1255 static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
1256 					  unsigned long rules)
1257 {
1258 	return mtk_phy_led_hw_is_supported(phydev, index, rules,
1259 					   supported_triggers);
1260 }
1261 
mt798x_phy_led_hw_control_get(struct phy_device * phydev,u8 index,unsigned long * rules)1262 static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
1263 					 unsigned long *rules)
1264 {
1265 	return mtk_phy_led_hw_ctrl_get(phydev, index, rules,
1266 				       MTK_GPHY_LED_ON_SET,
1267 				       MTK_GPHY_LED_RX_BLINK_SET,
1268 				       MTK_GPHY_LED_TX_BLINK_SET);
1269 };
1270 
mt798x_phy_led_hw_control_set(struct phy_device * phydev,u8 index,unsigned long rules)1271 static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
1272 					 unsigned long rules)
1273 {
1274 	return mtk_phy_led_hw_ctrl_set(phydev, index, rules,
1275 				       MTK_GPHY_LED_ON_SET,
1276 				       MTK_GPHY_LED_RX_BLINK_SET,
1277 				       MTK_GPHY_LED_TX_BLINK_SET);
1278 };
1279 
mt7988_phy_led_get_polarity(struct phy_device * phydev,int led_num)1280 static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num)
1281 {
1282 	struct mtk_socphy_shared *priv = phy_package_get_priv(phydev);
1283 	u32 polarities;
1284 
1285 	if (led_num == 0)
1286 		polarities = ~(priv->boottrap);
1287 	else
1288 		polarities = MTK_PHY_LED1_DEFAULT_POLARITIES;
1289 
1290 	if (polarities & BIT(phydev->mdio.addr))
1291 		return true;
1292 
1293 	return false;
1294 }
1295 
mt7988_phy_fix_leds_polarities(struct phy_device * phydev)1296 static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev)
1297 {
1298 	struct pinctrl *pinctrl;
1299 	int index;
1300 
1301 	/* Setup LED polarity according to bootstrap use of LED pins */
1302 	for (index = 0; index < 2; ++index)
1303 		phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
1304 				MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
1305 			       MTK_PHY_LED_ON_POLARITY,
1306 			       mt7988_phy_led_get_polarity(phydev, index) ?
1307 				MTK_PHY_LED_ON_POLARITY : 0);
1308 
1309 	/* Only now setup pinctrl to avoid bogus blinking */
1310 	pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
1311 	if (IS_ERR(pinctrl))
1312 		dev_err(&phydev->mdio.bus->dev,
1313 			"Failed to setup PHY LED pinctrl\n");
1314 
1315 	return 0;
1316 }
1317 
mt7988_phy_probe_shared(struct phy_device * phydev)1318 static int mt7988_phy_probe_shared(struct phy_device *phydev)
1319 {
1320 	struct device_node *np = dev_of_node(&phydev->mdio.bus->dev);
1321 	struct mtk_socphy_shared *shared = phy_package_get_priv(phydev);
1322 	struct regmap *regmap;
1323 	u32 reg;
1324 	int ret;
1325 
1326 	/* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B,
1327 	 * LED_C and LED_D respectively. At the same time those pins are used to
1328 	 * bootstrap configuration of the reference clock source (LED_A),
1329 	 * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
1330 	 * In practice this is done using a LED and a resistor pulling the pin
1331 	 * either to GND or to VIO.
1332 	 * The detected value at boot time is accessible at run-time using the
1333 	 * TPBANK0 register located in the gpio base of the pinctrl, in order
1334 	 * to read it here it needs to be referenced by a phandle called
1335 	 * 'mediatek,pio' in the MDIO bus hosting the PHY.
1336 	 * The 4 bits in TPBANK0 are kept as package shared data and are used to
1337 	 * set LED polarity for each of the LED0.
1338 	 */
1339 	regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio");
1340 	if (IS_ERR(regmap))
1341 		return PTR_ERR(regmap);
1342 
1343 	ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, &reg);
1344 	if (ret)
1345 		return ret;
1346 
1347 	shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg);
1348 
1349 	return 0;
1350 }
1351 
mt7988_phy_probe(struct phy_device * phydev)1352 static int mt7988_phy_probe(struct phy_device *phydev)
1353 {
1354 	struct mtk_socphy_shared *shared;
1355 	struct mtk_socphy_priv *priv;
1356 	int err;
1357 
1358 	if (phydev->mdio.addr > 3)
1359 		return -EINVAL;
1360 
1361 	err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0,
1362 				    sizeof(struct mtk_socphy_shared));
1363 	if (err)
1364 		return err;
1365 
1366 	if (phy_package_probe_once(phydev)) {
1367 		err = mt7988_phy_probe_shared(phydev);
1368 		if (err)
1369 			return err;
1370 	}
1371 
1372 	shared = phy_package_get_priv(phydev);
1373 	priv = &shared->priv[phydev->mdio.addr];
1374 
1375 	phydev->priv = priv;
1376 
1377 	mtk_phy_leds_state_init(phydev);
1378 
1379 	err = mt7988_phy_fix_leds_polarities(phydev);
1380 	if (err)
1381 		return err;
1382 
1383 	/* Disable TX power saving at probing to:
1384 	 * 1. Meet common mode compliance test criteria
1385 	 * 2. Make sure that TX-VCM calibration works fine
1386 	 */
1387 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
1388 		       MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
1389 
1390 	return mt798x_phy_calibration(phydev);
1391 }
1392 
mt7981_phy_probe(struct phy_device * phydev)1393 static int mt7981_phy_probe(struct phy_device *phydev)
1394 {
1395 	struct mtk_socphy_priv *priv;
1396 
1397 	priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv),
1398 			    GFP_KERNEL);
1399 	if (!priv)
1400 		return -ENOMEM;
1401 
1402 	phydev->priv = priv;
1403 
1404 	mtk_phy_leds_state_init(phydev);
1405 
1406 	return mt798x_phy_calibration(phydev);
1407 }
1408 
1409 static struct phy_driver mtk_socphy_driver[] = {
1410 	{
1411 		PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
1412 		.name		= "MediaTek MT7981 PHY",
1413 		.config_init	= mt798x_phy_config_init,
1414 		.config_intr	= genphy_no_config_intr,
1415 		.handle_interrupt = genphy_handle_interrupt_no_ack,
1416 		.probe		= mt7981_phy_probe,
1417 		.suspend	= genphy_suspend,
1418 		.resume		= genphy_resume,
1419 		.read_page	= mtk_phy_read_page,
1420 		.write_page	= mtk_phy_write_page,
1421 		.led_blink_set	= mt798x_phy_led_blink_set,
1422 		.led_brightness_set = mt798x_phy_led_brightness_set,
1423 		.led_hw_is_supported = mt798x_phy_led_hw_is_supported,
1424 		.led_hw_control_set = mt798x_phy_led_hw_control_set,
1425 		.led_hw_control_get = mt798x_phy_led_hw_control_get,
1426 	},
1427 	{
1428 		PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988),
1429 		.name		= "MediaTek MT7988 PHY",
1430 		.config_init	= mt798x_phy_config_init,
1431 		.config_intr	= genphy_no_config_intr,
1432 		.handle_interrupt = genphy_handle_interrupt_no_ack,
1433 		.probe		= mt7988_phy_probe,
1434 		.suspend	= genphy_suspend,
1435 		.resume		= genphy_resume,
1436 		.read_page	= mtk_phy_read_page,
1437 		.write_page	= mtk_phy_write_page,
1438 		.led_blink_set	= mt798x_phy_led_blink_set,
1439 		.led_brightness_set = mt798x_phy_led_brightness_set,
1440 		.led_hw_is_supported = mt798x_phy_led_hw_is_supported,
1441 		.led_hw_control_set = mt798x_phy_led_hw_control_set,
1442 		.led_hw_control_get = mt798x_phy_led_hw_control_get,
1443 	},
1444 };
1445 
1446 module_phy_driver(mtk_socphy_driver);
1447 
1448 static const struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
1449 	{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) },
1450 	{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) },
1451 	{ }
1452 };
1453 
1454 MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver");
1455 MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
1456 MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
1457 MODULE_LICENSE("GPL");
1458 
1459 MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl);
1460