1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright Altera Corporation (C) 2014. All rights reserved.
3 *
4 * Adopted from dwmac-sti.c
5 */
6
7 #include <linux/mfd/altera-sysmgr.h>
8 #include <linux/of.h>
9 #include <linux/of_address.h>
10 #include <linux/of_net.h>
11 #include <linux/phy.h>
12 #include <linux/regmap.h>
13 #include <linux/mdio/mdio-regmap.h>
14 #include <linux/pcs-lynx.h>
15 #include <linux/reset.h>
16 #include <linux/stmmac.h>
17
18 #include "stmmac.h"
19 #include "stmmac_platform.h"
20
21 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
22 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
23 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
24 #define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
25 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
26 #define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010
27 #define SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000100
28
29 #define SYSMGR_FPGAGRP_MODULE_REG 0x00000028
30 #define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004
31 #define SYSMGR_FPGAINTF_EMAC_REG 0x00000070
32 #define SYSMGR_FPGAINTF_EMAC_BIT 0x1
33
34 #define EMAC_SPLITTER_CTRL_REG 0x0
35 #define EMAC_SPLITTER_CTRL_SPEED_MASK 0x3
36 #define EMAC_SPLITTER_CTRL_SPEED_10 0x2
37 #define EMAC_SPLITTER_CTRL_SPEED_100 0x3
38 #define EMAC_SPLITTER_CTRL_SPEED_1000 0x0
39
40 #define SGMII_ADAPTER_CTRL_REG 0x00
41 #define SGMII_ADAPTER_ENABLE 0x0000
42 #define SGMII_ADAPTER_DISABLE 0x0001
43
44 struct socfpga_dwmac;
45 struct socfpga_dwmac_ops {
46 int (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv);
47 };
48
49 struct socfpga_dwmac {
50 u32 reg_offset;
51 u32 reg_shift;
52 struct device *dev;
53 struct plat_stmmacenet_data *plat_dat;
54 struct regmap *sys_mgr_base_addr;
55 struct reset_control *stmmac_rst;
56 struct reset_control *stmmac_ocp_rst;
57 void __iomem *splitter_base;
58 void __iomem *tse_pcs_base;
59 void __iomem *sgmii_adapter_base;
60 bool f2h_ptp_ref_clk;
61 const struct socfpga_dwmac_ops *ops;
62 };
63
socfpga_dwmac_fix_mac_speed(void * bsp_priv,int speed,unsigned int mode)64 static void socfpga_dwmac_fix_mac_speed(void *bsp_priv, int speed,
65 unsigned int mode)
66 {
67 struct socfpga_dwmac *dwmac = (struct socfpga_dwmac *)bsp_priv;
68 struct stmmac_priv *priv = netdev_priv(dev_get_drvdata(dwmac->dev));
69 void __iomem *splitter_base = dwmac->splitter_base;
70 void __iomem *sgmii_adapter_base = dwmac->sgmii_adapter_base;
71 u32 val;
72
73 if (sgmii_adapter_base)
74 writew(SGMII_ADAPTER_DISABLE,
75 sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
76
77 if (splitter_base) {
78 val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG);
79 val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK;
80
81 switch (speed) {
82 case 1000:
83 val |= EMAC_SPLITTER_CTRL_SPEED_1000;
84 break;
85 case 100:
86 val |= EMAC_SPLITTER_CTRL_SPEED_100;
87 break;
88 case 10:
89 val |= EMAC_SPLITTER_CTRL_SPEED_10;
90 break;
91 default:
92 return;
93 }
94 writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG);
95 }
96
97 if ((priv->plat->phy_interface == PHY_INTERFACE_MODE_SGMII ||
98 priv->plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) &&
99 sgmii_adapter_base)
100 writew(SGMII_ADAPTER_ENABLE,
101 sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
102 }
103
socfpga_dwmac_parse_data(struct socfpga_dwmac * dwmac,struct device * dev)104 static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev)
105 {
106 struct device_node *np = dev->of_node;
107 struct regmap *sys_mgr_base_addr;
108 u32 reg_offset, reg_shift;
109 int ret, index;
110 struct device_node *np_splitter = NULL;
111 struct device_node *np_sgmii_adapter = NULL;
112 struct resource res_splitter;
113 struct resource res_tse_pcs;
114 struct resource res_sgmii_adapter;
115
116 sys_mgr_base_addr =
117 altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
118 if (IS_ERR(sys_mgr_base_addr)) {
119 dev_info(dev, "No sysmgr-syscon node found\n");
120 return PTR_ERR(sys_mgr_base_addr);
121 }
122
123 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset);
124 if (ret) {
125 dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n");
126 return -EINVAL;
127 }
128
129 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, ®_shift);
130 if (ret) {
131 dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n");
132 return -EINVAL;
133 }
134
135 dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk");
136
137 np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0);
138 if (np_splitter) {
139 ret = of_address_to_resource(np_splitter, 0, &res_splitter);
140 of_node_put(np_splitter);
141 if (ret) {
142 dev_info(dev, "Missing emac splitter address\n");
143 return -EINVAL;
144 }
145
146 dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter);
147 if (IS_ERR(dwmac->splitter_base)) {
148 dev_info(dev, "Failed to mapping emac splitter\n");
149 return PTR_ERR(dwmac->splitter_base);
150 }
151 }
152
153 np_sgmii_adapter = of_parse_phandle(np,
154 "altr,gmii-to-sgmii-converter", 0);
155 if (np_sgmii_adapter) {
156 index = of_property_match_string(np_sgmii_adapter, "reg-names",
157 "hps_emac_interface_splitter_avalon_slave");
158
159 if (index >= 0) {
160 if (of_address_to_resource(np_sgmii_adapter, index,
161 &res_splitter)) {
162 dev_err(dev,
163 "%s: ERROR: missing emac splitter address\n",
164 __func__);
165 ret = -EINVAL;
166 goto err_node_put;
167 }
168
169 dwmac->splitter_base =
170 devm_ioremap_resource(dev, &res_splitter);
171
172 if (IS_ERR(dwmac->splitter_base)) {
173 ret = PTR_ERR(dwmac->splitter_base);
174 goto err_node_put;
175 }
176 }
177
178 index = of_property_match_string(np_sgmii_adapter, "reg-names",
179 "gmii_to_sgmii_adapter_avalon_slave");
180
181 if (index >= 0) {
182 if (of_address_to_resource(np_sgmii_adapter, index,
183 &res_sgmii_adapter)) {
184 dev_err(dev,
185 "%s: ERROR: failed mapping adapter\n",
186 __func__);
187 ret = -EINVAL;
188 goto err_node_put;
189 }
190
191 dwmac->sgmii_adapter_base =
192 devm_ioremap_resource(dev, &res_sgmii_adapter);
193
194 if (IS_ERR(dwmac->sgmii_adapter_base)) {
195 ret = PTR_ERR(dwmac->sgmii_adapter_base);
196 goto err_node_put;
197 }
198 }
199
200 index = of_property_match_string(np_sgmii_adapter, "reg-names",
201 "eth_tse_control_port");
202
203 if (index >= 0) {
204 if (of_address_to_resource(np_sgmii_adapter, index,
205 &res_tse_pcs)) {
206 dev_err(dev,
207 "%s: ERROR: failed mapping tse control port\n",
208 __func__);
209 ret = -EINVAL;
210 goto err_node_put;
211 }
212
213 dwmac->tse_pcs_base =
214 devm_ioremap_resource(dev, &res_tse_pcs);
215
216 if (IS_ERR(dwmac->tse_pcs_base)) {
217 ret = PTR_ERR(dwmac->tse_pcs_base);
218 goto err_node_put;
219 }
220 }
221 }
222 dwmac->reg_offset = reg_offset;
223 dwmac->reg_shift = reg_shift;
224 dwmac->sys_mgr_base_addr = sys_mgr_base_addr;
225 dwmac->dev = dev;
226 of_node_put(np_sgmii_adapter);
227
228 return 0;
229
230 err_node_put:
231 of_node_put(np_sgmii_adapter);
232 return ret;
233 }
234
socfpga_get_plat_phymode(struct socfpga_dwmac * dwmac)235 static int socfpga_get_plat_phymode(struct socfpga_dwmac *dwmac)
236 {
237 return dwmac->plat_dat->mac_interface;
238 }
239
socfpga_sgmii_config(struct socfpga_dwmac * dwmac,bool enable)240 static void socfpga_sgmii_config(struct socfpga_dwmac *dwmac, bool enable)
241 {
242 u16 val = enable ? SGMII_ADAPTER_ENABLE : SGMII_ADAPTER_DISABLE;
243
244 writew(val, dwmac->sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
245 }
246
socfpga_set_phy_mode_common(int phymode,u32 * val)247 static int socfpga_set_phy_mode_common(int phymode, u32 *val)
248 {
249 switch (phymode) {
250 case PHY_INTERFACE_MODE_RGMII:
251 case PHY_INTERFACE_MODE_RGMII_ID:
252 case PHY_INTERFACE_MODE_RGMII_RXID:
253 case PHY_INTERFACE_MODE_RGMII_TXID:
254 *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
255 break;
256 case PHY_INTERFACE_MODE_MII:
257 case PHY_INTERFACE_MODE_GMII:
258 case PHY_INTERFACE_MODE_SGMII:
259 case PHY_INTERFACE_MODE_1000BASEX:
260 *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
261 break;
262 case PHY_INTERFACE_MODE_RMII:
263 *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
264 break;
265 default:
266 return -EINVAL;
267 }
268 return 0;
269 }
270
socfpga_gen5_set_phy_mode(struct socfpga_dwmac * dwmac)271 static int socfpga_gen5_set_phy_mode(struct socfpga_dwmac *dwmac)
272 {
273 struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
274 int phymode = socfpga_get_plat_phymode(dwmac);
275 u32 reg_offset = dwmac->reg_offset;
276 u32 reg_shift = dwmac->reg_shift;
277 u32 ctrl, val, module;
278
279 if (socfpga_set_phy_mode_common(phymode, &val)) {
280 dev_err(dwmac->dev, "bad phy mode %d\n", phymode);
281 return -EINVAL;
282 }
283
284 /* Overwrite val to GMII if splitter core is enabled. The phymode here
285 * is the actual phy mode on phy hardware, but phy interface from
286 * EMAC core is GMII.
287 */
288 if (dwmac->splitter_base)
289 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
290
291 /* Assert reset to the enet controller before changing the phy mode */
292 reset_control_assert(dwmac->stmmac_ocp_rst);
293 reset_control_assert(dwmac->stmmac_rst);
294
295 regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
296 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
297 ctrl |= val << reg_shift;
298
299 if (dwmac->f2h_ptp_ref_clk ||
300 phymode == PHY_INTERFACE_MODE_MII ||
301 phymode == PHY_INTERFACE_MODE_GMII ||
302 phymode == PHY_INTERFACE_MODE_SGMII) {
303 regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
304 &module);
305 module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2));
306 regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
307 module);
308 }
309
310 if (dwmac->f2h_ptp_ref_clk)
311 ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
312 else
313 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK <<
314 (reg_shift / 2));
315
316 regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
317
318 /* Deassert reset for the phy configuration to be sampled by
319 * the enet controller, and operation to start in requested mode
320 */
321 reset_control_deassert(dwmac->stmmac_ocp_rst);
322 reset_control_deassert(dwmac->stmmac_rst);
323 if (phymode == PHY_INTERFACE_MODE_SGMII)
324 socfpga_sgmii_config(dwmac, true);
325
326 return 0;
327 }
328
socfpga_gen10_set_phy_mode(struct socfpga_dwmac * dwmac)329 static int socfpga_gen10_set_phy_mode(struct socfpga_dwmac *dwmac)
330 {
331 struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
332 int phymode = socfpga_get_plat_phymode(dwmac);
333 u32 reg_offset = dwmac->reg_offset;
334 u32 reg_shift = dwmac->reg_shift;
335 u32 ctrl, val, module;
336
337 if (socfpga_set_phy_mode_common(phymode, &val))
338 return -EINVAL;
339
340 /* Overwrite val to GMII if splitter core is enabled. The phymode here
341 * is the actual phy mode on phy hardware, but phy interface from
342 * EMAC core is GMII.
343 */
344 if (dwmac->splitter_base)
345 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
346
347 /* Assert reset to the enet controller before changing the phy mode */
348 reset_control_assert(dwmac->stmmac_ocp_rst);
349 reset_control_assert(dwmac->stmmac_rst);
350
351 regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
352 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK);
353 ctrl |= val;
354
355 if (dwmac->f2h_ptp_ref_clk ||
356 phymode == PHY_INTERFACE_MODE_MII ||
357 phymode == PHY_INTERFACE_MODE_GMII ||
358 phymode == PHY_INTERFACE_MODE_SGMII) {
359 ctrl |= SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK;
360 regmap_read(sys_mgr_base_addr, SYSMGR_FPGAINTF_EMAC_REG,
361 &module);
362 module |= (SYSMGR_FPGAINTF_EMAC_BIT << reg_shift);
363 regmap_write(sys_mgr_base_addr, SYSMGR_FPGAINTF_EMAC_REG,
364 module);
365 } else {
366 ctrl &= ~SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK;
367 }
368
369 regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
370
371 /* Deassert reset for the phy configuration to be sampled by
372 * the enet controller, and operation to start in requested mode
373 */
374 reset_control_deassert(dwmac->stmmac_ocp_rst);
375 reset_control_deassert(dwmac->stmmac_rst);
376 if (phymode == PHY_INTERFACE_MODE_SGMII)
377 socfpga_sgmii_config(dwmac, true);
378 return 0;
379 }
380
socfpga_dwmac_pcs_init(struct stmmac_priv * priv)381 static int socfpga_dwmac_pcs_init(struct stmmac_priv *priv)
382 {
383 struct socfpga_dwmac *dwmac = priv->plat->bsp_priv;
384 struct regmap_config pcs_regmap_cfg = {
385 .reg_bits = 16,
386 .val_bits = 16,
387 .reg_shift = REGMAP_UPSHIFT(1),
388 };
389 struct mdio_regmap_config mrc;
390 struct regmap *pcs_regmap;
391 struct phylink_pcs *pcs;
392 struct mii_bus *pcs_bus;
393
394 if (!dwmac->tse_pcs_base)
395 return 0;
396
397 pcs_regmap = devm_regmap_init_mmio(priv->device, dwmac->tse_pcs_base,
398 &pcs_regmap_cfg);
399 if (IS_ERR(pcs_regmap))
400 return PTR_ERR(pcs_regmap);
401
402 memset(&mrc, 0, sizeof(mrc));
403 mrc.regmap = pcs_regmap;
404 mrc.parent = priv->device;
405 mrc.valid_addr = 0x0;
406 mrc.autoscan = false;
407
408 /* Can't use ndev->name here because it will not have been initialised,
409 * and in any case, the user can rename network interfaces at runtime.
410 */
411 snprintf(mrc.name, MII_BUS_ID_SIZE, "%s-pcs-mii",
412 dev_name(priv->device));
413 pcs_bus = devm_mdio_regmap_register(priv->device, &mrc);
414 if (IS_ERR(pcs_bus))
415 return PTR_ERR(pcs_bus);
416
417 pcs = lynx_pcs_create_mdiodev(pcs_bus, 0);
418 if (IS_ERR(pcs))
419 return PTR_ERR(pcs);
420
421 priv->hw->phylink_pcs = pcs;
422 return 0;
423 }
424
socfpga_dwmac_pcs_exit(struct stmmac_priv * priv)425 static void socfpga_dwmac_pcs_exit(struct stmmac_priv *priv)
426 {
427 if (priv->hw->phylink_pcs)
428 lynx_pcs_destroy(priv->hw->phylink_pcs);
429 }
430
socfpga_dwmac_select_pcs(struct stmmac_priv * priv,phy_interface_t interface)431 static struct phylink_pcs *socfpga_dwmac_select_pcs(struct stmmac_priv *priv,
432 phy_interface_t interface)
433 {
434 return priv->hw->phylink_pcs;
435 }
436
socfpga_dwmac_init(struct platform_device * pdev,void * bsp_priv)437 static int socfpga_dwmac_init(struct platform_device *pdev, void *bsp_priv)
438 {
439 struct socfpga_dwmac *dwmac = bsp_priv;
440
441 return dwmac->ops->set_phy_mode(dwmac);
442 }
443
socfpga_dwmac_probe(struct platform_device * pdev)444 static int socfpga_dwmac_probe(struct platform_device *pdev)
445 {
446 struct plat_stmmacenet_data *plat_dat;
447 struct stmmac_resources stmmac_res;
448 struct device *dev = &pdev->dev;
449 int ret;
450 struct socfpga_dwmac *dwmac;
451 const struct socfpga_dwmac_ops *ops;
452
453 ops = device_get_match_data(&pdev->dev);
454 if (!ops) {
455 dev_err(&pdev->dev, "no of match data provided\n");
456 return -EINVAL;
457 }
458
459 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
460 if (ret)
461 return ret;
462
463 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
464 if (IS_ERR(plat_dat))
465 return PTR_ERR(plat_dat);
466
467 dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL);
468 if (!dwmac)
469 return -ENOMEM;
470
471 dwmac->stmmac_ocp_rst = devm_reset_control_get_optional(dev, "stmmaceth-ocp");
472 if (IS_ERR(dwmac->stmmac_ocp_rst)) {
473 ret = PTR_ERR(dwmac->stmmac_ocp_rst);
474 dev_err(dev, "error getting reset control of ocp %d\n", ret);
475 return ret;
476 }
477
478 reset_control_deassert(dwmac->stmmac_ocp_rst);
479
480 ret = socfpga_dwmac_parse_data(dwmac, dev);
481 if (ret) {
482 dev_err(dev, "Unable to parse OF data\n");
483 return ret;
484 }
485
486 /* The socfpga driver needs to control the stmmac reset to set the phy
487 * mode. Create a copy of the core reset handle so it can be used by
488 * the driver later.
489 */
490 dwmac->stmmac_rst = plat_dat->stmmac_rst;
491 dwmac->ops = ops;
492 dwmac->plat_dat = plat_dat;
493
494 plat_dat->bsp_priv = dwmac;
495 plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;
496 plat_dat->init = socfpga_dwmac_init;
497 plat_dat->pcs_init = socfpga_dwmac_pcs_init;
498 plat_dat->pcs_exit = socfpga_dwmac_pcs_exit;
499 plat_dat->select_pcs = socfpga_dwmac_select_pcs;
500 plat_dat->has_gmac = true;
501
502 plat_dat->riwt_off = 1;
503
504 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
505 }
506
507 static const struct socfpga_dwmac_ops socfpga_gen5_ops = {
508 .set_phy_mode = socfpga_gen5_set_phy_mode,
509 };
510
511 static const struct socfpga_dwmac_ops socfpga_gen10_ops = {
512 .set_phy_mode = socfpga_gen10_set_phy_mode,
513 };
514
515 static const struct of_device_id socfpga_dwmac_match[] = {
516 { .compatible = "altr,socfpga-stmmac", .data = &socfpga_gen5_ops },
517 { .compatible = "altr,socfpga-stmmac-a10-s10", .data = &socfpga_gen10_ops },
518 { .compatible = "altr,socfpga-stmmac-agilex5", .data = &socfpga_gen10_ops },
519 { }
520 };
521 MODULE_DEVICE_TABLE(of, socfpga_dwmac_match);
522
523 static struct platform_driver socfpga_dwmac_driver = {
524 .probe = socfpga_dwmac_probe,
525 .driver = {
526 .name = "socfpga-dwmac",
527 .pm = &stmmac_pltfr_pm_ops,
528 .of_match_table = socfpga_dwmac_match,
529 },
530 };
531 module_platform_driver(socfpga_dwmac_driver);
532
533 MODULE_DESCRIPTION("Altera SOC DWMAC Specific Glue layer");
534 MODULE_LICENSE("GPL v2");
535