1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * NXP i.MX8MQ SoC series MIPI-CSI2 receiver driver
4 *
5 * Copyright (C) 2021 Purism SPC
6 */
7
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/errno.h>
12 #include <linux/interconnect.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/of.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regmap.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/reset.h>
25 #include <linux/spinlock.h>
26
27 #include <media/v4l2-common.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-fwnode.h>
30 #include <media/v4l2-mc.h>
31 #include <media/v4l2-subdev.h>
32
33 #define MIPI_CSI2_DRIVER_NAME "imx8mq-mipi-csi2"
34 #define MIPI_CSI2_SUBDEV_NAME MIPI_CSI2_DRIVER_NAME
35
36 #define MIPI_CSI2_PAD_SINK 0
37 #define MIPI_CSI2_PAD_SOURCE 1
38 #define MIPI_CSI2_PADS_NUM 2
39
40 #define MIPI_CSI2_DEF_PIX_WIDTH 640
41 #define MIPI_CSI2_DEF_PIX_HEIGHT 480
42
43 /* Register map definition */
44
45 /* i.MX8MQ CSI-2 controller CSR */
46 #define CSI2RX_CFG_NUM_LANES 0x100
47 #define CSI2RX_CFG_DISABLE_DATA_LANES 0x104
48 #define CSI2RX_BIT_ERR 0x108
49 #define CSI2RX_IRQ_STATUS 0x10c
50 #define CSI2RX_IRQ_MASK 0x110
51 #define CSI2RX_IRQ_MASK_ALL 0x1ff
52 #define CSI2RX_IRQ_MASK_ULPS_STATUS_CHANGE 0x8
53 #define CSI2RX_ULPS_STATUS 0x114
54 #define CSI2RX_PPI_ERRSOT_HS 0x118
55 #define CSI2RX_PPI_ERRSOTSYNC_HS 0x11c
56 #define CSI2RX_PPI_ERRESC 0x120
57 #define CSI2RX_PPI_ERRSYNCESC 0x124
58 #define CSI2RX_PPI_ERRCONTROL 0x128
59 #define CSI2RX_CFG_DISABLE_PAYLOAD_0 0x12c
60 #define CSI2RX_CFG_VID_VC_IGNORE 0x180
61 #define CSI2RX_CFG_VID_VC 0x184
62 #define CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL 0x188
63 #define CSI2RX_CFG_DISABLE_PAYLOAD_1 0x130
64
65 enum {
66 ST_POWERED = 1,
67 ST_STREAMING = 2,
68 ST_SUSPENDED = 4,
69 };
70
71 enum imx8mq_mipi_csi_clk {
72 CSI2_CLK_CORE,
73 CSI2_CLK_ESC,
74 CSI2_CLK_UI,
75 CSI2_NUM_CLKS,
76 };
77
78 static const char * const imx8mq_mipi_csi_clk_id[CSI2_NUM_CLKS] = {
79 [CSI2_CLK_CORE] = "core",
80 [CSI2_CLK_ESC] = "esc",
81 [CSI2_CLK_UI] = "ui",
82 };
83
84 #define CSI2_NUM_CLKS ARRAY_SIZE(imx8mq_mipi_csi_clk_id)
85
86 #define GPR_CSI2_1_RX_ENABLE BIT(13)
87 #define GPR_CSI2_1_VID_INTFC_ENB BIT(12)
88 #define GPR_CSI2_1_HSEL BIT(10)
89 #define GPR_CSI2_1_CONT_CLK_MODE BIT(8)
90 #define GPR_CSI2_1_S_PRG_RXHS_SETTLE(x) (((x) & 0x3f) << 2)
91
92 /*
93 * The send level configures the number of entries that must accumulate in
94 * the Pixel FIFO before the data will be transferred to the video output.
95 * The exact value needed for this configuration is dependent on the rate at
96 * which the sensor transfers data to the CSI-2 Controller and the user
97 * video clock.
98 *
99 * The calculation is the classical rate-in rate-out type of problem: If the
100 * video bandwidth is 10% faster than the incoming mipi data and the video
101 * line length is 500 pixels, then the fifo should be allowed to fill
102 * 10% of the line length or 50 pixels. If the gap data is ok, then the level
103 * can be set to 16 and ignored.
104 */
105 #define CSI2RX_SEND_LEVEL 64
106
107 struct csi_state {
108 struct device *dev;
109 void __iomem *regs;
110 struct clk_bulk_data clks[CSI2_NUM_CLKS];
111 struct reset_control *rst;
112 struct regulator *mipi_phy_regulator;
113
114 struct v4l2_subdev sd;
115 struct media_pad pads[MIPI_CSI2_PADS_NUM];
116 struct v4l2_async_notifier notifier;
117 struct v4l2_subdev *src_sd;
118
119 struct v4l2_mbus_config_mipi_csi2 bus;
120
121 struct mutex lock; /* Protect state */
122 u32 state;
123
124 struct regmap *phy_gpr;
125 u8 phy_gpr_reg;
126
127 struct icc_path *icc_path;
128 s32 icc_path_bw;
129 };
130
131 /* -----------------------------------------------------------------------------
132 * Format helpers
133 */
134
135 struct csi2_pix_format {
136 u32 code;
137 u8 width;
138 };
139
140 static const struct csi2_pix_format imx8mq_mipi_csi_formats[] = {
141 /* RAW (Bayer and greyscale) formats. */
142 {
143 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
144 .width = 8,
145 }, {
146 .code = MEDIA_BUS_FMT_SGBRG8_1X8,
147 .width = 8,
148 }, {
149 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
150 .width = 8,
151 }, {
152 .code = MEDIA_BUS_FMT_SRGGB8_1X8,
153 .width = 8,
154 }, {
155 .code = MEDIA_BUS_FMT_Y8_1X8,
156 .width = 8,
157 }, {
158 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
159 .width = 10,
160 }, {
161 .code = MEDIA_BUS_FMT_SGBRG10_1X10,
162 .width = 10,
163 }, {
164 .code = MEDIA_BUS_FMT_SGRBG10_1X10,
165 .width = 10,
166 }, {
167 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
168 .width = 10,
169 }, {
170 .code = MEDIA_BUS_FMT_Y10_1X10,
171 .width = 10,
172 }, {
173 .code = MEDIA_BUS_FMT_SBGGR12_1X12,
174 .width = 12,
175 }, {
176 .code = MEDIA_BUS_FMT_SGBRG12_1X12,
177 .width = 12,
178 }, {
179 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
180 .width = 12,
181 }, {
182 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
183 .width = 12,
184 }, {
185 .code = MEDIA_BUS_FMT_Y12_1X12,
186 .width = 12,
187 }, {
188 .code = MEDIA_BUS_FMT_SBGGR14_1X14,
189 .width = 14,
190 }, {
191 .code = MEDIA_BUS_FMT_SGBRG14_1X14,
192 .width = 14,
193 }, {
194 .code = MEDIA_BUS_FMT_SGRBG14_1X14,
195 .width = 14,
196 }, {
197 .code = MEDIA_BUS_FMT_SRGGB14_1X14,
198 .width = 14,
199 },
200 /* YUV formats */
201 {
202 .code = MEDIA_BUS_FMT_YUYV8_1X16,
203 .width = 16,
204 }, {
205 .code = MEDIA_BUS_FMT_UYVY8_1X16,
206 .width = 16,
207 }
208 };
209
find_csi2_format(u32 code)210 static const struct csi2_pix_format *find_csi2_format(u32 code)
211 {
212 unsigned int i;
213
214 for (i = 0; i < ARRAY_SIZE(imx8mq_mipi_csi_formats); i++)
215 if (code == imx8mq_mipi_csi_formats[i].code)
216 return &imx8mq_mipi_csi_formats[i];
217 return NULL;
218 }
219
220 /* -----------------------------------------------------------------------------
221 * Hardware configuration
222 */
223
imx8mq_mipi_csi_write(struct csi_state * state,u32 reg,u32 val)224 static inline void imx8mq_mipi_csi_write(struct csi_state *state, u32 reg, u32 val)
225 {
226 writel(val, state->regs + reg);
227 }
228
imx8mq_mipi_csi_sw_reset(struct csi_state * state)229 static int imx8mq_mipi_csi_sw_reset(struct csi_state *state)
230 {
231 int ret;
232
233 /*
234 * these are most likely self-clearing reset bits. to make it
235 * more clear, the reset-imx7 driver should implement the
236 * .reset() operation.
237 */
238 ret = reset_control_assert(state->rst);
239 if (ret < 0) {
240 dev_err(state->dev, "Failed to assert resets: %d\n", ret);
241 return ret;
242 }
243
244 return 0;
245 }
246
imx8mq_mipi_csi_set_params(struct csi_state * state)247 static void imx8mq_mipi_csi_set_params(struct csi_state *state)
248 {
249 int lanes = state->bus.num_data_lanes;
250
251 imx8mq_mipi_csi_write(state, CSI2RX_CFG_NUM_LANES, lanes - 1);
252 imx8mq_mipi_csi_write(state, CSI2RX_CFG_DISABLE_DATA_LANES,
253 (0xf << lanes) & 0xf);
254 imx8mq_mipi_csi_write(state, CSI2RX_IRQ_MASK, CSI2RX_IRQ_MASK_ALL);
255 /*
256 * 0x180 bit 0 controls the Virtual Channel behaviour: when set the
257 * interface ignores the Virtual Channel (VC) field in received packets;
258 * when cleared it causes the interface to only accept packets whose VC
259 * matches the value to which VC is set at offset 0x184.
260 */
261 imx8mq_mipi_csi_write(state, CSI2RX_CFG_VID_VC_IGNORE, 1);
262 imx8mq_mipi_csi_write(state, CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL,
263 CSI2RX_SEND_LEVEL);
264 }
265
imx8mq_mipi_csi_clk_enable(struct csi_state * state)266 static int imx8mq_mipi_csi_clk_enable(struct csi_state *state)
267 {
268 return clk_bulk_prepare_enable(CSI2_NUM_CLKS, state->clks);
269 }
270
imx8mq_mipi_csi_clk_disable(struct csi_state * state)271 static void imx8mq_mipi_csi_clk_disable(struct csi_state *state)
272 {
273 clk_bulk_disable_unprepare(CSI2_NUM_CLKS, state->clks);
274 }
275
imx8mq_mipi_csi_clk_get(struct csi_state * state)276 static int imx8mq_mipi_csi_clk_get(struct csi_state *state)
277 {
278 unsigned int i;
279
280 for (i = 0; i < CSI2_NUM_CLKS; i++)
281 state->clks[i].id = imx8mq_mipi_csi_clk_id[i];
282
283 return devm_clk_bulk_get(state->dev, CSI2_NUM_CLKS, state->clks);
284 }
285
imx8mq_mipi_csi_calc_hs_settle(struct csi_state * state,struct v4l2_subdev_state * sd_state,u32 * hs_settle)286 static int imx8mq_mipi_csi_calc_hs_settle(struct csi_state *state,
287 struct v4l2_subdev_state *sd_state,
288 u32 *hs_settle)
289 {
290 struct media_pad *src_pad;
291 s64 link_freq;
292 u32 lane_rate;
293 unsigned long esc_clk_rate;
294 u32 min_ths_settle, max_ths_settle, ths_settle_ns, esc_clk_period_ns;
295 const struct v4l2_mbus_framefmt *fmt;
296 const struct csi2_pix_format *csi2_fmt;
297
298 src_pad = media_entity_remote_source_pad_unique(&sd_state->sd->entity);
299 if (IS_ERR(src_pad)) {
300 dev_err(state->dev, "can't get source pad of %s (%ld)\n",
301 sd_state->sd->name, PTR_ERR(src_pad));
302 return PTR_ERR(src_pad);
303 }
304
305 /* Calculate the line rate from the pixel rate. */
306
307 fmt = v4l2_subdev_state_get_format(sd_state, MIPI_CSI2_PAD_SINK);
308 csi2_fmt = find_csi2_format(fmt->code);
309
310 link_freq = v4l2_get_link_freq(src_pad, csi2_fmt->width,
311 state->bus.num_data_lanes * 2);
312 if (link_freq < 0) {
313 dev_err(state->dev, "Unable to obtain link frequency: %d\n",
314 (int)link_freq);
315 return link_freq;
316 }
317
318 lane_rate = link_freq * 2;
319 if (lane_rate < 80000000 || lane_rate > 1500000000) {
320 dev_dbg(state->dev, "Out-of-bound lane rate %u\n", lane_rate);
321 return -EINVAL;
322 }
323
324 /*
325 * The D-PHY specification requires Ths-settle to be in the range
326 * 85ns + 6*UI to 140ns + 10*UI, with the unit interval UI being half
327 * the clock period.
328 *
329 * The Ths-settle value is expressed in the hardware as a multiple of
330 * the Esc clock period:
331 *
332 * Ths-settle = (PRG_RXHS_SETTLE + 1) * Tperiod of RxClkInEsc
333 *
334 * Due to the one cycle inaccuracy introduced by rounding, the
335 * documentation recommends picking a value away from the boundaries.
336 * Let's pick the average.
337 */
338 esc_clk_rate = clk_get_rate(state->clks[CSI2_CLK_ESC].clk);
339 if (!esc_clk_rate) {
340 dev_err(state->dev, "Could not get esc clock rate.\n");
341 return -EINVAL;
342 }
343
344 dev_dbg(state->dev, "esc clk rate: %lu\n", esc_clk_rate);
345 esc_clk_period_ns = 1000000000 / esc_clk_rate;
346
347 min_ths_settle = 85 + 6 * 1000000 / (lane_rate / 1000);
348 max_ths_settle = 140 + 10 * 1000000 / (lane_rate / 1000);
349 ths_settle_ns = (min_ths_settle + max_ths_settle) / 2;
350
351 *hs_settle = ths_settle_ns / esc_clk_period_ns - 1;
352
353 dev_dbg(state->dev, "lane rate %u Ths_settle %u hs_settle %u\n",
354 lane_rate, ths_settle_ns, *hs_settle);
355
356 return 0;
357 }
358
imx8mq_mipi_csi_start_stream(struct csi_state * state,struct v4l2_subdev_state * sd_state)359 static int imx8mq_mipi_csi_start_stream(struct csi_state *state,
360 struct v4l2_subdev_state *sd_state)
361 {
362 int ret;
363 u32 hs_settle = 0;
364
365 ret = imx8mq_mipi_csi_sw_reset(state);
366 if (ret)
367 return ret;
368
369 imx8mq_mipi_csi_set_params(state);
370 ret = imx8mq_mipi_csi_calc_hs_settle(state, sd_state, &hs_settle);
371 if (ret)
372 return ret;
373
374 regmap_update_bits(state->phy_gpr,
375 state->phy_gpr_reg,
376 0x3fff,
377 GPR_CSI2_1_RX_ENABLE |
378 GPR_CSI2_1_VID_INTFC_ENB |
379 GPR_CSI2_1_HSEL |
380 GPR_CSI2_1_CONT_CLK_MODE |
381 GPR_CSI2_1_S_PRG_RXHS_SETTLE(hs_settle));
382
383 return 0;
384 }
385
imx8mq_mipi_csi_stop_stream(struct csi_state * state)386 static void imx8mq_mipi_csi_stop_stream(struct csi_state *state)
387 {
388 imx8mq_mipi_csi_write(state, CSI2RX_CFG_DISABLE_DATA_LANES, 0xf);
389 }
390
391 /* -----------------------------------------------------------------------------
392 * V4L2 subdev operations
393 */
394
mipi_sd_to_csi2_state(struct v4l2_subdev * sdev)395 static struct csi_state *mipi_sd_to_csi2_state(struct v4l2_subdev *sdev)
396 {
397 return container_of(sdev, struct csi_state, sd);
398 }
399
imx8mq_mipi_csi_s_stream(struct v4l2_subdev * sd,int enable)400 static int imx8mq_mipi_csi_s_stream(struct v4l2_subdev *sd, int enable)
401 {
402 struct csi_state *state = mipi_sd_to_csi2_state(sd);
403 struct v4l2_subdev_state *sd_state;
404 int ret = 0;
405
406 if (enable) {
407 ret = pm_runtime_resume_and_get(state->dev);
408 if (ret < 0)
409 return ret;
410 }
411
412 mutex_lock(&state->lock);
413
414 if (enable) {
415 if (state->state & ST_SUSPENDED) {
416 ret = -EBUSY;
417 goto unlock;
418 }
419
420 sd_state = v4l2_subdev_lock_and_get_active_state(sd);
421 ret = imx8mq_mipi_csi_start_stream(state, sd_state);
422 v4l2_subdev_unlock_state(sd_state);
423
424 if (ret < 0)
425 goto unlock;
426
427 ret = v4l2_subdev_call(state->src_sd, video, s_stream, 1);
428 if (ret < 0)
429 goto unlock;
430
431 state->state |= ST_STREAMING;
432 } else {
433 v4l2_subdev_call(state->src_sd, video, s_stream, 0);
434 imx8mq_mipi_csi_stop_stream(state);
435 state->state &= ~ST_STREAMING;
436 }
437
438 unlock:
439 mutex_unlock(&state->lock);
440
441 if (!enable || ret < 0)
442 pm_runtime_put(state->dev);
443
444 return ret;
445 }
446
imx8mq_mipi_csi_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state)447 static int imx8mq_mipi_csi_init_state(struct v4l2_subdev *sd,
448 struct v4l2_subdev_state *sd_state)
449 {
450 struct v4l2_mbus_framefmt *fmt_sink;
451 struct v4l2_mbus_framefmt *fmt_source;
452
453 fmt_sink = v4l2_subdev_state_get_format(sd_state, MIPI_CSI2_PAD_SINK);
454 fmt_source = v4l2_subdev_state_get_format(sd_state,
455 MIPI_CSI2_PAD_SOURCE);
456
457 fmt_sink->code = MEDIA_BUS_FMT_SGBRG10_1X10;
458 fmt_sink->width = MIPI_CSI2_DEF_PIX_WIDTH;
459 fmt_sink->height = MIPI_CSI2_DEF_PIX_HEIGHT;
460 fmt_sink->field = V4L2_FIELD_NONE;
461
462 fmt_sink->colorspace = V4L2_COLORSPACE_RAW;
463 fmt_sink->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt_sink->colorspace);
464 fmt_sink->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt_sink->colorspace);
465 fmt_sink->quantization =
466 V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt_sink->colorspace,
467 fmt_sink->ycbcr_enc);
468
469 *fmt_source = *fmt_sink;
470
471 return 0;
472 }
473
imx8mq_mipi_csi_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)474 static int imx8mq_mipi_csi_enum_mbus_code(struct v4l2_subdev *sd,
475 struct v4l2_subdev_state *sd_state,
476 struct v4l2_subdev_mbus_code_enum *code)
477 {
478 /*
479 * We can't transcode in any way, the source format is identical
480 * to the sink format.
481 */
482 if (code->pad == MIPI_CSI2_PAD_SOURCE) {
483 struct v4l2_mbus_framefmt *fmt;
484
485 if (code->index > 0)
486 return -EINVAL;
487
488 fmt = v4l2_subdev_state_get_format(sd_state, code->pad);
489 code->code = fmt->code;
490 return 0;
491 }
492
493 if (code->pad != MIPI_CSI2_PAD_SINK)
494 return -EINVAL;
495
496 if (code->index >= ARRAY_SIZE(imx8mq_mipi_csi_formats))
497 return -EINVAL;
498
499 code->code = imx8mq_mipi_csi_formats[code->index].code;
500
501 return 0;
502 }
503
imx8mq_mipi_csi_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * sdformat)504 static int imx8mq_mipi_csi_set_fmt(struct v4l2_subdev *sd,
505 struct v4l2_subdev_state *sd_state,
506 struct v4l2_subdev_format *sdformat)
507 {
508 const struct csi2_pix_format *csi2_fmt;
509 struct v4l2_mbus_framefmt *fmt;
510
511 /*
512 * The device can't transcode in any way, the source format can't be
513 * modified.
514 */
515 if (sdformat->pad == MIPI_CSI2_PAD_SOURCE)
516 return v4l2_subdev_get_fmt(sd, sd_state, sdformat);
517
518 if (sdformat->pad != MIPI_CSI2_PAD_SINK)
519 return -EINVAL;
520
521 csi2_fmt = find_csi2_format(sdformat->format.code);
522 if (!csi2_fmt)
523 csi2_fmt = &imx8mq_mipi_csi_formats[0];
524
525 fmt = v4l2_subdev_state_get_format(sd_state, sdformat->pad);
526
527 fmt->code = csi2_fmt->code;
528 fmt->width = sdformat->format.width;
529 fmt->height = sdformat->format.height;
530
531 sdformat->format = *fmt;
532
533 /* Propagate the format from sink to source. */
534 fmt = v4l2_subdev_state_get_format(sd_state, MIPI_CSI2_PAD_SOURCE);
535 *fmt = sdformat->format;
536
537 return 0;
538 }
539
540 static const struct v4l2_subdev_video_ops imx8mq_mipi_csi_video_ops = {
541 .s_stream = imx8mq_mipi_csi_s_stream,
542 };
543
544 static const struct v4l2_subdev_pad_ops imx8mq_mipi_csi_pad_ops = {
545 .enum_mbus_code = imx8mq_mipi_csi_enum_mbus_code,
546 .get_fmt = v4l2_subdev_get_fmt,
547 .set_fmt = imx8mq_mipi_csi_set_fmt,
548 };
549
550 static const struct v4l2_subdev_ops imx8mq_mipi_csi_subdev_ops = {
551 .video = &imx8mq_mipi_csi_video_ops,
552 .pad = &imx8mq_mipi_csi_pad_ops,
553 };
554
555 static const struct v4l2_subdev_internal_ops imx8mq_mipi_csi_internal_ops = {
556 .init_state = imx8mq_mipi_csi_init_state,
557 };
558
559 /* -----------------------------------------------------------------------------
560 * Media entity operations
561 */
562
563 static const struct media_entity_operations imx8mq_mipi_csi_entity_ops = {
564 .link_validate = v4l2_subdev_link_validate,
565 .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
566 };
567
568 /* -----------------------------------------------------------------------------
569 * Async subdev notifier
570 */
571
572 static struct csi_state *
mipi_notifier_to_csi2_state(struct v4l2_async_notifier * n)573 mipi_notifier_to_csi2_state(struct v4l2_async_notifier *n)
574 {
575 return container_of(n, struct csi_state, notifier);
576 }
577
imx8mq_mipi_csi_notify_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * sd,struct v4l2_async_connection * asd)578 static int imx8mq_mipi_csi_notify_bound(struct v4l2_async_notifier *notifier,
579 struct v4l2_subdev *sd,
580 struct v4l2_async_connection *asd)
581 {
582 struct csi_state *state = mipi_notifier_to_csi2_state(notifier);
583 struct media_pad *sink = &state->sd.entity.pads[MIPI_CSI2_PAD_SINK];
584
585 state->src_sd = sd;
586
587 return v4l2_create_fwnode_links_to_pad(sd, sink, MEDIA_LNK_FL_ENABLED |
588 MEDIA_LNK_FL_IMMUTABLE);
589 }
590
591 static const struct v4l2_async_notifier_operations imx8mq_mipi_csi_notify_ops = {
592 .bound = imx8mq_mipi_csi_notify_bound,
593 };
594
imx8mq_mipi_csi_async_register(struct csi_state * state)595 static int imx8mq_mipi_csi_async_register(struct csi_state *state)
596 {
597 struct v4l2_fwnode_endpoint vep = {
598 .bus_type = V4L2_MBUS_CSI2_DPHY,
599 };
600 struct v4l2_async_connection *asd;
601 struct fwnode_handle *ep;
602 unsigned int i;
603 int ret;
604
605 v4l2_async_subdev_nf_init(&state->notifier, &state->sd);
606
607 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(state->dev), 0, 0,
608 FWNODE_GRAPH_ENDPOINT_NEXT);
609 if (!ep)
610 return -ENOTCONN;
611
612 ret = v4l2_fwnode_endpoint_parse(ep, &vep);
613 if (ret)
614 goto err_parse;
615
616 for (i = 0; i < vep.bus.mipi_csi2.num_data_lanes; ++i) {
617 if (vep.bus.mipi_csi2.data_lanes[i] != i + 1) {
618 dev_err(state->dev,
619 "data lanes reordering is not supported");
620 ret = -EINVAL;
621 goto err_parse;
622 }
623 }
624
625 state->bus = vep.bus.mipi_csi2;
626
627 dev_dbg(state->dev, "data lanes: %d flags: 0x%08x\n",
628 state->bus.num_data_lanes,
629 state->bus.flags);
630
631 asd = v4l2_async_nf_add_fwnode_remote(&state->notifier, ep,
632 struct v4l2_async_connection);
633 if (IS_ERR(asd)) {
634 ret = PTR_ERR(asd);
635 goto err_parse;
636 }
637
638 fwnode_handle_put(ep);
639
640 state->notifier.ops = &imx8mq_mipi_csi_notify_ops;
641
642 ret = v4l2_async_nf_register(&state->notifier);
643 if (ret)
644 return ret;
645
646 return v4l2_async_register_subdev(&state->sd);
647
648 err_parse:
649 fwnode_handle_put(ep);
650
651 return ret;
652 }
653
654 /* -----------------------------------------------------------------------------
655 * Suspend/resume
656 */
657
imx8mq_mipi_csi_pm_suspend(struct device * dev)658 static void imx8mq_mipi_csi_pm_suspend(struct device *dev)
659 {
660 struct v4l2_subdev *sd = dev_get_drvdata(dev);
661 struct csi_state *state = mipi_sd_to_csi2_state(sd);
662
663 mutex_lock(&state->lock);
664
665 if (state->state & ST_POWERED) {
666 imx8mq_mipi_csi_stop_stream(state);
667 imx8mq_mipi_csi_clk_disable(state);
668 state->state &= ~ST_POWERED;
669 }
670
671 mutex_unlock(&state->lock);
672 }
673
imx8mq_mipi_csi_pm_resume(struct device * dev)674 static int imx8mq_mipi_csi_pm_resume(struct device *dev)
675 {
676 struct v4l2_subdev *sd = dev_get_drvdata(dev);
677 struct csi_state *state = mipi_sd_to_csi2_state(sd);
678 struct v4l2_subdev_state *sd_state;
679 int ret = 0;
680
681 mutex_lock(&state->lock);
682
683 if (!(state->state & ST_POWERED)) {
684 state->state |= ST_POWERED;
685 ret = imx8mq_mipi_csi_clk_enable(state);
686 }
687 if (state->state & ST_STREAMING) {
688 sd_state = v4l2_subdev_lock_and_get_active_state(sd);
689 ret = imx8mq_mipi_csi_start_stream(state, sd_state);
690 v4l2_subdev_unlock_state(sd_state);
691 if (ret)
692 goto unlock;
693 }
694
695 state->state &= ~ST_SUSPENDED;
696
697 unlock:
698 mutex_unlock(&state->lock);
699
700 return ret ? -EAGAIN : 0;
701 }
702
imx8mq_mipi_csi_suspend(struct device * dev)703 static int imx8mq_mipi_csi_suspend(struct device *dev)
704 {
705 struct v4l2_subdev *sd = dev_get_drvdata(dev);
706 struct csi_state *state = mipi_sd_to_csi2_state(sd);
707
708 imx8mq_mipi_csi_pm_suspend(dev);
709
710 state->state |= ST_SUSPENDED;
711
712 return 0;
713 }
714
imx8mq_mipi_csi_resume(struct device * dev)715 static int imx8mq_mipi_csi_resume(struct device *dev)
716 {
717 struct v4l2_subdev *sd = dev_get_drvdata(dev);
718 struct csi_state *state = mipi_sd_to_csi2_state(sd);
719
720 if (!(state->state & ST_SUSPENDED))
721 return 0;
722
723 return imx8mq_mipi_csi_pm_resume(dev);
724 }
725
imx8mq_mipi_csi_runtime_suspend(struct device * dev)726 static int imx8mq_mipi_csi_runtime_suspend(struct device *dev)
727 {
728 struct v4l2_subdev *sd = dev_get_drvdata(dev);
729 struct csi_state *state = mipi_sd_to_csi2_state(sd);
730 int ret;
731
732 imx8mq_mipi_csi_pm_suspend(dev);
733
734 ret = icc_set_bw(state->icc_path, 0, 0);
735 if (ret)
736 dev_err(dev, "icc_set_bw failed with %d\n", ret);
737
738 return ret;
739 }
740
imx8mq_mipi_csi_runtime_resume(struct device * dev)741 static int imx8mq_mipi_csi_runtime_resume(struct device *dev)
742 {
743 struct v4l2_subdev *sd = dev_get_drvdata(dev);
744 struct csi_state *state = mipi_sd_to_csi2_state(sd);
745 int ret;
746
747 ret = icc_set_bw(state->icc_path, 0, state->icc_path_bw);
748 if (ret) {
749 dev_err(dev, "icc_set_bw failed with %d\n", ret);
750 return ret;
751 }
752
753 return imx8mq_mipi_csi_pm_resume(dev);
754 }
755
756 static const struct dev_pm_ops imx8mq_mipi_csi_pm_ops = {
757 RUNTIME_PM_OPS(imx8mq_mipi_csi_runtime_suspend,
758 imx8mq_mipi_csi_runtime_resume, NULL)
759 SYSTEM_SLEEP_PM_OPS(imx8mq_mipi_csi_suspend, imx8mq_mipi_csi_resume)
760 };
761
762 /* -----------------------------------------------------------------------------
763 * Probe/remove & platform driver
764 */
765
imx8mq_mipi_csi_subdev_init(struct csi_state * state)766 static int imx8mq_mipi_csi_subdev_init(struct csi_state *state)
767 {
768 struct v4l2_subdev *sd = &state->sd;
769 int ret;
770
771 v4l2_subdev_init(sd, &imx8mq_mipi_csi_subdev_ops);
772 sd->internal_ops = &imx8mq_mipi_csi_internal_ops;
773 sd->owner = THIS_MODULE;
774 snprintf(sd->name, sizeof(sd->name), "%s %s",
775 MIPI_CSI2_SUBDEV_NAME, dev_name(state->dev));
776
777 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
778
779 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
780 sd->entity.ops = &imx8mq_mipi_csi_entity_ops;
781
782 sd->dev = state->dev;
783
784 state->pads[MIPI_CSI2_PAD_SINK].flags = MEDIA_PAD_FL_SINK
785 | MEDIA_PAD_FL_MUST_CONNECT;
786 state->pads[MIPI_CSI2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE
787 | MEDIA_PAD_FL_MUST_CONNECT;
788 ret = media_entity_pads_init(&sd->entity, MIPI_CSI2_PADS_NUM,
789 state->pads);
790 if (ret)
791 return ret;
792
793 ret = v4l2_subdev_init_finalize(sd);
794 if (ret) {
795 media_entity_cleanup(&sd->entity);
796 return ret;
797 }
798
799 return 0;
800 }
801
imx8mq_mipi_csi_release_icc(struct platform_device * pdev)802 static void imx8mq_mipi_csi_release_icc(struct platform_device *pdev)
803 {
804 struct v4l2_subdev *sd = dev_get_drvdata(&pdev->dev);
805 struct csi_state *state = mipi_sd_to_csi2_state(sd);
806
807 icc_put(state->icc_path);
808 }
809
imx8mq_mipi_csi_init_icc(struct platform_device * pdev)810 static int imx8mq_mipi_csi_init_icc(struct platform_device *pdev)
811 {
812 struct v4l2_subdev *sd = dev_get_drvdata(&pdev->dev);
813 struct csi_state *state = mipi_sd_to_csi2_state(sd);
814
815 /* Optional interconnect request */
816 state->icc_path = of_icc_get(&pdev->dev, "dram");
817 if (IS_ERR_OR_NULL(state->icc_path))
818 return PTR_ERR_OR_ZERO(state->icc_path);
819
820 state->icc_path_bw = MBps_to_icc(700);
821
822 return 0;
823 }
824
imx8mq_mipi_csi_parse_dt(struct csi_state * state)825 static int imx8mq_mipi_csi_parse_dt(struct csi_state *state)
826 {
827 struct device *dev = state->dev;
828 struct device_node *np = state->dev->of_node;
829 struct device_node *node;
830 phandle ph;
831 u32 out_val[2];
832 int ret = 0;
833
834 state->rst = devm_reset_control_array_get_exclusive(dev);
835 if (IS_ERR(state->rst)) {
836 dev_err(dev, "Failed to get reset: %pe\n", state->rst);
837 return PTR_ERR(state->rst);
838 }
839
840 ret = of_property_read_u32_array(np, "fsl,mipi-phy-gpr", out_val,
841 ARRAY_SIZE(out_val));
842 if (ret) {
843 dev_err(dev, "no fsl,mipi-phy-gpr property found: %d\n", ret);
844 return ret;
845 }
846
847 ph = *out_val;
848
849 node = of_find_node_by_phandle(ph);
850 if (!node) {
851 dev_err(dev, "Error finding node by phandle\n");
852 return -ENODEV;
853 }
854 state->phy_gpr = syscon_node_to_regmap(node);
855 of_node_put(node);
856 if (IS_ERR(state->phy_gpr)) {
857 dev_err(dev, "failed to get gpr regmap: %pe\n", state->phy_gpr);
858 return PTR_ERR(state->phy_gpr);
859 }
860
861 state->phy_gpr_reg = out_val[1];
862 dev_dbg(dev, "phy gpr register set to 0x%x\n", state->phy_gpr_reg);
863
864 return ret;
865 }
866
imx8mq_mipi_csi_probe(struct platform_device * pdev)867 static int imx8mq_mipi_csi_probe(struct platform_device *pdev)
868 {
869 struct device *dev = &pdev->dev;
870 struct csi_state *state;
871 int ret;
872
873 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
874 if (!state)
875 return -ENOMEM;
876
877 state->dev = dev;
878
879 ret = imx8mq_mipi_csi_parse_dt(state);
880 if (ret < 0) {
881 dev_err(dev, "Failed to parse device tree: %d\n", ret);
882 return ret;
883 }
884
885 /* Acquire resources. */
886 state->regs = devm_platform_ioremap_resource(pdev, 0);
887 if (IS_ERR(state->regs))
888 return PTR_ERR(state->regs);
889
890 ret = imx8mq_mipi_csi_clk_get(state);
891 if (ret < 0)
892 return ret;
893
894 platform_set_drvdata(pdev, &state->sd);
895
896 mutex_init(&state->lock);
897
898 ret = imx8mq_mipi_csi_subdev_init(state);
899 if (ret < 0)
900 goto mutex;
901
902 ret = imx8mq_mipi_csi_init_icc(pdev);
903 if (ret)
904 goto mutex;
905
906 /* Enable runtime PM. */
907 pm_runtime_enable(dev);
908 if (!pm_runtime_enabled(dev)) {
909 ret = imx8mq_mipi_csi_runtime_resume(dev);
910 if (ret < 0)
911 goto icc;
912 }
913
914 ret = imx8mq_mipi_csi_async_register(state);
915 if (ret < 0)
916 goto cleanup;
917
918 return 0;
919
920 cleanup:
921 pm_runtime_disable(&pdev->dev);
922 imx8mq_mipi_csi_runtime_suspend(&pdev->dev);
923
924 media_entity_cleanup(&state->sd.entity);
925 v4l2_subdev_cleanup(&state->sd);
926 v4l2_async_nf_unregister(&state->notifier);
927 v4l2_async_nf_cleanup(&state->notifier);
928 v4l2_async_unregister_subdev(&state->sd);
929 icc:
930 imx8mq_mipi_csi_release_icc(pdev);
931 mutex:
932 mutex_destroy(&state->lock);
933
934 return ret;
935 }
936
imx8mq_mipi_csi_remove(struct platform_device * pdev)937 static void imx8mq_mipi_csi_remove(struct platform_device *pdev)
938 {
939 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
940 struct csi_state *state = mipi_sd_to_csi2_state(sd);
941
942 v4l2_async_nf_unregister(&state->notifier);
943 v4l2_async_nf_cleanup(&state->notifier);
944 v4l2_async_unregister_subdev(&state->sd);
945
946 pm_runtime_disable(&pdev->dev);
947 imx8mq_mipi_csi_runtime_suspend(&pdev->dev);
948 media_entity_cleanup(&state->sd.entity);
949 v4l2_subdev_cleanup(&state->sd);
950 mutex_destroy(&state->lock);
951 pm_runtime_set_suspended(&pdev->dev);
952 imx8mq_mipi_csi_release_icc(pdev);
953 }
954
955 static const struct of_device_id imx8mq_mipi_csi_of_match[] = {
956 { .compatible = "fsl,imx8mq-mipi-csi2", },
957 { /* sentinel */ },
958 };
959 MODULE_DEVICE_TABLE(of, imx8mq_mipi_csi_of_match);
960
961 static struct platform_driver imx8mq_mipi_csi_driver = {
962 .probe = imx8mq_mipi_csi_probe,
963 .remove = imx8mq_mipi_csi_remove,
964 .driver = {
965 .of_match_table = imx8mq_mipi_csi_of_match,
966 .name = MIPI_CSI2_DRIVER_NAME,
967 .pm = pm_ptr(&imx8mq_mipi_csi_pm_ops),
968 },
969 };
970
971 module_platform_driver(imx8mq_mipi_csi_driver);
972
973 MODULE_DESCRIPTION("i.MX8MQ MIPI CSI-2 receiver driver");
974 MODULE_AUTHOR("Martin Kepplinger <martin.kepplinger@puri.sm>");
975 MODULE_LICENSE("GPL v2");
976 MODULE_ALIAS("platform:imx8mq-mipi-csi2");
977